CN116073829A - LMS foreground calibration method and system of successive approximation type ADC - Google Patents

LMS foreground calibration method and system of successive approximation type ADC Download PDF

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CN116073829A
CN116073829A CN202310206695.8A CN202310206695A CN116073829A CN 116073829 A CN116073829 A CN 116073829A CN 202310206695 A CN202310206695 A CN 202310206695A CN 116073829 A CN116073829 A CN 116073829A
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offset
digital
adc
cdac
weight
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郑呈晔
石玉转
孙杰
王成华
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Nanjing University of Aeronautics and Astronautics
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Nanjing University of Aeronautics and Astronautics
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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Abstract

The invention provides a LMS foreground calibration method and system of successive approximation type ADC, wherein the method comprises that a pseudo random signal or a sequence signal is utilized to generate any sequence to toggle CDAC so that the CDAC generates an analog signal; the method comprises the steps of firstly dialing 1 and then dialing 0 by utilizing a target capacitor in a capacitor array, so that analog signals of upper polar plates of all capacitors in the capacitor array are respectively provided with two offset quantities with the same size and opposite polarities; quantizing two analog signals with offset to obtain two quantized results; multiplying the two digital results with the target capacitance weight respectively to obtain two digital results; calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset; and adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset. The method solves the problem that the background calibration LMS algorithm needs to reduce the conversion speed of the ADC by half, can calculate the capacitance weight of each bit, and improves the calibration precision.

Description

LMS foreground calibration method and system of successive approximation type ADC
Technical Field
The invention belongs to the technical field of analog-to-digital conversion, and particularly relates to an LMS foreground calibration method and system of a successive approximation type ADC.
Background
The successive approximation (Successive Approximation Register, SAR) analog-to-digital converter (Analog to Digital Converter, ADC) can achieve both ADC accuracy and chip power consumption and area without the need for a residual amplifier and a multi-bit comparator by using a dichotomy. However, non-ideal factors such as nonlinearity of a capacitor digital-to-analog converter (Capacitor Digital to Analog Converter, CDAC) in the SAR ADC severely limit the SAR ADC to realize high precision, and error reference voltage is generated when the reference voltage is changed every time the capacitor is shifted by taking capacitance mismatch and layout parasitism into consideration if each bit of comparison result still adopts the traditional binary capacitor weight. Because the mismatch of the capacitors is random, the capacitor stirred by each comparison result is likely to be larger or smaller, so that the residual transfer curve of the ADC has different offsets at different results, the linearity of the ADC is greatly deteriorated, and meanwhile, the mismatch of the high-order capacitor directly influences the effective digits of the ADC. The conventional foreground capacitance calibration method often needs to use a low-order capacitance array to quantify the mismatch generated by a high-order capacitance, so that the mismatch of the low-order capacitance is not calibrated, inaccurate results are overlapped on each to-be-calibrated capacitance, and the calibration accuracy is limited.
The least mean square (Least Mean Square, LMS) algorithm is often used in background capacitance calibration, and the input signal is compared after being quantized by two different paths to obtain an error result, and the error result is iteratively calibrated, and the calibration range can be expanded to each bit of capacitance along with the change of the input signal. However, twice quantization in background calibration necessarily results in halving the ADC conversion speed, and each quantization needs to be calibrated to increase the power consumption and hardware cost of the circuit.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides an LMS foreground calibration method and system of a successive approximation type ADC.
In a first aspect, the present invention provides a LMS foreground calibration method for a successive approximation ADC, comprising:
generating any sequence by using the pseudo-random signal or the sequence signal to stir the CDAC so that the CDAC generates an analog signal covering the range of the ADC part;
the method comprises the steps of firstly dialing 1 and then dialing 0 by utilizing a target capacitor in a capacitor array, so that analog signals of upper polar plates of all capacitors in the capacitor array are respectively provided with two offset quantities with the same size and opposite polarities; the offset exists in the analog signal in the form of offset voltage;
quantizing two analog signals with offset to obtain two quantized results;
multiplying the two quantized results with the target capacitance weight respectively to obtain two digital results;
calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset;
and adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset to make the change quantity of the target capacitor proportional to the deviation, wherein the deviation and the preset offset reach a convergence stable state.
Further, the generating any sequence of toggling CDAC using pseudo-random signals or sequential signals to cause the CDAC to generate analog signals covering the ADC part range includes:
the analog signal is calculated according to the following formula:
Figure SMS_1
；
wherein ,
Figure SMS_3
is an analog signal;
Figure SMS_6
Is the first of the digital calibration signalsiThe value of the bit;
Figure SMS_9
Differential pair positive pole of CDAC array>
Figure SMS_2
A plurality of capacitors;
Figure SMS_5
Negative pole of CDAC array differential pair +.>
Figure SMS_8
A plurality of capacitors;
Figure SMS_10
For CDAC array differential pair positive total capacitance, < >>
Figure SMS_4
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure SMS_7
Is the total number of capacitors in the capacitor array.
Further, the calculating the deviation between the difference value of the two digital results and the digital quantity corresponding to the preset offset includes:
calculating the deviation of the difference value of the two digital results and the digital quantity of the preset offset according to the following formula:
Figure SMS_11
；
wherein ,
Figure SMS_19
is->
Figure SMS_13
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure SMS_22
Is->
Figure SMS_15
During secondary calibration, the +.>
Figure SMS_23
The weight of the individual capacitances;
Figure SMS_16
Is->
Figure SMS_27
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_14
Quantization is performed at->
Figure SMS_26
A bit result;
Figure SMS_12
Is the offset;
Figure SMS_21
Is->
Figure SMS_20
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_25
Quantization is performed at->
Figure SMS_18
A bit result;
Figure SMS_24
Is an offset +.>
Figure SMS_17
Corresponding digital quantities.
Further, the adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset to make the change of the target capacitor proportional to the deviation, and the deviation and the preset offset reach the convergence stable state includes:
the weight of the adjusted target capacitance is calculated according to the following formula:
Figure SMS_28
；
wherein ,
Figure SMS_29
is->
Figure SMS_30
During secondary calibration, the +.>
Figure SMS_31
The weight of the individual capacitances;
Figure SMS_32
Step length is adjusted for the weight;
calculating the number corresponding to the adjusted preset offset according to the following formula:
Figure SMS_33
；
wherein ,
Figure SMS_34
is->
Figure SMS_35
Offset +.>
Figure SMS_36
Corresponding digital quantity, < > for>
Figure SMS_37
Is->
Figure SMS_38
Offset +.>
Figure SMS_39
Corresponding digital quantities.
In a second aspect, the present invention provides an LMS foreground calibration system for a successive approximation ADC comprising:
the signal generation module is used for generating any sequence by utilizing the pseudo-random signal or the sequence signal to stir the CDAC so as to enable the CDAC to generate an analog signal covering the range of the ADC part;
the offset generating module is used for firstly shifting 1 and then shifting 0 by utilizing a target capacitor in the capacitor array, so that analog signals of all upper electrode plates of the capacitors in the capacitor array are respectively provided with two offsets with the same size and opposite polarities; the offset exists in the analog signal in the form of offset voltage;
the signal quantization module is used for quantizing two analog signals with offset to obtain two quantized results;
the first calculation module is used for multiplying the two quantized results with the target capacitance weight respectively to obtain two digital results;
the second calculation module is used for calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset;
the adjusting module is used for adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset, so that the change quantity of the target capacitor is in direct proportion to the deviation, and the deviation and the preset offset reach a convergence stable state.
Further, the signal generating module includes:
a first calculation unit for calculating an analog signal according to the following formula:
Figure SMS_40
；
wherein ,
Figure SMS_42
is an analog signal;
Figure SMS_45
Is the +.>
Figure SMS_47
The value of the bit;
Figure SMS_43
Differential pair positive pole of CDAC array>
Figure SMS_46
A plurality of capacitors;
Figure SMS_49
Negative pole of CDAC array differential pair +.>
Figure SMS_50
A plurality of capacitors;
Figure SMS_41
For CDAC array differential pair positive total capacitance, < >>
Figure SMS_44
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure SMS_48
Is the total number of capacitors in the capacitor array.
Further, the second computing module includes:
a second calculating unit for calculating the deviation of the difference between the two digital results and the digital quantity of the preset offset according to the following formula:
Figure SMS_51
；
wherein ,
Figure SMS_58
is->
Figure SMS_54
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure SMS_61
Is->
Figure SMS_56
During secondary calibration, the +.>
Figure SMS_63
The weight of the individual capacitances;
Figure SMS_57
Is->
Figure SMS_62
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_59
Quantization is performed at->
Figure SMS_67
A bit result;
Figure SMS_52
Is the offset;
Figure SMS_64
Is->
Figure SMS_60
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_66
Quantization is performed at->
Figure SMS_55
A bit result;
Figure SMS_65
Is an offset +.>
Figure SMS_53
Corresponding digital quantities.
Further, the adjustment module includes:
a third calculation unit for calculating the weight of the adjusted target capacitance according to the following formula:
Figure SMS_68
；
wherein ,
Figure SMS_69
is->
Figure SMS_70
During secondary calibration, the +.>
Figure SMS_71
The weight of the individual capacitances;
Figure SMS_72
Step length is adjusted for the weight;
a fourth calculation unit, configured to calculate a digital quantity corresponding to the adjusted preset offset according to the following formula:
Figure SMS_73
；
wherein ,
Figure SMS_74
is->
Figure SMS_75
Offset +.>
Figure SMS_76
Corresponding digital quantity, < > for>
Figure SMS_77
Is->
Figure SMS_78
Offset +.>
Figure SMS_79
Corresponding digital quantities.
In a third aspect, the present invention provides a computer device comprising a processor and a memory; the steps of the LMS foreground calibration method of the successive approximation type ADC in the first aspect are realized when the processor executes a computer program stored in a memory.
In a fourth aspect, the present invention provides a computer-readable storage medium for storing a computer program; the computer program when executed by a processor implements the steps of the LMS foreground calibration method of a successive approximation ADC of the first aspect.
The invention provides a LMS foreground calibration method and system of successive approximation type ADC, wherein the method comprises that a pseudo random signal or a sequence signal is utilized to generate any sequence to stir CDAC, so that the CDAC generates an analog signal covering the range of the ADC part; the method comprises the steps of firstly dialing 1 and then dialing 0 by utilizing a target capacitor in a capacitor array, so that analog signals of upper polar plates of all capacitors in the capacitor array are respectively provided with two offset quantities with the same size and opposite polarities; the offset exists in the analog signal in the form of offset voltage; quantizing two analog signals with offset to obtain two quantized results; multiplying the two digital results with the target capacitance weight respectively to obtain two digital results; calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset; and adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset to make the change quantity of the target capacitor proportional to the deviation, wherein the deviation and the preset offset reach a convergence stable state.
When the foreground is calibrated, the pseudo-random signal is utilized to randomly stir or the sequence generator is utilized to sequentially stir the CDAC to generate an input signal of the SAR ADC, an LMS algorithm is utilized, the capacitance weight is gradually adjusted and iterated through comparing the deviation between the actual value and the ideal value, and finally, the accurate capacitance weight value is calculated, so that errors caused by capacitance mismatch are eliminated. According to the invention, the capacitance is calibrated only by utilizing the LMS algorithm in the foreground, twice quantization is not needed in the working process of the ADC, the problem that the conversion speed of the ADC needs to be reduced by the LMS algorithm in the background calibration is avoided, in addition, the weight of each capacitance can be calculated, the problem that the low-order capacitance cannot be calibrated in the traditional foreground calibration is solved, the error of the low-order capacitance cannot influence the calibration precision, and the calibration precision is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an LMS foreground calibration method of a successive approximation ADC according to an embodiment of the present invention;
fig. 2 is a block diagram of an LMS foreground calibration method of a successive approximation ADC according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a foreground calibration signal generation portion according to an embodiment of the present invention;
fig. 4 is a graph of a convergence result of a capacitance weight error simulated by an LMS algorithm in MATLAB, wherein the capacitance mismatch is 5% provided by the embodiment of the present invention;
fig. 5 is a graph of a Δd convergence result of an LMS algorithm in MATLAB simulation, with a capacitance mismatch of 5% provided by an embodiment of the present invention;
FIG. 6 is a graph of the convergence result of the LMS algorithm on the first bit capacitance simulated by MATLAB, wherein the mismatch of the capacitance is 5% provided by the embodiment of the invention;
FIG. 7 is a graph of a second bit capacitance convergence result of an LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the invention;
FIG. 8 is a graph of a third-bit capacitance convergence result of the LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the invention;
FIG. 9 is a graph of a fourth bit capacitance convergence result of the LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the invention;
fig. 10 is a diagram of a fifth capacitor convergence result of the LMS algorithm in MATLAB simulation, where the capacitor mismatch provided by the embodiment of the present invention is 5%;
FIG. 11 is a graph of a sixth-bit capacitance convergence result of the LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the invention;
fig. 12 is a graph of a seventh capacitance convergence result of 5% of capacitance mismatch provided by the embodiment of the present invention, where the MATLAB simulation is performed by the LMS algorithm;
fig. 13 is a graph of a capacitance convergence result of an eighth bit of an LMS algorithm in MATLAB simulation, where the capacitance mismatch provided by the embodiment of the present invention is 5%;
fig. 14 is a graph of a ninth-bit capacitance convergence result of the LMS algorithm in MATLAB simulation, where the capacitance mismatch provided by the embodiment of the present invention is 5%;
fig. 15 is a graph of a tenth capacitor convergence result of an LMS algorithm in MATLAB simulation, where the capacitor mismatch provided by the embodiment of the present invention is 5%;
FIG. 16 is a graph of the eleventh capacitance convergence result of the LMS algorithm in MATLAB simulation, with a capacitance mismatch of 5% provided by an embodiment of the present invention;
FIG. 17 is a graph of a twelfth-bit capacitance convergence result of an LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the invention;
FIG. 18 is a graph of a thirteenth capacitance convergence result of the LMS algorithm in MATLAB simulation, with a capacitance mismatch of 5% provided by an embodiment of the present invention;
FIG. 19 is a graph of a fourteenth bit capacitance convergence result of an LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the present invention;
FIG. 20 is a graph of a fifteenth capacitance convergence result of an LMS algorithm in MATLAB simulation, with a capacitance mismatch of 5% provided by an embodiment of the present invention;
FIG. 21 is a graph of a sixteenth-bit capacitance convergence result of an LMS algorithm in MATLAB simulation, wherein the capacitance mismatch is 5% in the embodiment of the present invention;
FIG. 22 is a graph of the result of a fast Fourier transform of an output signal simulated in MATLAB using an ideal capacitance weight, with a capacitance mismatch of 5% provided by an embodiment of the present invention;
FIG. 23 is a graph of the result of a fast Fourier transform of the output signal simulated in MATLAB using calibrated capacitance weights at a capacitance mismatch of 5% provided by an embodiment of the present invention;
fig. 24 is a flowchart of an LMS foreground calibration system for a successive approximation ADC according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In an embodiment, as shown in fig. 1 and fig. 2, an embodiment of the present invention provides an LMS foreground calibration method of a successive approximation ADC, including:
101, generating any sequence by using pseudo-random signals or sequential signals to toggle the CDAC so that the CDAC generates analog signals covering the range of the ADC part.
In an SAR ADC with an accuracy of N bits, when a pseudo-random signal randomly toggles its CDAC capacitor array, the CDAC will be randomly generated
Figure SMS_80
Different analog signals.
Illustratively, the analog signal is calculated according to the following formula:
Figure SMS_81
。
wherein ,
Figure SMS_83
is an analog signal;
Figure SMS_86
Is the +.>
Figure SMS_90
The value of the bit;
Figure SMS_84
Differential pair positive pole of CDAC array>
Figure SMS_87
A plurality of capacitors;
Figure SMS_89
Negative pole of CDAC array differential pair +.>
Figure SMS_91
A plurality of capacitors;
Figure SMS_82
For CDAC array differential pair positive total capacitance, < >>
Figure SMS_85
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure SMS_88
Is the total number of capacitors in the capacitor array.
102, firstly dialing 1 and then dialing 0 by utilizing a target capacitor in the capacitor array, so that analog signals of all upper electrode plates of the capacitors in the capacitor array are respectively provided with two offset amounts with the same size and opposite polarities; the offset exists in the analog signal in the form of an offset voltage.
The input signal of the SAR ADC is generated by randomly toggling the CDAC capacitor with a Pseudo-Noise (PN) signal or sequentially toggling the CDAC capacitor with a sequencer. As shown in FIG. 3, the pseudo random signal generator is used to randomly toggle the capacitors to generate analog input signals, the sequence generator is composed of linear feedback shift registers (Linear Feedback Shifting Register, LFSR) (or composed of sequential sequence generator, according to the use scenario), pseudo random numbers of M sequences can be generated, when the sequence generator generates such sequences as 0111100110111001, the corresponding capacitors C1, C2, C5, C8, C9, C11, C12, C13 and C16 are respectively toggled to "1" (the embodiment of the invention is based on Vcm-based algorithm, the Vref is toggled, different switching algorithms can be selected according to the use scenario), the rest bit capacitors are respectively toggled to "0" (toggled Gnd), so that analog signals corresponding to the sequences in CDAC are generated, and when in the capacitor array, additional capacitors Cos (CDAC self bit weight capacitors can be used as Cos) are respectively toggled to "1" and "0", the analog signals have the same offset of opposite polarities
Figure SMS_92
。
103, quantizing the two analog signals with the offset to obtain two quantized results.
After the two analog signals with offset are quantized by ADC, quantization results 1000011011100011 and 0110001001000000 are obtained.
104, multiplying the two quantized results by the target capacitance weight respectively to obtain two digital results.
And 105, calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset.
Illustratively, the deviation of the difference of the two digital results from the digital quantity of the preset offset is calculated according to the following formula:
Figure SMS_93
。
wherein ,
Figure SMS_101
is->
Figure SMS_96
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure SMS_106
Is->
Figure SMS_100
During secondary calibration, the +.>
Figure SMS_105
The weight of the individual capacitances;
Figure SMS_97
Is->
Figure SMS_104
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_95
Quantization is performed at->
Figure SMS_103
A bit result;
Figure SMS_94
Is the offset;
Figure SMS_109
Is->
Figure SMS_102
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_108
Quantization is performed at->
Figure SMS_99
A bit result;
Figure SMS_107
Is an offset +.>
Figure SMS_98
Corresponding digital quantities.
The result of the digital quantity corresponding to the two analog signals is differenced and doubled
Figure SMS_110
Subtracting the error amount caused by the capacitance weighterror=0.0003.
106, adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset, so that the change quantity of the target capacitor is in direct proportion to the deviation, and the deviation and the preset offset reach a convergence stable state.
Illustratively, the weight of the adjusted target capacitance is calculated according to the following formula:
Figure SMS_111
。
wherein ,
Figure SMS_112
is->
Figure SMS_113
During secondary calibration, the +.>
Figure SMS_114
The weight of the individual capacitances;
Figure SMS_115
The step size is adjusted for the weight.
Calculating the number corresponding to the adjusted preset offset according to the following formula:
Figure SMS_116
。
wherein ,
Figure SMS_117
is->
Figure SMS_118
Offset +.>
Figure SMS_119
Corresponding digital quantity, < > for>
Figure SMS_120
Is->
Figure SMS_121
Offset +.>
Figure SMS_122
Corresponding digital quantities.
Because the actual capacitance weight of the capacitance array is different from the ideal capacitance weight, the difference between the quantized result of the two signals and the multiplied result of the ideal capacitance weight is different from the actual value, and therefore the deviation between the current capacitance weight and the ideal capacitance weight can be obtained. According to the LMS algorithm, the capacitance weight is iteratively modified according to the deviation until the two are no longer different, namely error converges to 0, so that the actual capacitance weight is obtained. Because of storage in digital circuits
Figure SMS_123
Signal and->
Figure SMS_124
There is also a mismatch and therefore a corresponding adjustment of +.>
Figure SMS_125
Is of a size of (a) and (b).
If it iserrorIs positive and
Figure SMS_127
the target capacitance weight is reduced, and the digital quantity corresponding to the offset is increased>
Figure SMS_130
The method comprises the steps of carrying out a first treatment on the surface of the If it iserrorIs positive and +.>
Figure SMS_131
The weight of the target capacitance is increased, and the digital quantity corresponding to the offset is increased
Figure SMS_128
The method comprises the steps of carrying out a first treatment on the surface of the If it iserrorIs negative and->
Figure SMS_129
The weight of the target capacitance is increased, and the digital quantity corresponding to the offset is reduced
Figure SMS_132
The method comprises the steps of carrying out a first treatment on the surface of the If it iserrorIs negative and->
Figure SMS_133
The weight of the target capacitance is reduced, and the digital quantity corresponding to the offset is reduced
Figure SMS_126
。
In the quantization results, the quantization results corresponding to the capacitors C4, C5, C7, C8, C10, C12, C13 and C14 are the same, and the dialing method is the same in the SAR ADC conversion, so that the mismatch of the capacitors does not affect the current result, and therefore, the capacitance weight of the capacitor is not changed. Capacitors C6, C9, C11, C15 and C16
Figure SMS_134
The iterative procedure reduces its weight because its weight is too large resulting in error > 0. Similarly, the capacitance weights corresponding to C2 and C3 are too small to cancel the effect of the excessive remaining bits, and thus the weights are increased. The signal generator generates a plurality of different voltages, so that the weight of each capacitor can be calibrated by the calibration program.
As shown in fig. 4 and 5, respectively, simulated in MATLABerrorSignals and methods
Figure SMS_136
In a SAR ADC with 14bit precision and two bit redundancy, setting non-ideal factor capacitance mismatch 5% and comparator noise200 μA, at which time the LMS algorithm calibration procedure iterates in 0.0005 steps, when +.>
Figure SMS_139
And->
Figure SMS_142
The difference of (2) is greater than +.>
Figure SMS_137
The weights of the capacitors with different quantization results are correspondingly adjusted and +.>
Figure SMS_138
The value of>
Figure SMS_141
And->
Figure SMS_143
The difference of (2) is less than +.>
Figure SMS_135
The reverse operation is performed, finally +>
Figure SMS_140
Convergence can be achieved within a few sampling points.
Fig. 6 to 21 are sequentially diagrams of calibration convergence of each capacitor. As can be seen from fig. 6 to 21, the present invention enables each bit capacitor to be calibrated and converged in the foreground. As shown in fig. 22 and 23, the fast fourier transform results of the output signals of the ADC before and after calibration respectively show that, by comparing, the mismatch of the high-order capacitor directly causes the low-order quantization result to lose meaning due to the ideal capacitor weight used for the comparison result of the SAR ADC comparator before calibration, so the effective number of bits (Effective Numbers of Bits, ENOB) of the ADC does not reach the design index at all, and because the quantization error is large, the generated harmonic wave related to the input signal greatly affects the spurious free dynamic range (Spurious Free Dynamic Range, SFDR) of the ADC, which determines the linearity of the ADC. When the calibration procedure is used, the ADC can quantize using the real capacitance weight, and the quantization error between the quantized output result and the input analog is reduced to the minimum, so that the ENOB performance and the SFDR performance are greatly improved.
According to the LMS foreground calibration method of the successive approximation type ADC, when foreground calibration is carried out, a pseudo-random signal is utilized to randomly stir or a sequence generator is utilized to sequentially stir CDAC to generate an input signal of the SAR ADC, an LMS algorithm is used, the capacitance weight is adjusted step by step through comparing the deviation between an actual value and an ideal value, iteration is carried out, an accurate capacitance weight value is finally calculated, and errors caused by capacitance mismatch are eliminated. According to the invention, the capacitance is calibrated only by utilizing the LMS algorithm in the foreground, twice quantization is not needed in the working process of the ADC, the problem that the conversion speed of the ADC needs to be reduced by the LMS algorithm in the background calibration is avoided, in addition, the weight of each capacitance can be calculated, the problem that the low-order capacitance cannot be calibrated in the traditional foreground calibration is solved, the error of the low-order capacitance cannot influence the calibration precision, and the calibration precision is improved.
Based on the same inventive concept, the embodiment of the invention also provides an LMS foreground calibration system of the successive approximation type ADC, and because the principle of solving the problem of the system is similar to that of the LMS foreground calibration method of the successive approximation type ADC, the implementation of the system can refer to the implementation of the LMS foreground calibration method of the successive approximation type ADC, and the repetition is omitted.
In another embodiment, an LMS foreground calibration system for a successive approximation ADC according to an embodiment of the invention, as shown in fig. 24, includes:
the signal generating module 10 is configured to generate any sequence of toggling CDAC using the pseudo-random signal or the sequential signal, so that the CDAC generates an analog signal covering the range of the ADC portion.
The offset generating module 20 is configured to dial "1" first and dial "0" later by using the target capacitors in the capacitor array, so that analog signals of all the upper plates of the capacitors in the capacitor array have two offsets with the same size and opposite polarities respectively; the offset exists in the analog signal in the form of an offset voltage.
The signal quantization module 30 is configured to quantize two analog signals with offset to obtain two quantized results.
The first calculation module 40 is configured to multiply the two quantized results with the target capacitance weights respectively, so as to obtain two digital results.
The second calculating module 50 is configured to calculate a deviation between a difference between the two digital results and a digital value corresponding to the preset offset.
The adjusting module 60 is configured to adjust the weight of the target capacitor and the digital quantity corresponding to the preset offset, so that the variation of the target capacitor is proportional to the deviation, and the deviation and the preset offset reach the convergence steady state.
Illustratively, the signal generation module includes:
a first calculation unit for calculating an analog signal according to the following formula:
Figure SMS_144
。
wherein ,
Figure SMS_146
is an analog signal;
Figure SMS_150
Is the first of the digital calibration signalsiThe value of the bit;
Figure SMS_151
Differential pair positive pole of CDAC array>
Figure SMS_147
A plurality of capacitors;
Figure SMS_149
Negative pole of CDAC array differential pair +.>
Figure SMS_152
A plurality of capacitors;
Figure SMS_153
For CDAC array differential pair positive total capacitance, < >>
Figure SMS_145
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure SMS_148
Is the total number of capacitors in the capacitor array.
Illustratively, the second computing module includes:
a second calculating unit for calculating the deviation of the difference between the two digital results and the digital quantity of the preset offset according to the following formula:
Figure SMS_154
。
wherein ,
Figure SMS_156
is->
Figure SMS_160
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure SMS_164
Is->
Figure SMS_158
During secondary calibration, the +.>
Figure SMS_162
The weight of the individual capacitances;
Figure SMS_165
Is->
Figure SMS_168
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_155
Quantization time of the firstiA bit result;
Figure SMS_159
Is the offset;
Figure SMS_163
Is->
Figure SMS_167
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure SMS_157
Quantization time of the firstiA bit result;
Figure SMS_161
Is an offset +.>
Figure SMS_166
Corresponding digital quantities.
Illustratively, the adjustment module includes:
a third calculation unit for calculating the weight of the adjusted target capacitance according to the following formula:
Figure SMS_169
。
wherein ,
Figure SMS_170
is->
Figure SMS_171
During secondary calibration, the +.>
Figure SMS_172
The weight of the individual capacitances;
Figure SMS_173
The step size is adjusted for the weight.
A fourth calculation unit, configured to calculate a digital quantity corresponding to the adjusted preset offset according to the following formula:
Figure SMS_174
。
wherein ,
Figure SMS_175
is->
Figure SMS_176
Offset +.>
Figure SMS_177
Corresponding digital quantity, < > for>
Figure SMS_178
Is->
Figure SMS_179
Offset in secondary calibrationaCorresponding digital quantities.
For more specific working procedures of the above modules, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In another embodiment, the present invention also provides a computer device, including a processor and a memory; the LMS foreground calibration method of the successive approximation ADC disclosed in the previous embodiment is realized when the processor executes the computer program stored in the memory.
For more specific procedures of the above method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In another embodiment, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program; the computer program, when executed by the processor, implements the LMS foreground calibration method of the successive approximation ADC disclosed previously.
For more specific procedures of the above method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the system, the device and the storage medium disclosed in the embodiments, the description is relatively simple, and the relevant places refer to the description of the method part because the system, the device and the storage medium correspond to the methods disclosed in the embodiments.
It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in essence or what contributes to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present invention.
The invention has been described in detail in connection with the specific embodiments and exemplary examples thereof, but such description is not to be construed as limiting the invention. It will be understood by those skilled in the art that various equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its embodiments without departing from the spirit and scope of the present invention, and these fall within the scope of the present invention. The scope of the invention is defined by the appended claims.

Claims (10)

1. An LMS foreground calibration method for a successive approximation ADC, comprising:
generating any sequence by using the pseudo-random signal or the sequence signal to stir the CDAC so that the CDAC generates an analog signal covering the range of the ADC part;
the method comprises the steps of firstly dialing 1 and then dialing 0 by utilizing a target capacitor in a capacitor array, so that analog signals of upper polar plates of all capacitors in the capacitor array are respectively provided with two offset quantities with the same size and opposite polarities; the offset exists in the analog signal in the form of offset voltage;
quantizing two analog signals with offset to obtain two quantized results;
multiplying the two quantized results with the target capacitance weight respectively to obtain two digital results;
calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset;
and adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset to make the change quantity of the target capacitor proportional to the deviation, wherein the deviation and the preset offset reach a convergence stable state.
2. The LMS front calibration method of a successive approximation ADC of claim 1, wherein generating either sequence of toggle CDAC using a pseudo random signal or a sequential signal such that the CDAC generates an analog signal covering a portion of the ADC range comprises:
the analog signal is calculated according to the following formula:
Figure QLYQS_1
；
wherein ,
Figure QLYQS_2
is an analog signal;
Figure QLYQS_3
Is the first of the digital calibration signalsiThe value of the bit;
Figure QLYQS_4
Differential pair positive pole of CDAC arrayiA plurality of capacitors;
Figure QLYQS_5
Negative pole of CDAC array differential pairiA plurality of capacitors;
Figure QLYQS_6
For CDAC array differential pair positive total capacitance, < >>
Figure QLYQS_7
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure QLYQS_8
Is the total number of capacitors in the capacitor array.
3. The LMS front calibration method of a successive approximation ADC of claim 2, wherein calculating a deviation of a difference between two digital results from a digital quantity corresponding to a preset offset comprises:
calculating the deviation of the difference value of the two digital results and the digital quantity of the preset offset according to the following formula:
Figure QLYQS_9
；
wherein ,
Figure QLYQS_18
is->
Figure QLYQS_12
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure QLYQS_22
Is->
Figure QLYQS_11
During secondary calibration, the +.>
Figure QLYQS_24
The weight of the individual capacitances;
Figure QLYQS_17
Is->
Figure QLYQS_25
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure QLYQS_15
Quantization is performed at->
Figure QLYQS_21
A bit result;
Figure QLYQS_10
Is the offset;
Figure QLYQS_19
Is->
Figure QLYQS_14
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure QLYQS_20
Quantization is performed at->
Figure QLYQS_16
A bit result;
Figure QLYQS_23
Is an offset +.>
Figure QLYQS_13
Corresponding digital quantities.
4. A LMS front calibration method for a successive approximation ADC according to claim 3, wherein the adjusting the weight of the target capacitance and the digital amount corresponding to the preset offset to make the change amount of the target capacitance proportional to the deviation, and the deviation and the preset offset reach the convergence steady state comprises:
the weight of the adjusted target capacitance is calculated according to the following formula:
Figure QLYQS_26
；/>
wherein ,
Figure QLYQS_27
is->
Figure QLYQS_28
During secondary calibration, the +.>
Figure QLYQS_29
The weight of the individual capacitances;
Figure QLYQS_30
Step length is adjusted for the weight;
calculating the number corresponding to the adjusted preset offset according to the following formula:
Figure QLYQS_31
；
wherein ,
Figure QLYQS_32
is->
Figure QLYQS_33
Offset +.>
Figure QLYQS_34
Corresponding digital quantity, < > for>
Figure QLYQS_35
Is->
Figure QLYQS_36
Offset +.>
Figure QLYQS_37
Corresponding digital quantities.
5. An LMS foreground calibration system for a successive approximation ADC comprising:
the signal generation module is used for generating any sequence by utilizing the pseudo-random signal or the sequence signal to stir the CDAC so as to enable the CDAC to generate an analog signal covering the range of the ADC part;
the offset generating module is used for firstly shifting 1 and then shifting 0 by utilizing a target capacitor in the capacitor array, so that analog signals of all upper electrode plates of the capacitors in the capacitor array are respectively provided with two offsets with the same size and opposite polarities; the offset exists in the analog signal in the form of offset voltage;
the signal quantization module is used for quantizing two analog signals with offset to obtain two quantized results;
the first calculation module is used for multiplying the two quantized results with the target capacitance weight respectively to obtain two digital results;
the second calculation module is used for calculating the deviation of the difference value of the two digital results and the digital quantity corresponding to the preset offset;
the adjusting module is used for adjusting the weight of the target capacitor and the digital quantity corresponding to the preset offset, so that the change quantity of the target capacitor is in direct proportion to the deviation, and the deviation and the preset offset reach a convergence stable state.
6. The LMS front calibration system of a successive approximation ADC of claim 5, wherein said signal generation module comprises:
a first calculation unit for calculating an analog signal according to the following formula:
Figure QLYQS_38
；
wherein ,
Figure QLYQS_41
is an analog signal;
Figure QLYQS_43
Is the +.>
Figure QLYQS_47
The value of the bit;
Figure QLYQS_40
Differential pair positive pole of CDAC array>
Figure QLYQS_44
A plurality of capacitors;
Figure QLYQS_46
Negative pole of CDAC array differential pair +.>
Figure QLYQS_48
A plurality of capacitors;
Figure QLYQS_39
For CDAC array differential pair positive total capacitance, < >>
Figure QLYQS_42
The total capacitance of the negative electrode of the CDAC array differential pair;
Figure QLYQS_45
Is the total number of capacitors in the capacitor array.
7. The LMS foreground calibration system of a successive approximation ADC of claim 6, wherein said second calculation module comprises:
a second calculating unit for calculating the deviation of the difference between the two digital results and the digital quantity of the preset offset according to the following formula:
Figure QLYQS_49
；
wherein ,
Figure QLYQS_53
is->
Figure QLYQS_51
In secondary calibration, the difference value of the two digital results is deviated from the digital quantity of the preset offset;
Figure QLYQS_61
is->
Figure QLYQS_54
During secondary calibration, the +.>
Figure QLYQS_62
The weight of the individual capacitances;
Figure QLYQS_55
Is->
Figure QLYQS_63
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure QLYQS_56
Quantization is performed at->
Figure QLYQS_64
A bit result;
Figure QLYQS_50
Is the offset;
Figure QLYQS_59
Is->
Figure QLYQS_57
In the secondary calibration, successive approximation type ADC is added to the analog signal>
Figure QLYQS_65
Quantization is performed at->
Figure QLYQS_52
A bit result;
Figure QLYQS_60
Is an offset +.>
Figure QLYQS_58
Corresponding digital quantities.
8. The LMS foreground calibration system of a successive approximation ADC of claim 7, wherein said adjustment module comprises:
a third calculation unit for calculating the weight of the adjusted target capacitance according to the following formula:
Figure QLYQS_66
；
wherein ,
Figure QLYQS_67
is->
Figure QLYQS_68
During secondary calibration, the +.>
Figure QLYQS_69
The weight of the individual capacitances;
Figure QLYQS_70
Step length is adjusted for the weight;
a fourth calculation unit, configured to calculate a digital quantity corresponding to the adjusted preset offset according to the following formula:
Figure QLYQS_71
；
wherein ,
Figure QLYQS_72
is->
Figure QLYQS_73
Offset +.>
Figure QLYQS_74
Corresponding digital quantity, < > for>
Figure QLYQS_75
Is->
Figure QLYQS_76
Offset +.>
Figure QLYQS_77
Corresponding digital quantities.
9. A computer device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the steps of the LMS foreground calibration method of the successive approximation ADC of any one of claims 1-4.
10. A computer-readable storage medium storing a computer program; the computer program, when executed by a processor, implements the steps of the LMS foreground calibration method of a successive approximation ADC of any one of claims 1-4.
CN202310206695.8A 2023-03-07 2023-03-07 LMS foreground calibration method and system of successive approximation type ADC Pending CN116073829A (en)

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