CN102075189B - Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration - Google Patents
Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration Download PDFInfo
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Abstract
The invention discloses a pipelined analog-digital converter (ADC) capable of carrying out background digital calibration. The pipelined (ADC) comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit modules and a back level analog-to-digital conversion module which are sequentially connected in series, wherein each calibrated level circuit module is connected with a corresponding digital calibrated level circuit; the quantized value output port of the level circuit module and the quantized value output port of a back level analog-to-digital conversion module are respectively connected with a time delay and dislocation summation module; and the output end of the time delay and dislocation summation module is sequentially and reversely connected in series in the digital calibrated level circuit. The pipelined analog-to-digital converter provided by the invention has the advantages that the thinking is inventive, the analog circuit has a simple structure, a pseudo random number generator and a multi-way selection switch are additionally arranged on the foundation of the existing technical structure, and the working of other analog circuits can not be unaffected in the working process; and simultaneously, the principle of the digital circuit segment is simple and is easy to realize, the error of the pipelined ADC can be reduced obviously, the linearity of the pipelined ADC can be improved, and the dynamic properties of the pipelined ADC can be improved.
Description
Technical field
The present invention relates to pipelined analog-digital converter, particularly relate to a kind of pipelined analog-digital converter utilizing single order and three rank errors to carry out backstage digital calibration.
Background technology
Pipelined analog-digital converter (pipelined analog-to-digital converter, hereinafter referred to as pipeline system ADC) is a kind of critical elements be often used in video image system, digital user loop, Ethernet transceiver or wireless telecommunication system; Pipeline system analog-to-digital conversion (A/D conversion, hereinafter referred to as A/D conversion) good balance point can be obtained on power, speed, integrated circuit chip area, therefore can be used for realizing sampling frequency among the high-precision adc computing of MHz grade.
Be conventional pipeline formula ADC structured flowchart as shown in Figure 1, analog signal after sampling hold circuit 100, then is quantized by N number of grade of circuit module 200 and rear class analog to digital conversion circuit module 300; Finally by the quantized value that circuit module 200 at different levels and rear class analog to digital conversion circuit module 300 obtain, by time delay and dislocation summation module 400, carry out dislocation according to time delays and weight and be added, export final digital signal Dout.
The single-ended structure block diagram of some level circuit modules 200 in conventional pipeline formula ADC as shown in Figure 2, it is by the clock control of two-phase non-overlapping: in phase place 1, sub sampling holding circuit 210 pairs of input signals are sampled, and sub-analog-to-digital conversion module 220 pairs of input signals carry out thick quantification and obtain quantized value D; In phase place 2, above-mentioned thick quantized value D is converted to corresponding analog signal by subnumber weighted-voltage D/A converter 230, then this analog signal enters in subtracter 240 to subtract each other with the input signal through sub sampling holding circuit 210 and obtains quantizing surplus, this quantification surplus, through the amplification of surplus amplifier 250, exports to next level circuit module 200.Each grade of circuit module 200 carries out the flow work like this: next level circuit module 200 is amplified → outputted to sampling → thick quantification → surplus; The output of last grade of circuit module 200 is delivered in rear class analog-to-digital conversion module 300, and the quantized value Db of the thick quantized value D of each grade of circuit module 200 and rear class analog-to-digital conversion module also will export to time delay and dislocation summation module 400.
Be the physical circuit realizing Fig. 2 function as shown in Figure 3, realize sampled input signal, the function that thick quantification and surplus are amplified.This circuit works under the clock control of two-phase non-overlapping, in phase place 1, the conducting of all switch S 1, all switch S 2 are closed, input signal is sampled on the first electric capacity 211 and the second electric capacity 212, comparator 221 and comparator 222 pairs of input signals slightly quantize simultaneously, and the threshold voltage of comparator 221 and comparator 222 is-Vref/4 and+Vref/4 respectively, and the thick quantized value D of the increase along with input signal is-1,0,1 successively; In phase place 2, all switch S 1 are closed, the conducting of all switch S 2, and the second electric capacity 212 lower shoe determines to link-Vref, 0 or+Vref according to quantized value D, and the first electric capacity 211 is connected to the output of operational amplifier 251 as feedback capacity.Like this after two phase places, this circuit just achieves the function of grade circuit module 200.
Suppose that the first electric capacity 211 and the second electric capacity 212 mate completely, switch S 1 and switch S 2 are desirable, and operational amplifier 251 is desirable (namely having infinitely-great open-loop gain and zero input imbalance), and so according to law of conservation of charge, can obtain output voltage is V
o=2*Vi-D*Vref, desirable surplus transmission curve is as shown in Fig. 4 (a) dotted line.Db is the quantized result that this grade of output signal Vo obtains through all level circuit modules 200 afterwards and rear class analog-to-digital conversion module 300, the complete transmission curve of grade circuit module 200 is obtained after this result and the corresponding levels thick quantized value D weighting summation, suppose that each grade of circuit module 200 and rear class analog-to-digital conversion module 300 are desirable, so this complete transmission curve (D+Db) should be the straight line that a slope is fixed, as shown in Fig. 4 (b) dotted line.
But in a practical situation, there is mismatch in the first electric capacity 211 and the second electric capacity 212, and switch S 1 and switch S 2 exist non-linear, and operational amplifier 251 neither be desirable (namely open-loop gain is limited and non-linear), these non-ideal factors can cause the deterioration of transmission curve, actual surplus transmission curve and complete transmission curve are as shown in the solid line in Fig. 4 (a) and Fig. 4 (b), and this situation will make performance of analog-to-digital convertor be deteriorated.
Now for the collimation technique of capacitance error, op-amp gain error and nonlinearity erron, general analog circuit more complicated, and digital algorithm also compares and is difficult to realize.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides the pipelined analog-digital converter that a kind of analog circuit is simple, digital algorithm is easy to the carried out backstage digital calibration realized.
Technical scheme: for achieving the above object, the technical solution used in the present invention is:
A kind of pipelined analog-digital converter carrying out backstage digital calibration, comprise connect successively sampling hold circuit, M adjustable level circuit module, N number of grade of circuit module and rear class analog-to-digital conversion module, wherein each adjustable level circuit module connects a digital calibration level circuit corresponded, level circuit module is connected with time delay and the summation module that misplaces with the quantized value output port of rear class analog-to-digital conversion module, the output of time delay and dislocation summation module is oppositely connected successively and is accessed digital calibration level circuit, and M, N are natural number.Can to the analog signal sampling of input by employing holding circuit; By M adjustable level circuit module, N number of grade of circuit module and the rear class analog-to-digital conversion module of connecting successively, analog-to-digital conversion can be carried out to obtain initial quantization value to analog signal, digital calibration circuit can detect the error in analog circuit, and error compensation is carried out to initial quantization value, finally can obtain quantized value accurately.
Described level circuit module is level circuit module of the prior art, the compare many pseudorandom number generators of grade circuit module and one of adjustable level circuit module is used for the multidiameter option switch of selection and comparison device threshold value, original fixing turnover level is made to become change at random, its structure is very simple and clear, and adjustable level circuit module mainly comprises specifically:
A sub-sampling hold circuit;
A pseudorandom number generator, is used for producing pseudo random number;
A multidiameter option switch, is used for selection one group turnover level as comparator threshold voltage;
A sub-adc converter, is made up of comparator and digital units, is used for realizing the analog-to-digital conversion of this adjustable level circuit module, and wherein comparator threshold controls multidiameter option switch by pseudo random number and comes to switch at random;
A sub-digital to analog converter, the quantized value being used for realizing this adjustable level circuit module is changed to analog domain;
A surplus amplifying circuit, is made up of subtracter and surplus amplifier, is used for realizing the input of this adjustable level circuit module and quantizing the subtraction of equivalent simulation and carry out multiple amplification.
In level circuit module, the connected mode of various piece is as follows: sub sampling holding circuit is in parallel with sub-adc converter to be accessed, the input of the output access subnumber weighted-voltage D/A converter of sub-adc converter, the positive pole of the output termination subtracter of sub sampling holding circuit, the negative pole of the output termination subtracter of subnumber weighted-voltage D/A converter, the input of the output termination surplus amplifier of subtracter.
Compare a grade circuit module, in adjustable level circuit module, pseudo-random generator is connected with the comparator of sub-adc converter by multidiameter option switch.
In addition, in order to reduce the scale of circuit, multiple adjustable level circuit module can share a pseudorandom number generator, and such as M adjustable level circuit module shares a pseudorandom number generator.
Described M digital calibration level circuit forms digital calibration circuit after differential concatenation successively, wherein each digital calibration level circuit comprises error sensing module and the module that calibrates for error, wherein error sensing module comprises self-adapting window, first-order error detection module and three rank error sensing module, and the module that calibrates for error comprises first-order error calibration module and three rank and to calibrate for error module.
Described self-adapting window can adjust in a calibration process automatically, to reduce the impact of input signal on the work of first-order error detection module, stablizes first-order error coefficient, reduces randomized jitter; Described first-order error detection module is by measuring the average difference update first-order error coefficient of different complete transmission curve; Described three rank error sensing module are by measuring the difference update three rank error coefficient of different surplus transmission curve in turnover level place hop value.
The physical circuit of described adjustable level circuit module comprises signal input part, operational amplifier, the first electric capacity and the second electric capacity, when adjustable level circuit module is positioned at phase place 1, first electric capacity and the second electric capacity are all connected between signal input part and amplifier in, when adjustable level circuit module is positioned at phase place 2, first electric capacity is connected between opamp input terminal and operational amplifier output terminal, and the second electric capacity is connected between subnumber weighted-voltage D/A converter output and opamp input terminal.Described first electric capacity can be identical with the second electric capacity.
Described workflow of carrying out the pipelined analog-digital converter of backstage digital calibration is as follows: input signal Vi is step by step by M adjustable level circuit module, N number of grade of circuit module and rear class analog-to-digital conversion module, and during this period, adjustable level circuit module exports thick quantized value and pseudo random number, level circuit module exports thick quantized value, rear class analog-to-digital conversion module output quantization value, by the thick quantized value of level circuit module and the quantized value of rear class analog-to-digital conversion module being added according to weight, obtain rear class quantized value Db (M); Rear class quantized value Db (M) inputs last (namely M) digital calibration level circuit, single order and three rank error coefficients are upgraded by error sensing module, the coefficient simultaneously utilizing error sensing module to obtain by the module that calibrates for error carries out single order and three rank calibrate for error, obtain new rear class quantized value Db (M-1), again this rear class quantized value Db (M-1) is exported to the digital calibration level circuit of previous stage, such the flow work, finally exports the quantized value Dout of input signal after calibration by the first order module that calibrates for error.
Beneficial effect: a kind of pipelined analog-digital converter carrying out backstage digital calibration provided by the invention, thinking is novel, and simulation circuit structure is simple, only on the basis of prior art structure, add pseudorandom number generator and multidiameter option switch, and can not affect the work of other analog circuits in the course of the work; Meanwhile, the principle of digital circuits section is simple, realization is easy, obviously can reduce the error of pipeline system ADC, improve its linearity, improve its dynamic property.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of pipeline system ADC of the prior art;
Fig. 2 is the level circuit modular structure block diagram of pipeline system ADC of the prior art;
Fig. 3 is the level circuit figure of pipeline system ADC of the prior art;
The level circuit module surplus transmission curve that Fig. 4 (a) is pipeline system ADC of the prior art;
The level circuit module complete transmission curve that Fig. 4 (b) is pipeline system ADC of the prior art;
Fig. 5 is the structured flowchart of the pipeline system ADC in the present invention;
Fig. 6 is the adjustable level circuit modular structure block diagram of the pipeline system ADC in the present invention;
Fig. 7 is the adjustable level circuit figure of the pipeline system ADC in the present invention;
The adjustable level circuit module surplus transmission curve that Fig. 8 (a) is the pipeline system ADC in the present invention;
The adjustable level circuit module complete transmission curve that Fig. 8 (b) is the pipeline system ADC in the present invention;
Fig. 9 is the digital calibration level circuit block diagram of the pipeline system ADC in the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Be illustrated in figure 5 a kind of structural representation carrying out the pipeline system ADC of backstage digital calibration, comprise the sampling hold circuit 100 of connecting successively, M adjustable level circuit module 500, N number of grade of circuit module 200 and rear class analog-to-digital conversion module 300, wherein each adjustable level circuit module 500 connects a digital calibration level circuit 600 corresponded, level circuit module 200 is connected with time delay and the summation module 400 that misplaces with the quantized value output port of rear class analog-to-digital conversion module 300, the output of time delay and dislocation summation module 400 is oppositely connected successively and is accessed digital calibration level circuit 600, M, N is natural number.
By the analog signal sampling of sampling hold circuit 100 to input, by M the adjustable level circuit module 500 of connecting successively, N number of grade of circuit module 200 and rear class analog-to-digital conversion module 300 carry out analog-to-digital conversion, the quantized value obtained by N number of grade of circuit module 200 and rear class analog-to-digital conversion module 300 is obtained rear class quantized value Db (M) by time delay and dislocation summation module 400, this rear class quantized value Db (M) is inputted M digital calibration level circuit module 600, carry out error-detecting and calibrate obtaining new rear class quantized value Db (M-1), then M-1 digital calibration level circuit module 600 is inputted, inverted order is carried out successively, the last quantized value Dout being exported whole ADC by the 1st digital calibration level circuit 600.
The structure of described level circuit module 200 as shown in Figure 2, sub sampling holding circuit 210 is in parallel with sub-adc converter 220 to be accessed, the input of the output access subnumber weighted-voltage D/A converter 230 of sub-adc converter 220, the positive pole of the output termination subtracter 240 of sub sampling holding circuit 210, the negative pole of the output termination subtracter 240 of subnumber weighted-voltage D/A converter 230, the input of the output termination surplus amplifier 250 of subtracter 240; Its circuit specifically adopted as shown in Figure 3.
The structure of adjustable level circuit module 500 as shown in Figure 6, its compare grade circuit module more than 200 pseudorandom number generator 560 and one are used for the multidiameter option switch of selection and comparison device threshold value, this makes original fixing turnover level become change at random, and adjustable level circuit module 500 mainly comprises specifically:
A sub-sampling hold circuit 510;
A pseudorandom number generator 560, is used for producing pseudo random number;
A multidiameter option switch, is used for selection one group turnover level as comparator threshold voltage;
A sub-adc converter 520, is made up of comparator and digital units, is used for realizing the analog-to-digital conversion of this adjustable level circuit module 500, and wherein comparator threshold controls multidiameter option switch by pseudo random number and comes to switch at random;
A sub-digital to analog converter 530, the quantized value being used for realizing this adjustable level circuit module 500 is changed to analog domain;
A surplus amplifying circuit, is made up of subtracter 540 and surplus amplifier 550, is used for realizing this adjustable level circuit module 500 and inputs and quantize the subtraction of equivalent simulation and carry out multiple amplification.
Pseudo-random generator 560 is connected by the comparator of multidiameter option switch with sub-adc converter 520.Adjustable level circuit module 500 works under the control of two-phase non-overlapping clock: in phase place 1, sub sampling holding circuit 510 is to the analog signal sampling of input, pseudorandom number generator 560 produces pseudo random number PN, one group of turnover level in PN chooser analog to digital converter 520, and sub-adc converter 520 carries out slightly quantizing to obtain quantized value D to input analog signal according to selected turnover level; In phase place 2, subnumber weighted-voltage D/A converter 530 converts quantized value D to analog voltage, and then by subtracter 540, the analog signal of input is deducted this analog voltage and obtain the thick surplus quantized, this surplus is amplified certain multiple and exported by surplus amplifier 550.
Figure 7 shows that the single-ended schematic diagram of the physical circuit realizing adjustable level circuit module 500 function, comprise turnover level generator 524, multidiameter option switch 523, pseudorandom number generator 561, comparator 521, comparator 522, encoder 525, first electric capacity 511, second electric capacity 512, operational amplifier 551 and switch S 1 and switch S 2 form.Turnover level generator 524 can produce some groups of comparator threshold, and the pseudo random number PN that multidiameter option switch 523 exported according to pseudorandom number generator 561 each cycle selects one group of comparator threshold to compare.For two groups of turnover level: set first group of level of transferring as-Vref/4 and+Vref/4, second group of turnover level is-Vref/4+ Δ V and+Vref/4+ Δ V (Δ V < Vref/4), select first group of level threshold voltage as two comparators of transferring as PN=0, select second group of level threshold voltage as two comparators of transferring as PN=1.
Circuit shown in Fig. 7 is based on the block diagram shown in Fig. 6, under it is also operated in two-phase non-overlapping clock: in phase place 1, switch S 1 conducting, switch S 2 disconnects, the analog signal of input is sampled on the first electric capacity 511 and the second electric capacity 512, pseudorandom number generator 561 produces a pseudo random number PN, PN selects one group of level of transferring as comparator threshold from turnover level generator 524, the comparative result of comparator 521 and comparator 522 obtains thick quantized value D by encoder 525, when the analog signal inputted is less than two turnover level, D=-1, when the analog signal inputted is between two turnover level, D=0, when the analog signal inputted is greater than two turnover level, D=1, in phase place 2, switch S 1 disconnects, switch S 2 conducting, and the first electric capacity 511 lower shoe is connected to the output of operational amplifier 551 as feedback capacity, second electric capacity 512 lower shoe is connected on reference level, as D=-1, reference level is-Vref, as D=0, reference level was 0 (namely), as D=1, reference level is+Vref, and the loop of such operational amplifier 551 and the first electric capacity 511, second electric capacity 512 composition just achieves the function of surplus amplification.
According to law of conservation of charge, circuit shown in Fig. 7 can obtain two surplus transmission curves of PN=0 and PN=1 as shown in Fig. 8 (a) dotted line, the quantized value Db of thick quantized value D and surplus is added according to weight, the complete transmission curve as shown in Fig. 8 (b) dotted line can be obtained.Consider the non-ideal factor in analog circuit, such as capacitance mismatch, switch non-linear, the finite gain and amplifier nonlinearity etc. of amplifier, the non-ideal of transmission curve can be caused, thus become single order and three rank errors (owing to adopting both-end differential configuration in side circuit this imperfect type equivalence, second order error is negligible), nonideal surplus transmission curve and complete transmission curve are as shown in solid line in Fig. 8 (a) and Fig. 8 (b), as can be seen from diagram, error causes the slope of transmission curve to diminish, there is " saltus step " and non-linear in turnover level place, digital calibration level circuit 600 is exactly to detect and calibrating above-mentioned single order and three rank errors.
As shown in Fig. 8 (a), first-order error causes the slope of the transmission curve of grade circuit module to be less than ideal value, rear class quantized value Db is the quantized value exporting analog voltage, therefore the slope of Db also diminishes, add thick quantized value D (value of 1.5bit level is-1,0,1) like this, complete transmission curve D+Db slope as shown in Fig. 8 (b) also diminishes, and there will be " saltus step " at breakover voltage place simultaneously.As shown in Fig. 8 (b), due to pseudo random number PN Stochastic choice two groups turnover level, " trip point " of these two complete transmission curves of PN=0 and PN=1 is different, if pseudo random number and signal have nothing to do, this feature can make the mean value of these two complete transmission curves variant, the mean value of the complete transmission curve of PN=0 (turnover level is-Vref/4 and+Vref/4) is greater than the mean value of PN=1 (turnover level is-Vref/4+ Δ V and+Vref/4+ Δ V) complete transmission curve, and this difference detects the foundation of first-order error after being exactly.
As shown in Fig. 8 (a), three rank errors cause the transmission curve of grade circuit module " to bend " to Vi axle, d0 and d1 is that PN=0 and PN=1 two surplus transmission curves (only consider RHP herein at turnover level place respectively, the mean value on both sides can be got in practical application) hop value, the surplus transmission curve of PN=0 is axisymmetric about Vi at the saltus step two ends at turnover level place, according to the fundamental property of function, therefore d0 is herein greater than d1, and this difference detects the foundation of three rank errors after being.
Described M digital calibration level circuit 600 forms digital calibration circuit after differential concatenation successively, as shown in Figure 9, each digital calibration level circuit 600 comprises error sensing module 610 and module 620 two parts that calibrate for error, wherein error sensing module 610 comprises self-adapting window 611, first-order error detection module 612 and three rank error sensing module 613, and the module that calibrates for error 620 comprises first-order error calibration module 622 and three rank and to calibrate for error module 621.
Described self-adapting window 611 can adjust in a calibration process automatically, to reduce the impact that input signal works on first-order error detection module 612, stablizes first-order error coefficient, reduces randomized jitter; Described first-order error detection module 612 is by measuring the average difference update first-order error coefficient of different complete transmission curve; Described three rank error sensing module 613 go out the difference update three rank error coefficient of hop value at turnover level by the different surplus transmission curve of measurement.
First-order error factor alpha represents, three rank error factor beta represent, calibration equation can be expressed as Db (i)=α * D+Db (i+1)+β * Db (i+1)
3, three rank calibrate for error module 621 (in order to reduce hardware size, cube computing in formula draws by look-up table) and first-order error calibration module 622 series connection realize this formula, realize calibration function, export calibration after Db (i).
Three rank error sensing module 613 are used for renewal three rank error coefficient β, and concrete mode is: rear class quantized value Db (i+1)+β * Db (i+1) after three rank calibrate for error utilizing some time cycles
3, the difference of two the hop value d0 and d1, d0 and d1 that calculate the above-mentioned surplus transmission curve mentioned just illustrates three rank extent by mistake, so can upgrade three rank error coefficient β according to this difference.
First-order error detection module 612 is used for upgrading first-order error factor alpha, concrete mode is: quantized value Db (i) calibrated through three rank errors and first-order error utilizing some time cycles, calculate the average difference of above-mentioned PN=0 and PN=1 two the complete transmission curves mentioned, this difference value represents the size of first-order error, so can upgrade first-order error factor alpha according to the difference of this average.In order to reduce the impact of input signal on first-order error detection module 612, self-adapting window 611 produces the Db (i) that two window W1 and W2 are used for selecting to enter first-order error detection module 612, as shown in Fig. 8 (b), the Db (i) only within window W1 and W2 scope just enters the foundation of first-order error detection module 612 as first-order error.Due to constantly carrying out along with digital calibration, the transmission curve of each calibration level circuit module 500 is changes, in order to adapt to this situation, window W1 and W2 is also along with the carrying out of calibration changes, reduce input signal as far as possible to the impact of first-order error detection module 612, stablize first-order error factor alpha, reduce its shake.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (3)
1. one kind can be carried out the pipelined analog-digital converter of backstage digital calibration, it is characterized in that: this pipelined analog-digital converter comprises the sampling hold circuit of connecting successively, M adjustable level circuit module, N number of grade of circuit module and rear class analog-to-digital conversion module, wherein each adjustable level circuit module connects a digital calibration level circuit corresponded, level circuit module is connected with time delay and the summation module that misplaces with the quantized value output port of rear class analog-to-digital conversion module, the output of time delay and dislocation summation module is oppositely connected successively and is accessed digital calibration level circuit, M, N is natural number,
By the analog signal sampling of sampling hold circuit to input, by M the adjustable level circuit module of connecting successively, N number of grade of circuit module and rear class analog-to-digital conversion module carry out analog-to-digital conversion, the quantized value obtained by N number of grade of circuit module and rear class analog-to-digital conversion module is obtained rear class quantized value Db (M) by time delay and dislocation summation module, this rear class quantized value Db (M) is inputted M digital calibration level circuit module, carry out error-detecting and calibrate obtaining new rear class quantized value Db (M-1), then M-1 digital calibration level circuit module is inputted, inverted order is carried out successively, the last quantized value Dout being exported whole ADC by the 1st digital calibration level circuit,
Described adjustable level circuit module comprises a sub-sampling hold circuit, the pseudorandom number generator of a generation pseudo random number, one is used for selection one group turnover level as the multidiameter option switch of comparator threshold voltage, realize the analog-to-digital sub-adc converter of this adjustable level circuit module, the subnumber weighted-voltage D/A converter that the quantized value realizing this adjustable level circuit module is changed to analog domain, realize the input of this adjustable level circuit module and quantize the subtraction of equivalent simulation and carry out the surplus amplifying circuit of multiple amplification, described surplus amplifying circuit is made up of subtracter and surplus amplifier, and described sub-adc converter is made up of comparator and digital units, described sub sampling holding circuit is in parallel with sub-adc converter to be accessed, pseudorandom number generator is connected with the comparator of sub-adc converter by multidiameter option switch, the input of the output access subnumber weighted-voltage D/A converter of sub-adc converter, the positive pole of the output termination subtracter of sub sampling holding circuit, the negative pole of the output termination subtracter of subnumber weighted-voltage D/A converter, the input of the output termination surplus amplifier of subtracter, described M adjustable level circuit module shares a pseudorandom number generator, in phase place 1, sub sampling holding circuit is to the analog signal sampling of input, pseudorandom number generator produces pseudo random number PN, one group of turnover level in PN chooser analog to digital converter, and sub-adc converter carries out slightly quantizing to obtain quantized value D to input analog signal according to selected turnover level,
Described digital calibration level circuit comprises error sensing module and the module that calibrates for error, wherein error sensing module comprises in a calibration process adjustment automatically with the self-adapting window of stable first-order error coefficient, first-order error detection module and three rank error sensing module, the module that calibrates for error comprises according to first-order error detection module by measuring the first-order error calibration module of the average difference update first-order error coefficient of different complete transmission curve, to calibrate for error on three rank of the difference update three rank error coefficient of turnover level place hop value module by measuring different surplus transmission curve with according to three rank error sensing module,
Described M digital calibration level circuit forms digital calibration circuit after differential concatenation successively;
Described self-adapting window can adjust in a calibration process automatically, to reduce the impact of input signal on the work of first-order error detection module, stablizes first-order error coefficient, reduces randomized jitter; Described first-order error detection module is by measuring the average difference update first-order error coefficient of different complete transmission curve; Described three rank error sensing module go out the difference update three rank error coefficient of hop value at turnover level by the different surplus transmission curve of measurement;
First-order error factor alpha represents, three rank error factor beta represent, calibration equation can be expressed as Db (i)=α * D+Db (i+1)+β * Db (i+1)
3, three rank calibrate for error module and first-order error calibration module series connection realize this formula, realize calibration function, export calibration after Db (i);
Three rank error sensing module are used for renewal three rank error coefficient β, and concrete mode is: rear class quantized value Db (i+1)+β * Db (i+1) after three rank calibrate for error utilizing some time cycles
3, the difference of two the hop value d0 and d1, d0 and d1 that calculate surplus transmission curve just illustrates three rank extent by mistake, so can upgrade three rank error coefficient β according to this difference;
First-order error detection module is used for upgrading first-order error factor alpha, concrete mode is: quantized value Db (i) calibrated through three rank errors and first-order error utilizing some time cycles, calculate the average difference of PN=0 and PN=1 two complete transmission curves, this difference value represents the size of first-order error, so can upgrade first-order error factor alpha according to the difference of this average; In order to reduce the impact of input signal on first-order error detection module, self-adapting window produces the Db (i) that two window W1 and W2 are used for selecting to enter first-order error detection module, and the Db (i) only within window W1 and W2 scope just enters the foundation of first-order error detection module as first-order error; Due to constantly carrying out along with digital calibration, the transmission curve of each calibration level circuit module is change, in order to adapt to this situation, window W1 and W2 is also along with the carrying out of calibration changes, reduce input signal as far as possible to the impact of first-order error detection module, stablize first-order error factor alpha, reduce its shake.
2. the pipelined analog-digital converter carrying out backstage digital calibration according to claim 1, it is characterized in that: described adjustable level circuit module comprises signal input part, operational amplifier, first electric capacity and the second electric capacity, when adjustable level circuit module is positioned at phase place 1, first electric capacity and the second electric capacity are all connected between signal input part and opamp input terminal, when adjustable level circuit module is positioned at phase place 2, first electric capacity is connected between opamp input terminal and operational amplifier output terminal, second electric capacity is connected between subnumber weighted-voltage D/A converter output and opamp input terminal.
3. the pipelined analog-digital converter carrying out backstage digital calibration according to claim 2, is characterized in that: described first electric capacity is identical with the second electric capacity.
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