CN101888246B - Charge coupling pipelined analogue-to-digital converter with error correction function - Google Patents

Abstract

The invention provides a charge coupling pipelined analogue-to-digital converter with error correction function. The analogue-to-digital converter comprises a charge coupling pipelined analogue-to-digital converter core, a common-mode error correction module, a differential mode error correction module, an input common-mode voltage offset compensation module and an error correction controller module. The charge coupling pipelined analogue-to-digital converter with error correction function can automatically detect differential mode error, common-mode error and input common-mode voltage offset error which are caused by non-ideal characteristics in full-difference structure charge coupling pipelined analogue-to-digital converter and can correct the errors, the influence of the errors is controlled to be within the minimum resolution, so as to overcome the problem that restricts the accuracy of the existing charge coupling pipelined analogue-to-digital converter is restricted by errors caused by various non-ideal characteristics, and further the conversion accuracy of the existing charge coupling pipelined analogue-to-digital converter is improved.

Description

Charge coupling assembly line analog to digital converter with error correction function

Technical field

The present invention relates to a kind of production line analog-digital converter, relate in particular to a kind of charge coupling assembly line analog to digital converter with all kinds of error correction functions.

Background technology

Along with the continuous development of Digital Signal Processing, the digitlization of electronic system and integrated be inexorable trend.Yet the signal in the reality mostly is the continually varying analog quantity, need to become digital signal through analog-to-digital conversion and can be input to and handle in the digital system and control, thereby analog to digital converter is indispensable part in the Design of Digital System in future.In applications such as broadband connections, digital high-definition television and radars, the system requirements analog to digital converter has very high sampling rate and resolution simultaneously.The portable terminal product of these applications is not only wanted high sampling rate and high-resolution for the requirement of analog to digital converter, and its power consumption also should minimize.

At present, can realize simultaneously that high sampling rate and high-resolution analog-digital converter structure are the pipeline organization analog to digital converter.Pipeline organization is a kind of multistage transformational structure, and each grade uses the analog to digital converter of the basic structure of low precision, and input signal is through step by step processing, generates high-precision output by every grade result combinations at last.Its basic thought is exactly to arrive each level to the conversion accuracy mean allocation that requires generally, and the transformation result of each grade combines and can obtain final transformation result.Because the pipeline organization analog to digital converter can be realized best compromise on speed, power consumption and chip area, therefore when realizing the analog-to-digital conversion of degree of precision, still can keep higher speed and lower power consumption.

The mode of the realization pipeline organization analog to digital converter of existing comparative maturity is based on the pipeline organization of switched capacitor technique.Also all must use the operational amplifier of high-gain and wide bandwidth based on the work of sampling hold circuit in this technological production line analog-digital converter and each sub level circuit.The speed of analog to digital converter and processing accuracy depend on the degenerative speed and the precision set up of operational amplifier of the high-gain of using and ultra wide bandwidth.Therefore the core of such pipeline organization analog to digital converter design be the design of operational amplifier of the high-gain of using and ultra wide bandwidth.The use of these high-gains and wide bandwidth operational amplifier has limited the speed and the precision of switching capacity production line analog-digital converter; Become the major limitation bottleneck that such performance of analog-to-digital convertor improves, and under the constant situation of precision the analog to digital converter power consumption levels with the raising of speed ascendant trend linearly.Reduce the power consumption levels based on the production line analog-digital converter of switched-capacitor circuit, the most directly method is exactly the use of the operational amplifier of minimizing or cancellation high-gain and ultra wide bandwidth.

Charge coupling assembly line analog to digital converter is exactly a kind of analog to digital converter that does not use the operational amplifier of high-gain and ultra wide bandwidth, and this structural module transducer has the low-power consumption characteristic can realize high-speed and high accuracy simultaneously again.Charge coupling assembly line analog to digital converter adopts electric charge coupled signal treatment technology.In the circuit, signal representes with the form of charge packet, and the size of charge packet is represented the semaphores of different sizes, the storage of the charge packet of different sizes between different memory nodes, transmits, adds/subtract, relatively waits to handle and realize signal processing function.Through adopting periodic clock to come the signal processing of charge packet between different memory nodes of the different sizes of drive controlling just can realize analog-digital conversion function.

In charge coupling assembly line analog to digital converter, the charge packet that the charge coupled sampling-holding circuit sampling obtains will be delivered in the subsequent stages electric charge coupling sub level flow line circuit and carry out step by step relatively quantification treatment.For the charge coupling assembly line analog to digital converter that adopts the fully differential structure to realize; Signal processing is to carry out synchronously on the positive and negative signal processing path of the complementary symmetry in center with the common-mode signal two signal conditions, at last with the difference of two signalling channel results as final process result.Input voltage signal at first converts two charge packets of fully differential form into, supplies subsequent stages fully differential electric charge coupling sub level flow line circuit quantification treatment respectively, obtains quantizing the output result at last.

Shown in Figure 1 being has the most basic charge coupling assembly line analog to digital converter circuit structure block diagram now.A charge coupling assembly line analog to digital converter generally includes: charge coupled sampling-holding circuit 0, a n level produce circuit 7 and clock signal generating circuit 8 based on streamline sub level circuit 1～3, afterbody (n+1 level) N-bit Flash analog-digital converter circuit 4, time-delay SYN register 5, digital correction circuit module 6, the reference signal of electric charge coupled signal treatment technology.The mode of operation control module also is the necessary back work module of analog to digital converter work in addition, and this module does not identify in the drawings.

The basic functional principle of circuit shown in Fig. 1 is following: input analog voltage signal Vin is at first through charge coupled sampling-holding circuit 0 charge packet that to convert a size to be Qp0-Qn0; When the charge transfer control switch of first order streamline sub level circuit 1 was opened, this charge packet was transferred to first order streamline sub level circuit 1; Streamline sub level circuit 1 compares quantification with this charge packet with reference signal after receiving the charge packet completion immediately; Obtain k1 position at the corresponding levels and quantize the output digital code; The k1 position of comparator at the corresponding levels quantizes the output digital code will output to time-delay SYN register 5; Quantize the output digital code and also will control reference signal at the corresponding levels is carried out corresponding size to charge packet plus-minus processing; Obtaining size at the corresponding levels is Qp1-Qn1 surplus charge packet; After clock phase switched, the surplus charge packet of circuit at the corresponding levels got into second level sub level circuit 2 and repeats said process through the charge transfer control switch of next stage, and generation k2 position quantizes the output digital code and outputs to time-delay SYN register 5; Analogize in proper order, when n level sub level flow line circuit 3 is accomplished conversion work at the corresponding levels, will obtain size and be the surplus charge packet of Qpn-Qnn, and quantification output digital code in generation kn position outputs to time-delay SYN register 5; When the size of n level sub level circuit is that the surplus charge packet of Qpn-Qnn is when being transferred to afterbody (n+1 level) N-bit Flash analog-digital converter circuit 4 through charge transfer control switch amount; This grade circuit will carry out the analog-to-digital conversion work of afterbody to the charge packet that receives; And the kn+1 position of circuit at the corresponding levels output digital code is input to time-delay SYN register 5; But this grade circuit is only accomplished analog-to-digital conversion, does not carry out surplus and handles; Time-delay SYN register 5; To the digital code of each sub-pipelining-stage output alignings of delaying time, and the digital code of alignment is input to figure adjustment module 6, wherein the k1 position of first order output quantizes to export digital code and will delay time n clock cycle; The k2 position of second level output quantizes the output digital code and will delay time n-1 clock cycle; By that analogy, the k1 position of n level output quantizes the output digital code will delay time 1 clock cycle, and afterbody output is not delayed time; Digital correction circuit module 6 will receive the output digital code of SYN register, and the digital code that receives is carried out shifter-adder, to obtain the R bit digital output code of analog to digital converter.The clock signal of aforementioned all circuit module needs of work is provided by clock signal generating circuit 8, and the reference signal of all circuit module needs of work and offset signal reference signal produce circuit 7 and provide.

The 1.5bit/ level electric charge coupling sub level flow line circuit schematic diagram that is typical fully differential structure realization shown in Figure 2.Circuit is made up of the signal processing channel 20p and the 20n of fully differential among Fig. 2; Entire circuit comprises that 2 charge transfer control switchs at the corresponding levels (21p and 21n), 2 charge-storage node (24p and 24n), 6 are connected to the charge storage capacitance of charge-storage node, 2 comparators; 2 receive the reference charge of comparator output result control to select circuit (23p and 23n), 2 charge transfer control switchs (22p and 22n) that are connected to the next stage sub level circuit of charge-storage node at the corresponding levels.During the circuit operate as normal; Prime differential electrical pocket is at first through 21p and 21n transmission and be stored in charge-storage node 24p at the corresponding levels and 24n; Voltage difference variable quantity and reference signal Vrp and Vrn that comparator is imported between caused node 24p and the 24n the differential electrical pocket compare, and obtain 2 at the corresponding levels and quantize output digital code D1D0; Digital output code D1D0 will output to the time-delay SYN register; D1D0 also will control reference signal at the corresponding levels and select circuit 23p and 23n simultaneously; The reference signal that makes them produce a pair of complementation is respectively controlled positive and negative terminal electric charge plus-minus capacitor bottom plate at the corresponding levels respectively; To be transferred to the plus-minus processing that differential electrical pocket at the corresponding levels carries out corresponding size by prime, obtain difference surplus charge packet at the corresponding levels; At last; Circuit is accomplished difference surplus charge packet at the corresponding levels and is transmitted to next stage by the corresponding levels; Reset signal Vset resets to differential charge memory node 24p at the corresponding levels and 24n, accomplishes the work in a 1.5bit/ level charge coupling assembly line sub level complete clock cycle of circuit.

Adopt the fully differential structure to carry out signal processing and have extraordinary anti-common mode disturbances characteristic, and can make input reference signal expand as the twice of single-ended format.Yet realize the high-performance of fully differential architecture signals treatment circuit, its positive and negative signal processing path that carries out signal processing must be strict symmetrical; Simultaneously, in the above-mentioned charge coupling assembly line analog to digital converter, its common mode charge packet size was general when subsequent stages electric charge coupling sub level flow line circuit was handled the input charge packet keeps equating constant.Yet; Under existing C MOS process conditions; Because the existence of technological fluctuation randomness and other kinds irrational factors; The positive and negative signal processing path of being realized can not be strict symmetrical, and the common mode electric charge size of electric charges coupling sub level flow line circuits at different levels can not strictly equate, but has certain differential mode and common-mode error.At the charge coupling assembly line analog to digital converter below 10, the error that the technological fluctuation of existing CMOS technology brings can be ignored for precision.Reach the charge coupling assembly line analog to digital converter more than 10 for precision, components and parts mismatch differential mode error and common-mode error that existing process conditions are brought can not be ignored.And in the side circuit, the fully differential input signal generally is to handle the differential complement signals that obtains 180 ° of phase differences through single-ended signal input sample coupling circuit outside sheet.Because there are all kinds of non-ideal characteristics in this input sample coupling circuit; The fluctuation of certain amplitude can appear in the common mode electrical level of the differential complement signals of its output; The phase difference of its output differential signal also certain error can occur simultaneously, and just may there be certain common mode offset error in ADC input fully differential signal like this.

Therefore to realize the fully differential structure high accuracy charge coupling assembly line analog to digital converter of precision more than 10; Must calibrate differential mode error and all kinds of common-mode error that components and parts mismatch in its positive and negative signal processing path is brought, to overcome the restriction of differential mode that various non-ideal characteristic brought and common-mode error the charge coupling assembly line analog to digital converter performance.

Summary of the invention

The objective of the invention is to overcome the deficiency that exists in the prior art, a kind of fully differential structure is provided, has the charge coupling assembly line analog to digital converter circuit of differential mode and common-mode error calibration function, to realize higher precision.

According to technical scheme provided by the invention, said charge coupling assembly line analog to digital converter with error correction function comprises:

A charge coupling assembly line analog to digital converter nuclear is used for converting analog input signal into digital output code; A common-mode error calibration module is used for said charge coupling assembly line analog to digital converter nuclear is carried out the common-mode error calibration; A differential mode error calibration module is used for said charge coupling assembly line analog to digital converter nuclear is carried out the differential mode error calibration; An input common mode voltage offset compensating module, the input differential signal common mode voltage offset error that is used for the charge coupling assembly line analog to digital converter chip exterior is input to said charge coupling assembly line analog to digital converter nuclear compensates; The controller module that calibrates for error is used to control the mode of operation of charge coupling assembly line analog to digital converter, also controls the operating state of common-mode error calibration module, differential mode error calibration module and input common mode voltage offset compensating module simultaneously.

The operating state of whole charge coupling assembly line analog to digital converter has two kinds of calibration mode and normal data translative mode; During electrification reset, charge coupling assembly line analog to digital converter at first gets into calibration mode, after the work of accomplishing calibration mode, gets into the normal data translative mode;

In said calibration mode, charge coupling assembly line analog to digital converter carries out the calibration of common mode and differential mode error by common-mode error calibration module and differential mode error calibration module respectively to said charge coupling assembly line analog to digital converter nuclear under the control of the said controller module that calibrates for error; The input common mode voltage offset compensating module will can not be activated in calibration mode; In whole calibration mode, the quantification output code of whole charge coupling assembly line analog to digital converter is a disarmed state;

In said normal data translative mode, charge coupling assembly line analog to digital converter carries out the input common mode voltage offset compensation by the input common mode voltage offset compensating module to said charge coupling assembly line analog to digital converter nuclear under the control of the said controller module that calibrates for error; Said common-mode error calibration module and differential mode error calibration module can not be activated in whole normal data translative mode and only keep its calibration result constant; In whole normal data translative mode, the quantification output code of whole charge coupling assembly line analog to digital converter is an effective status.

In the said calibration mode: at first, the controller module that calibrates for error sends control code Ctrl0 and controls said charge coupling assembly line analog to digital converter nuclear entering calibration mode; Then; The controller module that calibrates for error output control code Ctrl1 starts the common-mode error calibration module; The common-mode error calibration module produces error correction signal Cal1 said charge coupling assembly line analog to digital converter nuclear is carried out the common-mode error calibration under the control of control code Ctrl1; When accomplishing the common-mode error calibration operation, control code Ctrl1 is with no longer valid, but error correction signal Cal1 will remain unchanged; Subsequently; The controller module that calibrates for error output control code Ctrl2 starts the differential mode error calibration module; The differential mode error calibration module produces error correction signal Cal2 charge coupling assembly line analog to digital converter nuclear is carried out the differential mode error calibration under the control of control code Ctrl2; When accomplishing the differential mode error calibration operation, control code Ctrl2 is with no longer valid, but error correction signal Cal2 will remain unchanged; At last, the said controller module change control code Ctrl0 that calibrates for error controls said charge coupling assembly line analog to digital converter nuclear and withdraws from calibration mode, gets into the normal data translative mode.

Said controller calibration module comprises: MCU module, ROM module, SRAM module, common mode calibration control logic, differential mode calibration control logic and input common mode voltage offset compensation control logic;

Said MCU module plays overall control action, and the control command of all calibration operations is sent by the MCU module;

The ROM module is used for storage calibration control program, and after the charge coupling assembly line analog to digital converter chip manufacture was come out, the calibration control program that is stored on the ROM immobilized;

The SRAM module is used for storing the data that calibration process produces, and plays the effect of metadata cache;

Common mode calibration control logic, differential mode calibration control logic and input common mode voltage offset compensation control logic are worked when the job step that calibrates for error proceeds to common mode calibration, differential mode calibration and input common mode voltage offset compensation process respectively, are respectively the control logic of corresponding calibration steps.

Advantage of the present invention is: can detect common-mode error in the fully differential structure charge coupling production line analog-digital converter automatically; And this common-mode error calibrated; The influence of this common-mode error is controlled in the lowest resolution requirement of analog to digital converter; To overcome common-mode error that technological fluctuation brings problem, further improve the conversion accuracy of existing charge coupling assembly line analog to digital converter to the accuracy limitations of existing charge coupling assembly line analog to digital converter.

Description of drawings

Fig. 1 is existing typical charge coupling production line analog-digital converter structured flowchart;

Fig. 2 is typical 1.5bit/ level electric charge coupling sub level flow line circuit schematic diagram;

Fig. 3 has the charge coupling assembly line analog to digital converter structured flowchart of error correction function for the present invention;

Fig. 4 is the present invention's flow chart that calibrates for error;

Fig. 5 is a controller calibration modular structure block diagram of the present invention;

Fig. 6 is common-mode error calibration module structured flowchart among the present invention;

Fig. 7 for refinement the present invention in common-mode error calibration module structured flowchart;

Fig. 8 selects the array module schematic block circuit diagram for switch of the present invention;

Fig. 9 detects selector switch element circuit figure for common-mode signal among the present invention;

Figure 10 is with reference to common-mode signal selector switch element circuit figure among the present invention;

Figure 11 is register and controller module structured flowchart in the common-mode error calibration module of the present invention;

Figure 12 is error correction modular circuit structure in the common-mode error calibration module of the present invention;

Figure 13 corrects the element circuit structure principle chart for common-mode error in the common-mode error calibration module of the present invention;

Figure 14 is differential mode error calibration module structured flowchart among the present invention;

Figure 15 for refinement the present invention in differential mode error calibration module structured flowchart;

Figure 16 is reference signal selecting circuit structure and different working modes schematic diagram;

Figure 16 (a) is a reference signal selecting circuit structure block diagram; Figure 16 (b) selects the schematic diagram of circuit working when the normal mode for reference signal; Figure 16 (c) selects the schematic diagram of circuit working when the calibration mode for reference signal;

Figure 17 is for carrying out the schematic diagram of differential mode error calibration to typical 1.5bit/ level sub level flow line circuit;

Figure 18 realizes circuit theory diagrams for differential mode error quantization modules of the present invention;

Figure 19 is a differential mode error calibration module middle controller modular structure schematic diagram of the present invention;

Figure 20 is a kind of circuit theory diagrams of charge coupled sampling-holding circuit;

Figure 21 is to input common mode voltage offset error compensation circuit structure chart among the present invention;

Figure 22 is the application block diagram of input common mode voltage offset error compensation circuit of the present invention;

Figure 23 is input common mode voltage offset error-detector circuit among the present invention;

The circuit that Figure 24 quantizes for the input common mode voltage offset error that among the present invention detection is obtained;

Figure 25 is the circuit structure block diagram of displacement and controller module among the present invention;

Figure 26 is input common mode offset error compensation modular circuit structured flowchart among the present invention.

Embodiment

As shown in Figure 3, charge coupling assembly line analog to digital converter 300 its inside that the present invention has error correction function comprise: 30, common-mode error calibration modules of charge coupling assembly line analog to digital converter nuclear 31, differential mode error calibration module 32, an input common mode voltage offset compensating module 33 and the controller module 34 that calibrates for error.Charge coupling assembly line analog to digital converter nuclear 30 is the nucleus module of whole analog to digital converter, and it is used for converting analog input signal into digital output code, and all the other 4 modules are used for charge coupling assembly line analog to digital converter nuclear 30 is calibrated for error; Common-mode error calibration module 31 is used for charge coupling assembly line analog to digital converter nuclear 30 is carried out the common-mode error calibration; Differential mode error calibration module 32 is used for charge coupling assembly line analog to digital converter nuclear 30 is carried out the differential mode calibration, and the input differential signal common mode voltage offset error that input common mode voltage offset compensating module 33 is used for chip exterior is input to charge coupling assembly line analog to digital converter nuclear 30 compensates; The controller module 34 that calibrates for error is used to control the mode of operation of whole analog to digital converter 300, also controls the operating state of common-mode error calibration module 31, differential mode error calibration module 32 and input common mode voltage offset compensating module 33 simultaneously.Wherein charge coupling assembly line analog to digital converter nuclear 30 is elementary charge coupling production line analog-digital converter shown in Figure 1.

The operating state of the charge coupling assembly line analog to digital converter circuit with error correction function shown in Figure 3 has calibration mode and two kinds of mode of operations of normal data translative mode.In the calibration mode; Analog to digital converter 300 portion within it calibrates for error and carries out common mode and differential mode error respectively by 32 pairs of charge coupling assembly line analog to digital converter nuclears 30 of common-mode error calibration module 31 and differential mode error calibration module under the control of controller module 34 and calibrate; Input common mode voltage offset compensating module 33 will can not be activated in calibration mode; And in whole calibration mode, the quantification output code of analog to digital converter 300 is a disarmed state; In the normal data translative mode; Analog to digital converter 300 portion within it calibrates for error and carries out the input common mode voltage offset compensation by 33 pairs of charge coupling assembly line analog to digital converter nuclears 30 of input common mode voltage offset compensating module under the control of controller module 34; Common-mode error calibration module 31 will can not be activated in whole normal data translative mode with differential mode error calibration module 32 and only keep its calibration result constant; In whole normal data translative mode, the quantification output code of analog to digital converter 300 is an effective status.

Operation principle when the charge coupling assembly line analog to digital converter 300 with error correction function is in calibration mode is: circuit sends the calibration mode commencing signal by the controller module 34 that calibrates for error; Whole error calibration circuit is started working, and charge coupling assembly line analog to digital converter 300 gets into calibration mode; The controller module 34 that calibrates for error at first sends control code Ctrl0 control charge coupling assembly line analog to digital converter nuclear 30 and gets into calibration mode, and 300 outer input analog signals to be quantified of analog to digital converter will no longer be input to charge coupling assembly line analog to digital converter nuclear 30; The controller module 34 that calibrates for error is at first exported control code Ctrl1 and is started common-mode error calibration module 31; Common-mode error calibration module 31 produces error correction signal Cal1 charge coupling assembly line analog to digital converter nuclear 30 is carried out the common-mode error calibration under the control of control code Ctrl1; When accomplishing the common-mode error calibration operation; Control code Ctrl1 is with no longer valid, but error correction signal Cal1 will remain unchanged, i.e. common mode error correction will be the result will remain unchanged; After accomplishing the common-mode error calibration operation; The controller module 34 that calibrates for error will be exported control code Ctrl2 and start differential mode error calibration module 32; Differential mode error calibration module 32 produces error correction signal Cal2 charge coupling assembly line analog to digital converter nuclear 30 is carried out the differential mode error calibration under the control of control code Ctrl2, when accomplishing the differential mode error calibration operation, control code Ctrl2 is with no longer valid; But error correction signal Cal2 will remain unchanged, i.e. differential mode error correction will be the result will remain unchanged; Input common mode voltage offset compensating module 33 will can not be activated in calibration mode, and in whole calibration mode, the quantification output code of analog to digital converter 300 is a disarmed state; After accomplishing the differential mode error calibration operation, analog to digital converter 300 withdraws from calibration mode, beginning normal data translative mode.

Operation principle when analog to digital converter 300 is in the normal data translative mode is: the controller module 34 output control code Ctrl3 that calibrate for error start common-mode error calibration module 31; Input common mode voltage offset compensating module 33 produces error correction signal Cal3 charge coupling assembly line analog to digital converter nuclear 30 is carried out the input common mode voltage offset compensation under the control of control code Ctrl3; Common-mode error calibration module 31 will can not be activated in whole normal data translative mode with differential mode error calibration module 32 and only keep its calibration result constant; In whole normal data translative mode, the quantification output code of analog to digital converter 300 is an effective status.

In two kinds of mode of operations of above-mentioned charge coupling assembly line analog to digital converter 300 with error correction function; When analog to digital converter 300 electrification resets begin to start; What at first get into is calibration mode of operation; After accomplishing common mode and differential mode calibration operation, analog to digital converter 300 finishes calibration mode of operation, and analog to digital converter 300 is accomplished the electrification reset step simultaneously.After withdrawing from calibration mode of operation, analog to digital converter 300 gets into the normal data translative mode, beginning normal data conversion work.The workflow diagram that calibrates for error of whole charge coupling assembly line analog to digital converter 300 is as shown in Figure 4.

The structured flowchart of controller calibration module 34 in the charge coupling assembly line analog to digital converter 300 that has error correction function for the present invention shown in Figure 5.Controller calibration module 500 its inner functions comprise MCU module 50, ROM module 51, SRAM module 52, common mode calibration control logic 53, differential mode calibration control logic 54 and input common mode voltage offset compensation control logic 55.Wherein, the effect of MCU module is to play overall control action, and the control of all calibration operations is sent by MCU module 50; ROM module 51 is used for storage calibration control program, and after chip manufacture is come out, the calibration control program that is stored on the ROM will immobilize; The SRAM module is used for storing the data that calibration process produces, and plays the effect of metadata cache; Common mode calibration control logic 53, differential mode calibration control logic 54 and input common mode voltage offset compensation control logic 55 work when the calibration flow process proceeds to common mode calibration, common mode calibration and input common mode voltage offset compensation process respectively, are used for the Control work of corresponding calibration steps.

The circuit working process is following among Fig. 5: behind the analog to digital converter electrification reset, the MCU module reads calibration procedure from the ROM module; According to calibration procedure; The MCU module will at first make analog to digital converter 300 get into calibration mode; And generation control code Ctrl0 is used to make charge coupling assembly line analog to digital converter nuclear 30 to get into calibration modes; Make common mode calibration control logic 53 effective then; 31 pairs of charge coupling assembly line analog to digital converter nuclears 30 of common-mode error calibration module that common mode calibration control logic 53 will produce control code Ctrl1 control analog to digital converter 300 carry out the common-mode error calibration, and whether MCU accomplishes the common mode calibration operation through common mode calibration control logic 53 feedback signals; After the MCU decision circuitry is accomplished the common-mode error calibration operation; The MCU module will make differential mode calibration control logic 54 effective; 31 pairs of charge coupling assembly line analog to digital converter nuclears 30 of common-mode error calibration module that differential mode calibration control logic 54 will produce control code Ctrl2 control analog to digital converter 300 carry out the differential mode error calibration, and whether MCU accomplishes the common mode calibration operation through differential mode calibration control logic 54 feedback signals; After the MCU decision circuitry is accomplished the common-mode error calibration operation; The MCU module will make analog to digital converter 300 withdraw from calibration mode and get into the normal data translative mode, and change control code Ctrl0 is used to make charge coupling assembly line analog to digital converter nuclear 30 to get into the normal data translative mode; Analog to digital converter 300 gets into after the normal data translative mode; The MCU module will make input common mode voltage offset compensation control logic 55 effective, and input common mode voltage offset compensation control logic 55 will produce 33 pairs of charge coupling assembly line analog to digital converter nuclears 30 of control code Ctrl3 control input common mode voltage offset compensating module and carry out the input common mode voltage offset compensation.

Two calibration steps when introducing the charge coupling assembly line analog to digital converter 300 with error correction function below and being in calibration mode are at first introduced the common mode calibration circuit.

As shown in Figure 6, the circuit structure that the present invention calibrates common-mode error in the fully differential structure charge coupling production line analog-digital converter comprises: switch is selected array module 61, error quantization module 62, error correction module 63 and register and controller module 64.Wherein, switch selects array module 61 to be used for selecting common-mode signal that output needs to detect and with reference to common-mode signal according to control code; Error quantization module 62 is used for selecting the common-mode signal to be detected and the benchmark common-mode signal of array module 61 outputs to compare quantification on switch; Controller module 64 effects are to control the work of whole calibration circuit; Provide switch to select the needed control code of array module 61 work, and the quantization code of error quantization module 62 outputs is handled the needed error correcting code of generation error correction module 63 work; Error correction module 63 effect is that the error correcting code that provides according to controller module carries out common mode to charge coupled sampling-holding circuit in the fully differential structure charge coupling production line analog-digital converter with each electric charge coupling sub level flow line circuit and correct.

The operation principle of circuit shown in Figure 6 is: circuit at first sends the calibration mode commencing signal by register and controller module, and whole common-mode error calibration circuit is started working; Calibration reference signal of charge coupling assembly line analog to digital converter input, and this calibration reference signal all remains unchanged in whole calibration process; The control code that switch selects array module 61 to provide according to register and controller module 64 selects in the output analog to digital converter institute will calibrate the common-mode signal of electronic circuit and the benchmark common-mode signal of correspondence; Error quantization module 62 will receive to detect common-mode signal and compare with corresponding benchmark common-mode signal and quantize to obtain quantization code, and quantization code is outputed to register and controller module 64; The needed error correcting code of error correction module 63 work is handled and produced to 64 pairs of these quantization code of register and controller module; Error correction module 63 is calibrated charge coupled sampling-holding circuit in the fully differential structure charge coupling production line analog-digital converter and each electric charge coupling sub level flow line circuit according to the error correcting code that register and controller module provide.When above-mentioned calibration process carries out; Circuit is at first calibrated charge coupled sampling-holding circuit; Secondly to electric charges coupling sub level flow line circuits at different levels by forward direction after calibration step by step; After the common mode calibration of accomplishing afterbody electric charge coupling sub level flow line circuit, whole common mode calibration operation finishes.

The charge coupling assembly line analog to digital converter 70 that provides among Fig. 7 has comprised sub level flow line circuit (701～703), afterbody (n+1 level) the electric charge coupling sub level flow line circuit 704 of a charge coupled sampling-holding circuit 700,3 (n=3) level based on electric charge coupled signal treatment technology.Switch selects array module 71 to select the charge coupled sampling-holding circuit and the common-mode signal of each electric charge coupling sub level flow line circuit to export Vcm (n) successively according to the control code Ctrl (n) that register and controller module 74 provide, simultaneously also according to control code Ctrl (n) selects successively output the benchmark common-mode signal Vr (n) of the electronic circuit that detects correspondence; Error quantization module 72 will receive to detect the margin of error between electronic circuit common-mode signal Vcm (n) and the corresponding benchmark common-mode signal Vr (n) and compare and quantize to obtain quantization code D (n), and quantization code D (n) is outputed to register and controller module 74; Register and 74 pairs of these quantization code of controller module D (n) handle and produce error correction module 73 work needed error correcting code E (n); Error correction module 73 is calibrated charge coupled sampling-holding circuit in the fully differential structure charge coupling production line analog-digital converter and each electric charge coupling sub level flow line circuit according to the error correcting code E (n) that register and controller module provide.

Specify the operation principle of common-mode error calibration circuit shown in Fig. 7 below.

After getting into charge-coupled A/D converter 70, input calibration reference signal at first passes through charge coupled sampling-holding circuit 700; It is used for converting the input reference voltage signal to charge packet Q0p and Q0n that correspondence is in proportion, and this charge packet is transferred to first order electric charge coupling sub level flow line circuit 701; The common mode calibration circuit carries out the common mode calibration to charge coupled sampling-holding circuit 700 earlier; The control code Ctrl (0) that switch selects array module 71 to provide according to register and controller module 74 selects the common-mode signal of charge packet Q0p and the Q0n of producing of charge coupled sampling-holding circuit 700 as output Vcm (0), the array module 71 of switch selection simultaneously also according to control code Ctrl (0) selection charge coupled sampling-holding circuit 700 pairing with reference to common-mode signal as exporting Vr (0); Error quantization module 72 compares the margin of error between the benchmark common-mode signal Vr (0) of charge coupled sampling-holding circuit common-mode signal Vcm (0) that receives and correspondence and quantizes to obtain quantization code D (0), and quantization code D (0) is outputed to register and controller module 74; Register and 74 pairs of these quantization code of controller module D (0) handle and produce error correction module 73 work needed error correcting code E (0); Error correction module 73 is calibrated the common-mode signal of charge coupled sampling-holding circuit in the fully differential structure charge coupling production line analog-digital converter according to the error correcting code E (0) that register and controller module provide; After the common mode calibration of accomplishing charge coupled sampling-holding circuit; Register and controller module 74 select array module 71 employed control code Ctrl (0) to change into Ctrl (1) on switch, and calibration circuit begins the common mode calibration operation of first order electric charge coupling sub level flow line circuit 701.

When calibration circuit begins that first order electric charge coupling sub level flow line circuit 701 carried out the common mode calibration operation; The control code Ctrl (1) that switch selects array module 71 to provide according to register and controller module 74 selects the common-mode signal of surplus charge packet Q1p that first order electric charge coupling 701 couples of Q0p of sub level flow line circuit and Q0n handle to be produced and Q1n as output Vcm (1), simultaneously switch select array module 71 also according to control code Ctrl (1) selection charge coupled sampling-holding circuit 701 pairing with reference to common-mode signal as exporting Vr (1); Error quantization module 72 compares quantification with the common-mode signal Vcm (1) of the first order electric charge that receives coupling sub level flow line circuit 701 with the margin of error between the corresponding benchmark common-mode signal Vr (1) and obtains quantization code D (1), and quantization code D (1) is outputed to register and controller module 74; Register and 74 pairs of these quantization code of controller module D (1) handle and produce error correction module 73 work needed error correcting code E (1); Error correction module 73 is calibrated the common-mode signal of first order electric charge coupling sub level flow line circuit 701 according to the error correcting code E (1) that register and controller module provide; After the common mode calibration of accomplishing first order electric charge coupling sub level flow line circuit 701; Register and controller module 74 select array module 71 employed control code Ctrl (1) to change into Ctrl (2) on switch, and calibration circuit begins the common mode calibration operation of second level electric charge coupling sub level flow line circuit 702.

The common mode calibration circuit carries out the job step of common mode calibration and first order electric charge coupling sub level flow line circuit 701 is carried out the job step of common mode calibration identical to second level electric charge coupling sub level flow line circuit 702; Accomplish when the common mode calibration circuit after the common mode calibration operation of second level electric charge coupling sub level flow line circuit 702; Register and controller module 74 select array module 71 employed control code Ctrl (2) to change into Ctrl (3) on switch, and the common mode calibration circuit begins the common mode calibration operation of back one-level electric charge coupling sub level flow line circuit; By that analogy, accomplish when the common mode calibration circuit after the common mode calibration operation of afterbody electric charge coupling sub level flow line circuit 704, whole common mode calibration operation is accomplished.

As shown in Figure 8, switch select array module 81 comprise a series of switch element circuit 810,811,812 that charge coupled sampling-holding circuit and electric charge at different levels coupling sub level flow line circuit common-mode signal are detected ..., 81n, 81n+1 and switching circuit 815 to selecting with reference to common-mode signal Vr.Wherein, The switch element circuit 810,811,812 that charge coupled sampling-holding circuit and electric charge at different levels coupling sub level flow line circuit common-mode signal is detected ..., 81n, 81n+1 circuit structure identical; And their input is connected to the corresponding differential charge memory node in the detection sub-module circuit of wanting; The common-mode signal of 810 pairs of charge coupled sampling-holding circuit 800 of switch element detects; The common-mode signal of 811 pairs of first order electric charge couplings of switch element sub level flow line circuit 801 detects; The common-mode signal of the 812 pairs of second level of switch element electric charge coupling sub level flow line circuit 802 detects; And the like, switch element 81n detects the common-mode signal of n level electric charge coupling sub level flow line circuit 803, and switch element 81n+1 detects the common-mode signal of afterbody electric charge coupling sub level flow line circuit 804; Switch element circuit 810,811,812 ..., 81n, 81n+1 output be connected to Vcm (n) signal input part that all is connected to error quantization module 82, the selected output of switch element circuit is only arranged in the common mode calibration process.The input of switching circuit 815 is connected to Vr_in, and output is connected to Vr (n) signal input part of error quantization module 82.

Fig. 9 selects to be used in the array module switch element circuit that charge coupled sampling-holding circuit and electric charge at different levels coupling sub level flow line circuit common-mode signal are detected for above-mentioned switch.Circuit basic structure is switching capacity common mode testing circuit, and clock cp and cp1 are two clocks that do not overlap mutually.When clock is in the cp1 phase time, the switch element circuit is sampled to input signal Vip/Vin, and the Vip/Vin signal is sampled on the sampling capacitance 94; When clock is in the cp phase time, be stored in sampling on the sampling capacitance 94 and obtain input signal Vip/Vin and will and output to Vcm (n) by superposition, obtain the common-mode signal of input signal Vip/Vin.

In the circuit shown in Figure 9, be common MOS switch by two switches that clock cp and cp1 controlled that do not overlap mutually.All adopted source follower circuit to the sampling of input signal Vip/Vin with to the output of sampling common-mode signal by clock control; Clock control source follower circuit 91 and 92 is respectively applied for samples to input signal Vip and Vin, and the output of common-mode signal adopts clock control source follower circuit 93 as output buffer.Why detection to common-mode signal in the circuit adopts the clock control source follower circuit, is will detect two difference complementation charge-storage node in charge coupled sampling-holding circuit and the electric charge at different levels coupling sub level flow line circuit because input signal Vip/Vin will be connected respectively to institute.If adopt the source electrode of common MOS sampling switch pipe or drain electrode to be connected to the complementary charge-storage node of difference; Then the complementary charge-storage node of difference attendes institute's charge stored and can share effect with electric capacity 94 generation electric charges through the source electrode or the drain electrode of MOS sampling switch pipe; Making the complementary charge-storage node of difference attend institute's charge stored can change, and detects the common-mode signal size occurrence of errors that obtains thereby make; And adopt the clock control source follower circuit that signal is detected; Because the input signal of source follower circuit is connected to the grid of metal-oxide-semiconductor; Do not exist electric charge to inject and leakage path; Therefore can not make the complementary charge-storage node of difference attend institute's charge stored can change, thereby can realize accurately sampling to common-mode signal.

Figure 10 selects to be used for the switch element circuit to selecting with reference to common-mode signal in the array module for switch shown in Figure 8.Increased a reference signal selector switch array 104 on the basis of switching circuit 100 element circuit in Fig. 9.The reference signal Vr_in that the reference signal of charge coupling assembly line analog to digital converter produces the circuit generation at first selects through reference signal selector switch array 104; Be selected the reference common-mode signal that obtains and be transferred to end points 105, V105 is input with reference to common-mode signal.Circuit is to identical with reference to circuit among the processing procedure of common-mode signal V105 and Fig. 9, controlled by two do not overlap mutually clock cp and cp1.When clock is in the cp1 phase time, the switch element circuit is sampled with reference to common-mode signal V105 to input, and input is sampled on the sampling capacitance 106 with reference to common-mode signal V105; When clock is in the cp phase time, be stored in sampling on the sampling capacitance 106 and obtain input and will and output to Vr (n) by superposition with reference to common-mode signal V105, obtain output with reference to common-mode signal.

Figure 11 is register of the present invention and controller module circuit structure block diagram.Whole register and controller module 110 its internal modules comprise a controller 111 and a M bit register array, wherein M bit register array by n+2 group M bit register (1120,1121,1122 ..., 112n, 112n+1) form.The work store status of controller module 111 control n+2 group M bit registers; Quantization code D (n) generation error correcting code E (the 0)～E (n+1) of M bit register according to input respectively organized in control, and not stopping pregnancy life is used for switch shown in Fig. 8 and selects array module 81 work needed control code Ctrl (n).Specify circuit operation shown in Figure 11 below.

When circuit begins the common mode calibration operation, all n+2 group M bit registers (1120,1121,1122 ..., 112n, 112n+1) the M position error correcting code E (0) that exports～E (n+1) is initial error correcting code, i.e. output is initial value; Controller at first produces first group of calibration control code Ctrl (0) and is used for charge coupled sampling-holding circuit is carried out the common mode calibration; Charge coupled sampling-holding circuit will quantize according to initial error correcting code E (0) 0 generation common-mode error and by error quantization circuit 72; The quantization code D (0) that error quantization circuit 72 produces is imported in the controller 111; Controller 111 produces the needed M of first group of M bit register, the 1120 outputs new error correcting code E (0) 1 in position according to this quantization code D (0); The common-mode signal of charge coupled sampling-holding circuit is calibrated in (0) 1 pair of charge coupling assembly line analog to digital converter of the new error correcting code E in M position that error correction module 73 provides according to register and controller module; After the common mode calibration of accomplishing charge coupled sampling-holding circuit; Controller module 111 selects array module 71 employed control code Ctrl (0) to change into Ctrl (1) on switch; The common mode calibration operation of beginning first order electric charge coupling sub level flow line circuit, first group of M bit register 1120 will be preserved the new error correcting code E (0) 1 in M position of output simultaneously, and remain unchanged; First order electric charge coupling sub level flow line circuit will quantize according to initial error correcting code E (1) 0 generation common-mode error and by error quantization circuit 72; The quantization code D (1) that error quantization circuit 72 produces is imported in the controller 111; Controller 111 produces the needed M of first group of M bit register, the 1121 outputs new error correcting code E (1) 1 in position according to this quantization code D (1); The common-mode signal of first order electric charge coupling sub level flow line circuit is calibrated in (1) 1 pair of charge coupling assembly line analog to digital converter of the new error correcting code E in M position that error correction module 73 provides according to register and controller module; After the common mode calibration of accomplishing first order electric charge coupling sub level flow line circuit; Controller module 111 selects array module 71 employed control code Ctrl (1) to change into Ctrl (2) on switch; The common mode calibration operation of beginning second level electric charge coupling sub level flow line circuit, second group of M bit register 1121 will be preserved the new error correcting code E (1) 1 in M position of output simultaneously, and remain unchanged; By that analogy, accomplish when controller common mode calibration circuit after the common mode calibration operation of afterbody electric charge coupling sub level flow line circuit, n+2 group M bit register 112n+1 will preserve the new error correcting code E in M position (n+1) 1 of output, and remain unchanged; At this moment, controller 111 will control all n+2 group M bit registers (1120,1121,1122 ..., 112n, 112n+1) the M position error correcting code of exporting remains unchanged, whole common mode calibration operation is accomplished.

For common-mode error calibration circuit of the present invention, wherein being provided with of the output quantization code of error quantization module can be a Bits Serial or M (M＞1) parallel-by-bit form, and M is the figure place of register, and its value can be the arbitrary integer greater than 1.The figure place of output quantization code is relevant with the number of its inner employed quantification comparator, if adopt the multi-bit parallel quantization code then need use a plurality of precision comparators; Adopt single precision comparator will obtain among Figure 11 M bit register group and export needed M position error correcting code and then need continuously relatively M time, i.e. the speed of the common mode calibration of Bits Serial output quantization code form is than slow M times of M position output quantization code form.And generally; Analog to digital converter is when being in calibration mode of operation; Calibrating the needed time is not key constraints, calibration process the target that will pursue be precision maximization under the minimum situation of hardware spending, hardware spending is more little good more under identical processing accuracy situation.Therefore the error quantization module adopts the comparator circuit of a high-precision and low-offset voltage just can realize.

Because the error quantization module adopts a comparator; Its output quantization code adopts a Bits Serial data format; Obtain among Figure 11 arbitrary group of M bit register and export needed M position error correcting code and then all need continuously relatively M time, need move all to the common mode calibration operation of arbitrary sub level circuit in charge coupled sampling-holding circuit and the electric charge at different levels coupling sub level flow line circuit promptly that M is individual relatively to quantize the cycle.Suppose that circuit begins first order electric charge coupling sub level flow line circuit is carried out the common mode calibration; And the figure place that M bit register group is exported needed M position error correcting code among Figure 11 is 8; Then needing in the common mode calibration process to carry out recycle ratio than 8 times, to confirm 8 error correcting codes to first order electric charge coupling sub level flow line circuit.

Shown in Figure 12 is error correction modular circuit structured flowchart among the present invention.Error correction module 120 its inside comprise n+2 common mode error correction unit (120,121,122 ..., 12n, 12n+1); The number of common mode error correction unit is Duoed one than the progression of electric charge coupling sub level flow line circuit in the charge-coupled A/D converter, and promptly charge coupled sampling-holding circuit adds the progression of electric charge coupling sub level flow line circuit.N+2 common mode error correction unit (120,121,122 ..., 12n, 12n+1) provide according to displacement and controller module respectively n+2 group error correcting code (E (0), E (1) ..., E (n), E (n+1)) produce the common mode error correction signal that is used for electric charges coupling sub level flow line circuits at different levels.

In charge coupling assembly line analog to digital converter; Signal charge is represented with the form of charge packet size; And the big I of charge packet adopts the form of Q=C*V specifically to realize; Therefore to realize the common mode electric charge in the circuit is compensated, can realize through voltage V or the storage capacitance C that changes charge-storage node in the circuit.In the side circuit, when circuit on the processing line by after being created, the physical device size of circuit is and immobilizes, and realize that bias voltage then can carry out linearity adjustment through external signal to the suitable difficulty of the linearity adjustment meeting of capacitor C size.Therefore, adopt to keep capacitor C constant, and the method for adjustment biasing reference voltage V is easier to realize relatively.

Suppose that the common mode electric charge size that will adjust error correction is Δ Qcm, the error correction voltage of a Δ V then need be provided on the voltage of charge-storage node, Δ V satisfies following formula: Δ V=Δ Qcm/C;

Wherein, C: by charge-storage node capacitance in the error correction electronic circuit; Δ V: the magnitude of voltage that needs error correction; Δ Qcm: the common mode electric charge size that adjust error correction.

Shown in Figure 13 being adopts the common-mode error of adjustment biasing reference voltage V mode to correct the element circuit schematic diagram among the present invention.Error compensation unit circuit 130 comprises an operating state control switch 131, is used for reference voltage V ref is carried out first resistance 1320, second resistance 1321 and the 3rd resistance 1322 of dividing potential drop and the M-bit DAC (digital to analog converter) 133 of adjustment output voltage.When analog to digital converter gets into normal mode of operation; Control signal puts 0; 131 conductings of operating state control switch; First resistance 1320, second resistance 1321 and 1322 couples of reference voltage V ref of the 3rd resistance carry out dividing potential drop and obtain an initial voltage output Vr0, and the M position error correcting code that is produced by displacement and register circuit among Figure 11 will produce the correction current Ic to ground as the control code of M-bit current mode DAC133, and correction current Ic the 3rd resistance 1322 of flowing through arrives ground; Will on resistance 1322, superpose the like this voltage of a Δ V=Ic * R1322 outputs to the voltage Vset=Vr0+ Δ V of reference signal output circuit.Therefore, as long as control M position error correcting code just can realize changing the purpose of output reference voltage.

During practical application; Above-mentioned common mode compensation element circuit realizes adopting distributed frame; Institute's electric charge that uses coupling sub level flow line circuit number can reach tens in the general charge coupling assembly line analog to digital converter, like this to this analog to digital converter carry out common mode compensation the number of the common mode compensation unit that will use with regard to often.And the calibration accuracy of common mode compensation element circuit depends on the precision of its inner M-bit current mode DAC, and obviously high more its precision of DAC figure place is high more, and power consumption and area are also big more simultaneously.Therefore, common mode compensation module complexity and compensation precision depend on the number and the precision of its inner common mode compensation element circuit that uses.Can only be suitably compromise during practical application according to real needs.

As previously mentioned, the charge coupling assembly line analog to digital converter 300 with error correction function at first carries out the common mode calibration steps when being in calibration mode, and next carries out the differential mode calibration steps.Introduce the differential mode calibration circuit below.

Input charge packet signal is stored in respectively on charge-storage node 24p and the 24n in the circuit shown in Figure 2.If input calibration signal is common-mode signal (being that differential signal is 0); And the measure-alike C24p=C24n of the charge storage capacitance on charge-storage node 24p and the 24n, then injecting the charge-storage node 24p and the voltage variety on the 24n that cause by electric charge should equate.Yet in the side circuit because the craft precision problem; The size of the charge storage capacitance on charge-storage node 24p and the 24n and C24p ≠ C24n inequality; But there is a capacitance error amount Δ C; The existence of this Δ C just can make the voltage variety on charge-storage node 24p and the 24n unequal, but has a voltage error amount Δ V, and this voltage error amount Δ V is directly proportional with the input quantity of electric charge under the situation that Δ C fixes; Voltage error amount Δ V just can cause misoperation if surpass the judgement threshold of comparator, and comparator produces erroneous judgement.In addition when electric charge adds reducing; Under the identical situation of reference voltage; The existence of capacitance error amount Δ C just can make the change in electrical charge amount on charge-storage node 24p and the 24n unequal; And having the error of a Δ Q, this charge error amount Δ Q will directly be transferred to next stage sub level circuit, and can accumulate the processing misoperation that causes late-class circuit step by step.

Owing to adopt pipeline organization; Figure adjustment module in the existing pipeline organization analog to digital converter can be carried out error correction to a great extent to the comparator misoperation that factors such as comparator imbalance in the circuit cause, the comparator erroneous judgement misoperation that therefore on existing technology, is caused by above-mentioned capacitance error amount Δ C can be corrected basically.Yet the electric charge that above-mentioned capacitance error amount Δ C causes plus-minus error quantity of electric charge Δ Q but can not be corrected by the figure adjustment module in the existing pipeline organization analog to digital converter, therefore must take other measures to proofread and correct.

The electric charge plus-minus error quantity of electric charge Δ Q that the present invention causes above-mentioned capacitance error amount Δ C carries out Calibration Method and is: a Δ V correction voltage amount is provided on the reference voltage that electric charge is added and subtracted.Suppose that the electric capacity on the positive and negative signal processing channel is respectively C24 and C24-Δ C, the reference voltage that is used for that electric charge is added and subtracted is Vr=Vrp=Vrn, and the charge Q p, Qn and the Δ Q that are added and subtracted in the then positive and negative passage are respectively:

Qp＝C24×Vrp＝C24×Vr

Qn＝(C24-ΔC)×Vrn＝(C24-ΔC)×Vr

ΔQ＝Qp-Qn＝C24×Vrp-(C24-ΔC)×Vrn

＝C24×Vr-(C24-ΔC)×Vr

＝ΔC×Vr

If to adjust its size adjustment be Vrn+ Δ V to being used for reference voltage V rn that electric charge adds and subtracts in above-mentioned negative signal treatment channel, the charge Q p, Qn and the Δ Q that are added and subtracted in the then positive and negative passage are respectively:

Qp＝C24×Vrp＝C24×Vr

Qn＝(C24-ΔC)×(Vrn+ΔV)＝(C24-ΔC)×(Vr+ΔV)

＝C24×Vr+C24×ΔV-ΔC×Vr-ΔC×ΔV

＝C24×Vr+(C24-ΔC)×ΔV-ΔC×Vr

ΔQ＝Qp-Qn＝C24×Vr-C24×Vr-(C24-ΔC)×ΔV+ΔC×Vr

＝-(C24-ΔC)×ΔV+ΔC×Vr

＝ΔC×Vr-(C24-ΔC)×ΔV

In the following formula, if want Δ Q=0, as long as get Δ V=Δ C * Vr/ (C24-Δ C).

Can know by following formula, as long as the calibration of the electric charge plus-minus error quantity of electric charge Δ Q that the regulation voltage that size of increase is Δ V=Δ C * Vr/ (C24-Δ C) on the reference voltage V rn basis that in above-mentioned negative signal treatment channel, is used for electric charge is added and subtracted just can be realized capacitance error amount Δ C is caused.

Realize above-mentionedly realizing that through the reference voltage signal of in the adjustment sub level circuit electric charge being added and subtracted the electric charge plus-minus error quantity of electric charge Δ Q that capacitance error amount Δ C is caused carries out Calibration Method, mechanism, a mechanism and the mechanism of this error quantity of electric charge Δ Q being carried out compensation for calibrating errors that the electric charge plus-minus error quantity of electric charge Δ Q that capacitance error amount Δ C in the circuit is caused quantizes that capacitance error amount Δ C in the circuit is detected need be provided.

Shown in figure 14, the circuit structure that the present invention calibrates the differential mode error that the components and parts mismatch is brought between positive and negative signal processing path in the fully differential structure charge coupling production line analog-digital converter comprises: differential mode error detection module 141, error quantization module 142, error correction module 143 and controller module 144.Wherein, differential mode error detection module 141 is used for producing differential mode error according to the calibration reference signal; Error quantization module 142 is used for the differential mode error that differential mode error detection module 141 produces is quantized; Controller module 144 effects are to control the work of whole calibration circuit; Provide 141 work of differential mode error detection module needed calibration code, and the quantized result of error quantization module 142 is handled the needed error correcting code of generation error correction module 143 work; Error correction module 143 effect is that the error correcting code that provides according to controller module corrects positive and negative signal processing path in the fully differential structure charge coupling production line analog-digital converter.

The operation principle of circuit shown in Figure 14 is: circuit at first sends the calibration mode commencing signal by controller module, and whole differential mode error calibration circuit is started working; System's calibration reference signal of input is to differential mode error detection module 141, and this calibration reference signal all remains unchanged in whole calibration process; The initial error correcting code that calibration code that differential mode error detection module 141 provides according to controller 144 and error correction module 143 provide is handled input calibration reference signal step by step, and differential mode error is handled accumulation step by step and outputed to error quantization module 142 in the processing procedure; Error quantization module 142 quantizes the differential mode error that receives, and quantized result is outputed to controller module 144; 144 pairs of these quantized result of controller module are handled judgement, if quantized result does not reach target call, then controller module produces the needed new error correcting code of error correction module 143 work; Error correction module 143 is calibrated positive and negative signal processing path in the fully differential structure charge coupling production line analog-digital converter according to the new error correcting code that controller module provides; After calibration; The calibration code that differential mode error detection module 141 continues to provide according to controller is handled input calibration charge signal step by step; The differential mode error of accumulating in the processing procedure continues to output to error quantization module 142 and quantizes; Controller judges again that to calibration result circulation successively judges that up to controller module 144 quantized result reaches target call; If quantized result reaches target call, then controller keeps the last error correcting code that produces and produces the calibration end signal, and calibration operation finishes.

In the differential mode error calibration circuit shown in Figure 14, the realization of said differential mode error detection module 141 is accomplished by positive and negative signal processing path in the fully differential structure charge coupling production line analog-digital converter nuclear; The circuit of said error correction module 143 realizes adopting distributed frame, and the error correction module connects the inner a plurality of sub-error correction circuit of control through bus form and realizes; Controller module 144 connects differential mode error detection module 141, differential mode error quantization modules 142 and error correction module 143 the differential mode error calibration operation of realizing analog to digital converter through bus.

Shown in Figure 15, differential mode error detection module 151 is accomplished by positive and negative signal processing path 150 in the fully differential structure charge coupling production line analog-digital converter nuclear.Positive and negative signal processing path 150 comprises charge coupled sampling-holding circuit 1500, n level streamline sub level circuit (1501～1503), afterbody (n+1 level) the electric charge coupling sub level flow line circuit 1504 based on electric charge coupled signal treatment technology in the analog to digital converter nuclear.After handling path 150, input calibration reference signal entering signal at first passes through charge coupled sampling-holding circuit 1500; It is used for converting the input reference voltage signal to reference charge bag that correspondence is in proportion, and this reference charge bag is transferred to first order electric charge coupling sub level flow line circuit 1501; Circuit earlier carries out the differential mode error calibration to first order electric charge coupling sub level flow line circuit 1501, and the reference charge bag that the initial error correcting code E0 that calibration code Cal (0) that first order electric charge coupling sub level flow line circuit 1501 provides according to controller module and error correction module provide obtains sampling is added and subtracted to handle and obtained difference surplus charge packet Q0p and Q0n and this difference surplus charge packet is transferred to the back level electric charge sub level flow line circuit that is coupled; Successively ((E1～En) the difference surplus charge packet that receives is separately handled obtains the difference surplus charge packet Qnp and the Qnn of afterbody electric charge coupling sub level flow line circuit 1504 to each back level sub level flow line circuit (1502,1503,1504) at last for Cal (1～n)) and initial error correcting code according to separately calibration code respectively; The error quantization module compares quantification with the difference surplus charge packet that receives, and quantized result is outputed to controller module; Controller module is handled judgement to this quantized result; If quantized result does not reach target call; Then controller module is made amendment to the E0 that supplies first order sub level flow line circuit to use in the initial error correcting code through processing and is obtained E0, simultaneously the initial error correcting code of other each sub level circuits needed (E1～En) remain unchanged; The reference charge bag that the new error correcting code E0 that first order electric charge coupling sub level flow line circuit 1501 provides according to calibration code Cal (0) and error correction module again obtains sampling is added and subtracted to handle and is obtained difference surplus charge packet Q0p and Q0n and this difference surplus charge packet is transferred to the back level electric charge sub level flow line circuit that is coupled; Successively ((E1～En) the difference surplus charge packet that receives is separately handled again obtains the difference surplus charge packet Qnp and the Qnn of afterbody electric charge coupling sub level flow line circuit 1504 to each back level sub level flow line circuit (1502,1503,1504) again for Cal (1～n)) and initial error correcting code according to separately calibration code respectively; The error quantization module relatively quantizes the difference surplus charge packet that receives again; And new quantized result outputed to controller module; Controller module is handled judgement to this new quantized result; If quantized result does not still reach target call, then the controller module control circuit repeats above-mentioned steps, till controller judges that new quantized result reaches target call; When controller judges that quantized result reaches target call; Controller module is no longer revised the employed error correcting code E0 of first order sub level circuit; And the error correcting code E0 that will produce for the last time is stored in the memory as the final error correcting code of first order sub level circuit and remains unchanged; Controller is accomplished the calibration operation of first order sub level circuit; The surplus charge packet of first order sub level circuit output this moment will be used as back level sub level flow line circuit and calibrate needed reference charge bag signal Q0pr and Q0nr, and circuit begins the calibration operation of second level sub level flow line circuit.

The calibration operation process and the first order sub level circuit of second level sub level flow line circuit are similar; Controller module at first is provided with second level sub level circuit and calibrates needed calibration code Cal (1), and (2～n) all remain unchanged the calibration code Cal of the third level and follow-up other circuit at different levels; The initial error correcting code E1 that second level sub level flow line circuit provides according to calibration code Cal (1) and error correction module adds and subtracts the reference charge bag signal Q0pr of input and Q0nr and handles etc. and first order sub level circuit calibration operation identical operations; When controller judges that quantized result reaches target call; Controller module is no longer revised the employed error correcting code E1 of second level sub level circuit; And the error correcting code E1 that will produce for the last time is stored in the register as the final error correcting code of second level sub level circuit and remains unchanged; Controller is accomplished the calibration operation of second level sub level circuit; The surplus charge packet of second level sub level circuit output this moment will be used as back level sub level flow line circuit and calibrate needed reference charge bag signal Q1pr and Q1nr, and circuit begins the calibration operation of third level sub level flow line circuit.

The calibration operation process of third level sub level flow line circuit and second level sub level circuit are identical, and after the calibration operation of third level sub level flow line circuit was accomplished, circuit was proceeded subsequent stages sub level circuit differential error calibration operation.After afterbody was the calibration completion of n+1 level sub level circuit, controller module produced the calibration end signal, and the differential mode calibration operation finishes.

The level of 1.5bit/ shown in Fig. 2 electric charge coupling sub level flow line circuit is when being operated in calibration mode, and its operating state is with different.Reference signal at the corresponding levels selects the output general of circuit 23p and 23n no longer to be controlled by the comparison quantized result D1D0 of comparator, but is controlled by the calibration code described in Figure 15.Reference signal selecting circuit structure and be in the circuit working schematic diagram under the different working modes in electric charge described in the Fig. 2 of the being shown in Figure 16 coupling sub level flow line circuit.Shown in Figure 16 (a), whole reference signal selects circuit 160 inside to comprise: relatively quantize functional modules such as control logic 161, calibrating signal control logic 162, mode of operation selector switch 163 and reference signal output circuit 164.The comparison quantized result of comparator is through relatively quantizing control logic 161 control output reference signals; The calibration mode control signal is through calibrating signal control logic 162 control output reference signals; The output signal of reference signal output circuit 164 is directly connected to electric charge plus-minus electric capacity.Shown in Figure 16 (b), mode of operation selector switch 163 switches to signal path and relatively quantizes control logic 161, and reference signal is selected the comparison quantized result control of the output of circuit by comparator.Shown in Figure 16 (c), mode of operation selector switch 163 switches to calibrating signal control logic 162 with signal path, and reference signal selects the output of circuit no longer to be controlled by the comparison quantized result of comparator, but by 162 controls of calibrating signal control logic.

Circuit theory diagrams when fully differential structure 1.5bit/ level electric charge coupling sub level flow line circuit is calibrated shown in Figure 17 have been ignored among the figure and have not been in the submodular circuits in the signal loop.Signal path comprises the positive and negative signal path 170p and the 170n of fully differential during calibration mode.Input difference calibration reference charge packet signal is stored in respectively on charge-storage node 174p and the 174n; The calibration code Calp and the Caln that are produced by controller module control calibrating signal control logic 171p and 171n respectively, and the error correcting code Ep and the En that are produced by controller module control sub-error correction circuit 173p and 173n respectively; The output reference voltage of the output reference voltage of the control end control positive signal path 170p of calibrating signal control logic 171p through being connected to reference signal output circuit 172p, the calibrating signal control logic 171n control end control negative signal path 170n through being connected to reference signal output circuit 172n; Sub-error correction circuit 173p is through being connected to the output reference voltage of reference signal output circuit 172p control positive signal path 170p, and sub-error correction circuit 173n is through being connected to the output reference voltage of reference signal output circuit 172n control negative signal path 170n.Sub-error correction circuit described in Figure 17 can adopt common-mode error shown in Figure 13 to correct element circuit and realize.

Shown in Figure 180 by the present invention be used for to the differential mode error detection module a kind of circuit implementation of the error quantization module that quantizes of generation differential mode error.Entire circuit comprise reset switch that 2 charge transfer control switchs (181p and 181n), 2 charge-storage node (184p and 184n), 2 are connected to the charge storage capacitance of charge-storage node, 2 charge-storage node is resetted, a N comparator (1821,1822 ..., 182n).During the circuit operate as normal; Prime differential electrical pocket is at first through 181p and 181n transmission and be stored in charge-storage node 184p at the corresponding levels and 184n; Voltage difference variable quantity and reference signal Vr0～Vrn that N comparator imported between caused node 184p and the 184n the differential electrical pocket compare, and obtain N at the corresponding levels position and quantize output digital code Dn～D0; Digital output code Dn～D0 will output in the controller module shown in Figure 14; At last, reset signal Vset resets to differential charge memory node 184p at the corresponding levels and 184n, accomplishes the work in a complete clock cycle of circuit.

During practical application, the quantified precision of error quantization module shown in Figure 180 and complicated circuit depend on the number and the precision of its inner comparator that uses.The speed of circuit is not key constraints during general calibration mode, and therefore an employed N comparator can use precision comparator as far as possible.For the transformed error that guarantees whole analog to digital converter less than 1LSB, the overall precision of differential mode error calibration circuit should be higher than the conversion accuracy of analog to digital converter, so the error of differential mode error calibration circuit should be less than 1/2LSB.In charge coupling assembly line analog to digital converter; Afterbody electric charge coupling sub level flow line circuit only compares the difference surplus charge packet of front stage circuits and quantizes and do not carry out electric charge and add reducing, the difference surplus charge packet that therefore is transferred to the error quantization module and the afterbody electric charge difference surplus charge packet equal and opposite in direction in the sub level flow line circuit that is coupled.The error that guarantees differential mode error calibration circuit is less than 1/2LSB, and then the number of error quantization comparator that module is used should be more than employed comparator number in the afterbody electric charge coupling sub level flow line circuit.

Shown in Figure 19, differential mode error calibration circuit middle controller module 190 of the present invention comprises: calibration control logic 191, calibration code produce circuit 192, M bit register 193, signal processor 194 and error correcting code and produce circuit 195.When the differential mode error calibration circuit began to get into calibration mode, system gave 191 inputs of calibration control logic an enabling signal, and controller module 190 is started working; Calibration control logic 191 at first produces one group of calibration code and one group of initial error correcting code supplies differential mode error detection module 196 and error correction circuit module 197 to use respectively; Through the processing of certain clock cycle, the error quantization module will feed back to the differential mode error quantized result of one group of M position and be stored in the M bit register 193; Signal processor 194 will be stored in the differential mode error quantized result of the M position in the register 193 and handle judgement; Do not reach target call if judge the differential mode error quantized result of M position; Then signal processor can trigger error correcting code and produces circuit 195 and produce one group of new error correcting code and supply the error correction circuit to calibrate again; After calibration; The error quantization module will feed back to the differential mode error quantized result of one group of new M position and be stored in again in the M bit register 193, and signal processor 194 will be stored in the differential mode error quantized result of the M position in the register 193 and handle judgement again, if quantized result does not still reach target call; Then controller module repeats above-mentioned steps, till controller judges that new quantized result reaches target call; When signal processor 194 judged that quantized result reach target call, signal processor 194 was no longer revised error correcting code, and the error correcting code that will produce for the last time is stored in the memory module 198 as final error correcting code and remains unchanged.

As previously mentioned, the charge coupling assembly line analog to digital converter 300 with error correction function at first carries out the common mode calibration steps when being in calibration mode, and next carries out the differential mode calibration steps.Analog to digital converter 300 withdraws from calibration mode after accomplishing the differential mode calibration steps, gets into the normal data translative mode.In the normal data translative mode, analog to digital converter 300 portion within it calibrates for error and carries out the input common mode voltage offset compensation by 33 pairs of charge coupling assembly line analog to digital converter nuclears 30 of input common mode voltage offset compensating module under the control of controller module 34.Introduce the execution mode of input common mode voltage offset compensating module 33 below.

Shown in figure 20 is a kind of charge coupled sampling-holding circuit commonly used, and this circuit comprises the clock of charge transfer control switch, general MOS switch, sampling capacitance and control circuit work.Here with the most simple sampling with keep the operation principle of two phase clock explanation circuit, the work control clock of side circuit with complicacy many.When sampling clock phase is effective; Input voltage signal is through K switch ts input; Input voltage vin p and Vinn are connected to the climax plate of sampling capacitance; The base plate of sampling capacitance is connected to common-mode voltage Vcmi through K switch bs, input voltage just with the stored in form of a certain amount of electric charge on sampling capacitance; When keeping clock phase effective; The climax plate of sampling capacitance is connected to common-mode voltage Vcmi through K switch th; The sole plate of sampling capacitance is transferred to first order sub level flow line circuit through the charge transfer control switch with the charge packet that preceding half clock phase sample obtains, and accomplishes sampling and keeps function.

In the whole sampling maintenance process, input fully differential voltage signal size is respectively Vinp and Vinn, exports corresponding charge packet size and is Qp and Qn, has following relational expression in the ideal case between them:

Qd＝Qp-Qn＝Vd*Cs＝(Vinp-Vinn)*Cs

$\mathrm{Qcm}=(\frac{\mathrm{Vinn}+\mathrm{<figure-callout\; id="2"\; label="Vinp"\; filenames="HSA00000177492300011.png,HSA00000177492300122.png"\; state="\{\{state\}\}">Vinp</figure-callout>}}{2}+\frac{\mathrm{Von}+\mathrm{Vop}}{2}-2\mathrm{Vcmi})*\mathrm{Cs}$

Wherein:

Cs is the sampling capacitance size;

Vcmi is a benchmark common mode reset signal, and is irrelevant with the input signal size;

Vop/Von is an output reference common mode reset signal, and is irrelevant with the input signal size.

Can find out that through following formula the size of the differential electrical pocket Qd that obtains of sampling hold circuit is proportional with input fully differential voltage signal Vd size in the ideal case.Equally in the ideal case; Common mode input signal

remains unchanged; Output common mode voltage signal

also remains unchanged, and the resulting common mode output charge of charge coupled sampling-holding circuit Qcm just remains unchanged like this.

In the side circuit, the fully differential input signal generally is to handle the differential complement signals that obtains 180 ° of phase differences through single-ended signal input sample coupling circuit outside sheet.Because there are all kinds of non-ideal characteristics in this input sample coupling circuit; The fluctuation of certain amplitude can appear in the common mode electrical level of the differential complement signals of its output; The phase difference of its output differential signal also certain error can occur simultaneously, and just may there be certain common mode offset error in ADC input fully differential signal like this.For the ADC of high dynamic performance, the influence of the caused common-mode error of this input signal must be eliminated or compensate.

For the charge coupled sampling-holding circuit shown in Figure 20, the variation of common mode input signal

will directly influence output common mode quantity of electric charge Qcm.If the variable quantity of common mode input signal Vcm is Δ Vcm, the common mode change in electrical charge amount Δ Qcm=Δ Vcm*Cs that is then introduced in the sampling hold circuit output charge bag.In charge coupling assembly line analog to digital converter, the charge packet that the charge coupled sampling-holding circuit sampling obtains will be delivered in the subsequent stages electric charge coupling sub level flow line circuit and carry out step by step relatively quantification treatment.And follow-up electric charge at different levels coupling sub level flow line circuit when the input charge packet is handled its common mode charge packet size generally remain unchanged and its value size be set to the charge coupled sampling-holding circuit perfect condition under the output common mode charge packet equal.With first order electric charge coupling sub level flow line circuit is example; If the outer input signal of ADC sheet caused charge coupled sampling-holding circuit output common mode charge packet by the Qcm variable quantity Δ Qcm; And the common mode electric charge size that the first order sub level flow line circuit of this moment sets still is Qcm, just has a common mode electric charge delta Qcm between charge coupled sampling-holding circuit output and the first order electric charge coupling sub level flow line circuit like this.The charge packet that obtains in this sampling by the output of charge coupled sampling-holding circuit when the transmission of first order electric charge coupling sub level flow line circuit; Because the existence of this common mode electric charge difference DELTA Qcm; Corresponding variation will appear in the existing initial potential difference when the beginning charge transfer between the charge transfer node; And the variation of this electrical potential difference can influence the efficiency of transmission and the transmission speed of charge packet, thereby causes the charge transfer error.

If adopt a kind of method before charge transfer between above-mentioned charge coupled sampling-holding circuit output and the first order electric charge coupling sub level flow line circuit; In first order electric charge coupling sub level flow line circuit, compensate a common mode electric charge difference DELTA Qcm, make the common mode electric charge size and charge coupled sampling-holding circuit output common mode electric charge equal and opposite in direction of first order electric charge coupling sub level flow line circuit.When charge transfer, the electrical potential difference between charge coupled sampling-holding circuit output and two charge transfer nodes of first order electric charge coupling sub level flow line circuit just can return to desirable initial set value, thereby guarantees the charge transfer precision so.

Realize above-mentionedly obtaining the common-mode signal equal and opposite in direction with the sampling hold circuit sampling through common mode electric charge in follow-up each electric charge coupling sub level flow line circuit is compensated the common mode size that reaches each electric charge coupling sub level flow line circuit of adjustment, thus reach suppress with compensating plate outside the function of input common mode voltage offset error.Circuit, a circuit and the circuit to being compensated by the caused common mode quantity of electric charge of the skew of this common mode input error delta Qcm that the offset Vcm of common mode input in the circuit is quantized that the offset Vcm of common mode input in the circuit is detected need be provided.

Shown in figure 21 is input common mode voltage offset error-detecting and compensating circuit structured flowchart among the present invention.Said input common mode offset error detects and the compensating circuit structure comprises: input common mode offset detection module 211, common mode offset error quantization modules 212, displacement and controller module 23 and error compensation module 214.Wherein, input common mode offset detection module 211 is used for the common mode electrical level of input signal is detected and handles, and obtains importing the offset error amount of common-mode signal; Common mode offset error quantization modules 212 is used for the offset error amount of the input common-mode signal of input common mode offset detection module 211 generations is quantized; Displacement and controller module 213 effects are to control the work of whole common mode detection and compensating circuit, provide 214 work of error compensation module needed error correcting code; The error correcting code that error compensation module 214 effect is to provide according to displacement and controller module compensates the common mode charge signal of each electric charge coupling sub level flow line circuit in the charge coupling assembly line analog to digital converter.

The operation principle of circuit is among Figure 21: input common mode offset detection module 211 at first detects the common mode electrical level of input signal and obtains importing common mode electrical level; And will import common mode electrical level and benchmark common mode electrical level and compare to handle and obtain importing the offset error amount of common-mode signal, and will import the common mode offset error and be transferred to common mode offset error quantization modules 212; Common mode offset error quantization modules 212 quantizes the common mode offset error that receives, and quantized result is outputed to displacement and controller module 213; 213 pairs of these quantized result of controller module are handled judgement, and produce the needed error correcting code EN of error compensation module 214 work; Error compensation module 214 is carried out the common-mode error compensation according to the error correcting code that is shifted and controller module provides to each electric charge coupling sub level flow line circuit in the charge coupling assembly line analog to digital converter; Displacement and controller module departure compensating circuit compensate each charge coupling assembly line common mode electric charge size step by step; Compensate first order sub level circuit earlier; Compensate second level sub level circuit then, compensation successively is up to having compensated afterbody sub level circuit.

Figure 22 is the application block diagram of input common mode voltage offset error compensation circuit of the present invention in the charge coupling assembly line analog to digital converter signal processing channel.Signal processing path 220 comprises charge coupled sampling-holding circuit 2200, n level streamline sub level circuit (2201～2203), afterbody (n+1 level) the electric charge coupling sub level flow line circuit 2204 based on electric charge coupled signal treatment technology in the analog to digital converter.The explanation of circuit working principle is same to be adopted the most simply sampling and keeps the two phase clock explanation.

Control clock when circuit and begin to get into the sampling phase time, input difference analog signal Vinp and Vinn get into the input common mode offset detection module of the present invention's common mode offset compensation circuit when entering signal is handled path 220.Input difference analog signal Vinp and Vinn also are transfused to common mode offset detection circuit 221 and detect the error quantization sign indicating number D (0) that handles and produce N-bit with common mode offset error sample circuit 222 when being handled by charge coupled sampling-holding circuit 2200.And charge packet that charge coupled sampling-holding circuit obtains sampling by the output of sampling hold circuit before the transmission of first order electric charge coupling sub level flow line circuit; Common mode offset error sample circuit 222 should the N-bit error quantization sign indicating number D (0) that produces be transferred to displacement and controller module makes it to produce effective error correcting code E0 (0), and signal is exported in error compensation module 224 compensation of the sub level of first order electric charge coupling all set flow line circuit under the control of E0 (0).Be charge coupled sampling-holding circuit 2200 when being kept switching mutually in opposite directions by sampling, the common mode electric charge size of the destination node that charge packet institute will transmit (first order electric charge be coupled sub level flow line circuit 2201) is through overcompensation.

When circuit control clock begins to get into the maintenance phase time; Charge coupled sampling-holding circuit 2200 accomplish keep in opposite directions switching mutually by sampling after, the charge coupled sampling-holding circuit charge packet that phase sampler obtains of will sample is transmitted to first order electric charge coupling sub level flow line circuit by the output of sampling hold circuit; In the whole maintenance phase process, the error compensation module will remain unchanged to the compensating signal of first order sub level flow line circuit; But simultaneously; Displacement and controller module 223 move circuit by first order sub level flow line circuit data register bank at the N-bit error quantization sign indicating number D (0) that sampling obtains mutually to second level sub level flow line circuit data register bank; Generation is used for second level electric charge coupling sub level flow line circuit is compensated needed error correcting code E1 (0), and error compensation module 224 will be ready for the common mode compensation output signal of second level electric charge coupling sub level flow line circuit under the control of E1 (0).

Begin to get into the sampling phase time of next clock cycle when circuit control clock; Charge coupled sampling-holding circuit 2200, input common mode offset detection circuit 221 and common mode offset error sample circuit 222 repeat the work of previous clock cycle, and obtain one group of new N-bit error quantization sign indicating number D (1); The new N-bit error quantization sign indicating number D (1) that produces will be transferred to displacement and controller module 33 and produce one group and be used for first order sub level flow line circuit is carried out the needed new error correcting code E0 of common mode compensation (1), and error compensation module 224 will be ready for the new compensation output signal of first order electric charge coupling sub level flow line circuit under the control of E0 (1); The sub level of first order electric charge coupling simultaneously flow line circuit carries out the electric charge surplus mutually with last maintenance clock and handles the second level electric charge coupling sub level flow line circuit transmission of surplus charge packet afterwards after the common mode electric charge has passed through error correcting code E1 (0) compensation.

Begin to get into the maintenance phase time of next clock cycle when circuit control clock; Charge coupled sampling-holding circuit 2200, input common mode offset detection circuit 221 and common mode offset error sample circuit 222 repeat the work of previous clock cycle, and the charge coupled sampling-holding circuit charge packet that phase sampler obtains of will sample is transmitted to first order electric charge coupling sub level flow line circuit by the output of sampling hold circuit; Equally, in the whole maintenance phase process, the error compensation module will remain unchanged to the compensating signal of first order sub level flow line circuit; But simultaneously; Displacement and controller module 223 move circuit by first order sub level flow line circuit data register bank at the new N-bit error quantization sign indicating number D (1) that second clock sampling obtains mutually to second level sub level flow line circuit data register bank; Generation is used for second level electric charge coupling sub level flow line circuit is compensated needed error correcting code E1 (1), and error compensation module 224 will be ready for a new common mode compensation output signal of second level electric charge coupling sub level flow line circuit under the control of E1 (1).

When the 3rd clock cycle arrived, charge coupled sampling-holding circuit and at different levels grades of sub level flow line circuits were adopted in a like fashion and are worked; Input common mode offset detection circuit 221 repeats the work of last clock cycle equally with common mode offset error sample circuit 222, and produces one group of new N-bit common-mode error quantization code D (2); Displacement and controller module 223 are when producing new error correcting code E0 (2) according to error quantization sign indicating number D (2), and error quantization sign indicating number D (1) that also will produce preceding two clock cycle and D (0) be to backward shift, generation E1 (1) and E2 (0); Error compensation module 34 produces first, second and the needed common mode compensation signal of third level electric charge coupling sub level flow line circuit of being used for by D (2), D (1) and D (0) control.

When the subsequent clock cycle arrives; Charge coupled sampling-holding circuit 2200, electric charge at different levels coupling sub level flow line circuit, input common mode offset detection circuit 221 and common mode offset error sample circuit 222 repeat the work of last clock cycle equally, and new N-bit common-mode error quantization code D (3), D (4), D (5) are respectively organized in generation successively Displacement and controller module 223 are being organized new error quantization sign indicating number D (3), D (4), D (5) according to each ... And error quantization sign indicating number D (0), D (1), the D (2) of clock cycle generation in the past ... Constantly produce error compensation module 224 needed new error correcting codes to backward shift; Error compensation module 224 produces the needed common mode compensation signal of electric charges coupling sub level flow line circuits at different levels according to the new error correcting code of displacement and the continual renovation that provided of controller module 223.

A kind of realization circuit theory diagrams for input common mode voltage offset error-detecting module among the present invention shown in Figure 23.Circuit comprises two big functional modules, and first functional module is the common-mode voltage detection module, and second functional module is the common mode voltage offset error-detector circuit.First functional module is connected to the equal-sized resistance R c of resistance that Vci, an other end be connected respectively to differential input signal Vinn and Vinp by two one ends and forms; Its role is to the common-mode voltage of differential input signal Vinn and Vinp is detected, obtain the common mode input signal of size for

.Second functional module is the active subtraction circuit with amplification; Circuit adopts the negative feedback of fully differential structure arithmetic amplifier to realize subtraction and enlarging function by 4 resistance R 1, R2, R3 and Rf by one, and obtaining size is the output offset margin of error Vcm_in output after Vci and benchmark common-mode signal Vcm_ref difference are exaggerated.Why common mode offset error amount being amplified, is because the value of side-play amount Vcm_in is generally less, if do not amplify, then following closely the error quantization circuit offset error amount Vcm_in is carried out difficulty that high accuracy quantizes will be very big.

Shown in Figure 24 is the circuit that a kind of operable input common mode voltage offset error that detection is obtained quantizes among the present invention.In fact circuit is exactly the full parallel organization analog-digital converter circuit of a N position.Select full parallel organization analog-digital converter circuit to be because this structural module transducer can be realized the fastest quantification speed; And among the present invention common mode detect and the rate request of compensating circuit higher, the speed of common mode testing circuit should be higher than the speed of institute's compensation charge coupled mode number converter.But, adopt this structure quantizer circuit when realizing the high accuracy quantified precision, can consume more power consumption, so should take all factors into consideration the selection of compromising of multiple factors such as power consumption, speed, precision for the selection of quantizer precision during practical application.

Shown in Figure 25, whole displacement and controller module 250 comprise a controller 251 and a M bit register array, wherein M bit register array by n+1 level M bit register (2521,2522 ..., 252n, 252n+1) form.The work store status of controller module 251 control n+1 level M bit registers; The M bit data generation error correcting code E0～En+1 of M bit register according to input respectively organized in control, and constantly the M bit data of storing in the M bit register at the corresponding levels transferred in back one group of M bit register following closely.The realization of controller can adopt a high performance state machine to realize, also can adopt an embedded MCU control, and the control clock of controller should be controlled clock synchronization with each sub level flow line circuit in the charge coupling assembly line analog to digital converter.In the above-mentioned explanation, M is the figure place of register, and its value can be any positive integer.The N of foregoing N-bit error quantization sign indicating number D (0) should 1≤N≤M.

Circuit operation is following among Figure 25.Begin to get into the sampling phase time of first clock cycle when the control clock; The N-bit error quantization sign indicating number D (0) that common mode offset error sample circuit 252 produces is imported in the first order M bit register 2521, and before clock phase switches, produces the output error correcting code E0 (0) of first order M bit register 2521; This moment, other all odd level M bit register operating states were identical, were in state front stage circuits dateout sign indicating number and that produce new output error correcting code that receives; And all even level M bit registers are keeping its output error correcting code constant to thereafter in the one-level M bit register circuit transmission error quantization sign indicating number; Only this moment, the output of every other M bit register circuit at different levels except that first order M bit register was initial code; Because input common mode offset error quantized signal only is transferred to first order register, the employed common mode offset error of inner other register circuits at different levels quantized signal is initial value.After clock phase was kept switching mutually by sampling in opposite directions, the state of all odd levels and even level M bit register exchanged; First order M bit register 2521 keeps its output error correcting code E0 (0) to remain unchanged on the one hand, on the one hand error quantization sign indicating number D (0) is transferred to second level M bit register 2522 thereafter, and at this moment, the operating state of all odd level M bit registers is identical; All even level M bit registers then are in the state that receives front stage circuits dateout sign indicating number and produce new output error correcting code.

When a clock cycle arrives instantly; Whole shift register array repeats the work in last cycle; Error quantization sign indicating number D (0) data of importing during but last clock cycle have been transferred to second level M bit shift register; And first order M bit shift register receives the common mode offset error sample circuit 222 new error quantization sign indicating number D (1) that produce, other registers at different levels identical with last clock cycle data state.

Whole displacement and controller module 223 be in the every experience of circuit after clock cycle, is stored in the data level M bit register shift transport once (except the afterbody) backward in the M bit registers at different levels.The operating state of the switching of circuit working state and electric charge at different levels coupling sub level flow line circuit is switched synchronously, and in the M bit register array in the sum of series charge-coupled A/D converter of register the progression of electric charge coupling sub level flow line circuit identical.

Shown in Figure 26, error compensation module 260 comprise n+1 common mode compensation unit (261,262 ..., 26n, 26n+1), the number of common mode compensation unit is identical with the progression of electric charge coupling sub level flow line circuit in the charge-coupled A/D converter.N+1 common mode compensation unit (261,262 ..., 26n, 26n+1) provide according to displacement and controller module respectively n+1 group error correcting code (E0, E1 ..., En-1, En) produce the common mode compensation signal that is used for electric charges coupling sub level flow line circuits at different levels.Common mode compensation element circuit described in Figure 26 can adopt common-mode error shown in Figure 13 to correct element circuit and realize.

Therefore; Present embodiment has following advantage: can detect the differential mode error, common-mode error and the input common mode voltage offset error that cause owing to non-ideal characteristic in the fully differential structure charge coupling production line analog-digital converter automatically; And these errors are calibrated; The influence of these errors is controlled in the lowest resolution requirement of analog to digital converter; To overcome error that all kinds of non-ideal characteristic caused problem, further improve the conversion accuracy of existing charge coupling assembly line analog to digital converter to the accuracy limitations of existing charge coupling assembly line analog to digital converter.

Claims (2)

1. the charge coupling assembly line analog to digital converter with error correction function is characterized in that, comprising:

A charge coupling assembly line analog to digital converter nuclear is used for converting analog input signal into digital output code;

A common-mode error calibration module is used for said charge coupling assembly line analog to digital converter nuclear is carried out the common-mode error calibration;

A differential mode error calibration module is used for said charge coupling assembly line analog to digital converter nuclear is carried out the differential mode error calibration;

An input common mode voltage offset compensating module, the input differential signal common mode voltage offset error that is used for the charge coupling assembly line analog to digital converter chip exterior is input to said charge coupling assembly line analog to digital converter nuclear compensates;

The controller module that calibrates for error is used to control the mode of operation of charge coupling assembly line analog to digital converter, also controls the operating state of common-mode error calibration module, differential mode error calibration module and input common mode voltage offset compensating module simultaneously;

The operating state of whole charge coupling assembly line analog to digital converter has two kinds of calibration mode and normal data translative mode; During electrification reset, charge coupling assembly line analog to digital converter at first gets into calibration mode, after the work of accomplishing calibration mode, gets into the normal data translative mode;

In said calibration mode, charge coupling assembly line analog to digital converter carries out the calibration of common mode and differential mode error by common-mode error calibration module and differential mode error calibration module respectively to said charge coupling assembly line analog to digital converter nuclear under the control of the said controller module that calibrates for error; The input common mode voltage offset compensating module will can not be activated in calibration mode; In whole calibration mode, the quantification output code of whole charge coupling assembly line analog to digital converter is a disarmed state;

In said normal data translative mode, charge coupling assembly line analog to digital converter carries out the input common mode voltage offset compensation by the input common mode voltage offset compensating module to said charge coupling assembly line analog to digital converter nuclear under the control of the said controller module that calibrates for error; Said common-mode error calibration module and differential mode error calibration module can not be activated in whole normal data translative mode and only keep its calibration result constant; In whole normal data translative mode, the quantification output code of whole charge coupling assembly line analog to digital converter is an effective status;

In said calibration mode: at first, the controller module that calibrates for error sends control code Ctrl0 and controls said charge coupling assembly line analog to digital converter nuclear entering calibration mode; Then; The controller module that calibrates for error output control code Ctrl1 starts the common-mode error calibration module; The common-mode error calibration module produces error correction signal Cal1 said charge coupling assembly line analog to digital converter nuclear is carried out the common-mode error calibration under the control of control code Ctrl1; When accomplishing the common-mode error calibration operation, control code Ctrl1 is with no longer valid, but error correction signal Cal1 will remain unchanged; Subsequently; The controller module that calibrates for error output control code Ctrl2 starts the differential mode error calibration module; The differential mode error calibration module produces error correction signal Cal2 charge coupling assembly line analog to digital converter nuclear is carried out the differential mode error calibration under the control of control code Ctrl2; When accomplishing the differential mode error calibration operation, control code Ctrl2 is with no longer valid, but error correction signal Cal2 will remain unchanged; At last, the said controller module change control code Ctr10 that calibrates for error controls said charge coupling assembly line analog to digital converter nuclear and withdraws from calibration mode, gets into the normal data translative mode.

2. according to the said charge coupling assembly line analog to digital converter of claim 1, it is characterized in that said controller calibration module comprises: MCU module, ROM module, SRAM module, common mode calibration control logic, differential mode calibration control logic and input common mode voltage offset compensation control logic with error correction function;

Said MCU module plays overall control action, and the control command of all calibration operations is sent by the MCU module;

The ROM module is used for storage calibration control program, and after the charge coupling assembly line analog to digital converter chip manufacture was come out, the calibration control program that is stored on the ROM immobilized;

The SRAM module is used for storing the data that calibration process produces, and plays the effect of metadata cache;

Common mode calibration control logic, differential mode calibration control logic and input common mode voltage offset compensation control logic are worked when the job step that calibrates for error proceeds to common mode calibration, differential mode calibration and input common mode voltage offset compensation process respectively, are respectively the control logic of corresponding calibration steps.

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