CN106788437B - Pipelined analog-to-digital converter and method for increasing sampling rate of analog-to-digital converter - Google Patents
Pipelined analog-to-digital converter and method for increasing sampling rate of analog-to-digital converter Download PDFInfo
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Abstract
The invention provides a pipelined analog-to-digital converter comprising a plurality of pipeline stages, wherein at least one pipeline stage is configured to: a plurality of sub-DACs connected in parallel to each other are connected in series between the sub-ADC and the amplifier, the plurality of sub-DACs being further configured with a plurality of gates, respectively, each of the gates being configured to: when the gating device gates, the sub-DAC corresponding to the gating device is in a working mode; when the gate is closed, the sub-DAC corresponding thereto is in a standby mode. The invention also provides a method for improving the sampling rate of the analog-to-digital converter, which adopts the time domain interleaving technology to improve the sampling rate of the analog-to-digital converter, and simultaneously maintains the advantage of high precision of the pipelined analog-to-digital converter.
Description
Technical Field
The present invention relates to pipelined analog-to-digital converters, and more particularly, to a pipelined analog-to-digital converter based on time-domain interleaving and a method for increasing the sampling rate of the analog-to-digital converter based on the pipelined analog-to-digital converter.
Background
Analog-to-digital converters (ADCs) are used to convert analog signals to digital signals and are widely used in various data acquisition and communication systems, where the sampling rate of the ADC directly determines the signal bandwidth that can be processed. As data bandwidth continues to increase, the sampling rate of ADCs is increasingly required.
There are various architectures for existing ADCs, such as pipelined (pipelined) ADCs, successive Approximation (SAR) ADCs, flash ADCs, time-domain interleaved (interleaved) ADCs, etc. In these architectures, pipelined ADCs are widely used because they achieve both relatively high accuracy and speed.
The time-domain interleaving architecture utilizes a plurality of ADCs with low sampling rate to form an ADC with high sampling rate, which has obvious effect of increasing the sampling rate of the ADC. For example, after time-domain interleaving of N low-speed ADCs with sampling rate fs, the sampling rate of n×fs can be reached. However, this architecture has two significant problems: first, it contains multiple (e.g., N) sub-channels, so the power consumption and area are N times that of each sub-channel; secondly, these N sub-channels introduce a lot of spurs (spurs) into the output spectrum due to gain error (gain error), offset voltage (offset voltage), sampling time offset (timing skew), etc., which greatly limit the accuracy of the ADC, and among these all error sources, the sampling time offset is the most difficult to handle (because it is strongly related to the amplitude, frequency, and manufacturing process and temperature of the input signal).
Therefore, while the sampling rate of the ADC is improved by using the time-domain interleaving architecture, various errors need to be reduced to ensure sampling accuracy.
Disclosure of Invention
To this end, the present invention provides a pipelined analog-to-digital converter comprising a plurality of pipeline stages, wherein at least one of said pipeline stages is configured to: a plurality of sub-DACs connected in parallel to each other are connected in series between the sub-ADC and the amplifier, the plurality of sub-DACs being further configured with a plurality of gates, respectively, each of the gates being configured to: when the gating device gates, the sub-DAC corresponding to the gating device is in a working mode; when the gate is closed, the sub-DAC corresponding thereto is in a standby mode.
Further, at least one of the pipeline stages further comprises a random number generator, at least one of the pipeline stages controls gating and closing of the plurality of gates according to random numbers output by the random number generator, and the frequency of the random numbers output by the random number generator is one random number for each sampling period of the pipeline analog-to-digital converter. The number of the values of the random numbers is the same as the number of the sub-DACs in the waiting mode, the values of the random numbers are in one-to-one correspondence with the sub-DACs in the waiting mode, when the random number generator outputs a certain random number, at least one pipeline stage controls gating of the gating device configured by the sub-DAC corresponding to the certain random number, and simultaneously controls closing of the gating device configured by the other sub-DACs in the waiting mode.
Preferably, the random number generator is configured to generate random numbers using a DEM algorithm, and the amplifier is an operational transconductance amplifier.
The present invention also provides a method of increasing the sampling rate of an analog-to-digital converter for a pipelined analog-to-digital converter, the pipelined analog-to-digital converter comprising a plurality of pipeline stages, the method comprising: at least one of the pipeline stages is configured to: a plurality of sub-DACs which are mutually connected in parallel are connected in series between the sub-ADC and the amplifier, and are respectively provided with a plurality of gates; each of the gates is configured to: when the gating device is gated, the sub-DAC corresponding to the gating device is in a working mode, and when the gating device is turned off, the sub-DAC corresponding to the gating device is in a waiting mode.
Further, the method further comprises: setting a random number generator for at least one pipeline stage, controlling gating and closing of the plurality of gates according to random numbers output by the random number generator, wherein the frequency of the random number output by the random number generator is a random number output by the sampling period of each pipeline analog-to-digital converter. The number of the values of the random numbers is the same as the number of the sub-DACs in the waiting mode, the values of the random numbers are in one-to-one correspondence with the sub-DACs in the waiting mode, and the method further comprises: when the random number generator outputs a certain random number, the gating device configured by the sub-DAC corresponding to the certain random number is controlled to gate, and the gating devices configured by the other sub-DACs in the waiting mode are controlled to be turned off.
Further, the method further comprises: when each sub DAC is in the working mode, in one working period, the following four working phases are sequentially passed: DAC reset, DAC sample phase, amplifier reset, and amplifier setup phase; the sum of the duration of the DAC resetting and DAC sampling phases and the sum of the duration of the amplifier resetting and amplifier establishing phases are one sampling period of the pipelined analog-to-digital converter.
Preferably, the random number generator generates random numbers by adopting a DEM algorithm, and the amplifier is an operational transconductance amplifier.
The pipelined analog-to-digital converter and the method for improving the sampling rate of the analog-to-digital converter adopt the time domain interleaving technology to improve the sampling rate of the analog-to-digital converter, and simultaneously keep the advantage of high precision of the pipelined analog-to-digital converter.
Drawings
FIG. 1 is a schematic diagram of a conventional pipelined analog-to-digital converter;
FIG. 2 is a schematic diagram illustrating one embodiment of a pipeline stage of a pipelined analog-to-digital converter of the present invention;
fig. 3 is a schematic diagram of one example of the operational sequence of fig. 2.
Detailed Description
The pipelined analog-to-digital converter and the method of increasing the sampling rate of the analog-to-digital converter of the present invention are described in further detail below with reference to the accompanying drawings and detailed description, but are not limiting of the invention.
Fig. 1 is a schematic diagram of a conventional pipelined analog-to-digital converter. It comprises an input buffer 40, a plurality of cascaded pipeline stages (e.g. a first pipeline stage 10, a second pipeline stage 20, etc.), and a final stage FLASH ADC 30, the output signals VADC of the pipeline stages are output to a digital correction module 50, and finally spliced to form the digital signal Vout output of the analog-to-digital converter. The number of bits of each pipeline stage may be valued according to the precision requirement, for example, a pipeline analog-to-digital converter including 6 pipeline stages, where the first pipeline stage 10 may be 4 bits, the second pipeline stage 20 to the sixth pipeline stage (not shown in the figure) and the FLASH ADC 30 are all 3 bits, and the final output digital signal Vout is 16 bits.
The pipelined analog-to-digital converter of the present invention is characterized in that the structure of at least one pipeline stage is improved. FIG. 2 is a schematic diagram of an embodiment of a pipeline stage modified according to the present invention. It will be appreciated that the pipelined analog-to-digital converter of the present invention may have some or all of the pipeline stages in this configuration. Preferably, each pipeline stage of the pipelined analog-to-digital converter of the present invention adopts this structure.
Fig. 2 is a schematic diagram of a pipeline stage of the pipelined analog-to-digital converter according to the present invention. A plurality of sub-DACs connected in parallel to each other are connected in series between the sub-ADC 1 and the amplifier 3, and 3 sub-DACs 2a, 2b, 2c are shown in fig. 2. Each sub DAC2a, 2b, 2c receives the signal output from the sub ADC 1, and sends the respective output to the amplifier 3, and the signal Vo amplified by the amplifier 3 is output to the next pipeline stage. The output signal of the sub ADC 1 is also fed to the encoder 4, and the encoded signal VADC is output to the digital correction module 50.
The plurality of sub-DACs 2a, 2b, 2c are also respectively configured with a plurality of gates, shown as a plurality of gate switches sw1, sw2, sw3 in fig. 2. Each gate is configured to: when the gate is on (i.e. gate switches sw1, sw2, sw3 are closed), the sub-DAC 2a, 2b, 2c corresponding thereto is in the operating mode; when the gate is off (i.e. gate switches sw1, sw2, sw3 are open), the sub-DACs 2a, 2b, 2c corresponding thereto are in a standby mode.
When each sub-DAC 2a, 2b, 2c is in the operation mode, in one operation period, the following four operation phases are sequentially passed: a DAC reset phase (DAC reset phase), a DAC sampling phase (sampling phase), an amplifier reset phase (OTA reset phase), and an amplifier setup phase (OTA settling phase). The sum of the duration of the DAC reset phase and the duration of the DAC sampling phase, and the sum of the duration of the amplifier reset phase and the amplifier set-up phase are both one sampling period of the pipelined analog-to-digital converter, i.e. the working mode of each sub-DAC lasts for two sampling periods.
The DAC reset phase is used for removing residual charges on the DAC capacitor array of the last phase so as to reduce distortion in the sampling process; when in the DAC sampling phase, the capacitance of the sub DAC follows the input signal and 'freezes' the input voltage at the sampling ending moment; the amplifier reset phase is used for clearing charges of the last phase remained on the OTA and the feedback capacitor CFB so as to reduce distortion; when the amplifier is in the amplifier establishment phase (OTA settling phase), the sub-DAC array transmits corresponding charges to the feedback capacitor CFB according to the output result of the sub-ADC, and establishes output through OTA.
For each sub-DAC, once it leaves the standby mode to enter the active mode, it must go through the four phases of operation described above in sequence, which constitute a complete working cycle.
Further, the pipeline stage further comprises a random number generator 5, the random number generator 5 outputs a random number every sampling period, and the pipeline stage controls the gating and closing of the plurality of gates according to the output random number every sampling period. In order to facilitate that the number of the random numbers corresponds to the gates, the number of the values of the random numbers is the same as the number of the sub-DACs in the waiting mode, the values of the random numbers correspond to the sub-DACs in the waiting mode one by one, and when the random number generator 5 outputs a certain random number, the pipeline stage controls the gate configured by the sub-DAC corresponding to the random number to gate, and simultaneously controls the gates configured by other sub-DACs in the waiting mode to turn off. Preferably, the random number generator 5 generates random numbers using a dynamic random matching (DEM) algorithm.
In one embodiment, the sub ADC 1 is composed of a plurality of comparators and resistor strings, the sub DACs 2a, 2b, and 2c are each a capacitor array, and the amplifier 3 is an Operational Transconductance Amplifier (OTA).
It will be appreciated that although the number of sub-DACs is 3 in the present embodiment, the number may be any more than one.
In this way, each pipeline stage of the pipelined analog-to-digital converter comprises a plurality of sub-DACs, a plurality of working channels are formed in each pipeline stage, the working channels which need to be used can be randomly selected each time, and the spurious caused by errors such as sampling time deviation can be scattered to noise, so that the spurious-free dynamic range (SFDR) of the analog-to-digital converter is improved.
In addition, since the sub ADC 1 and the amplifier 3 are shared between the plurality of operation channels, the area and power consumption of the analog-to-digital converter are greatly reduced.
The operation principle and timing of each pipeline stage of the pipelined analog-to-digital converter of the present invention are described below with reference to fig. 3. The ADC clock is a master clock of the analog-to-digital converter, and its frequency is equal to the sampling frequency of the analog-to-digital converter. The shaded portion of the figure indicates that the sub-DAC is in standby mode. The sub-ADC in fig. 2 always samples when the ADC clock is high, compares when the ADC clock is low, and outputs the result to the corresponding sub-DAC channel and encoder 4.
As shown in fig. 3, in sampling period T1, sub-DAC <0>2a is assumed to be in DAC reset and DAC sampling phase, sub-DAC <1>2b is assumed to be in amplifier reset and amplifier setup phase, and sub-DAC <2>2c is assumed to be in standby mode.
In the sampling period T2, the sub DAC <0>2a enters the phase of amplifier resetting and amplifier establishing, and the sampling period T2 is still in an operating mode at the beginning of the sampling period, so that the sub DAC <0>2a cannot be selected to execute the sampling task in the period T2; while sub-DAC <1>2b, since it has already performed one duty cycle, is already in standby mode at the beginning of sampling period T2, and can be gated to perform the sampling task; sub-DAC <2>2c may also be gated to perform the sampling task since it is always in standby mode. The analog to digital converter will select which sub-DAC to sample based on the random number generated by the random number generator 5. In this example, the analog-to-digital converter selects sub-DAC <1>2b to perform the sampling task of sampling period T2, which enters the DAC resetting and DAC sampling phase phases; while sub-DAC <2>2c continues to be in standby mode.
Similarly, at the beginning of the sampling period T3, since the sub DAC <0>2a completes one duty cycle, in the idle mode, the sub DAC <0>2a is in a state that can be gated; sub-DAC <1>2b enters the amplifier resetting and amplifier setup phase, i.e. it is still in operation mode and therefore cannot be gated during the T3 period; at the same time, sub-DAC <2>2c is still in idle mode and can be gated. In this example, sub-DAC <2>2c is gated to start into the DAC reset phase and DAC sample phase phases during sample period T3, while sub-DAC <0>2a is in the standby mode.
At the beginning of sampling period T4, since sub-DAC <0>2a is always in idle mode, it is in a state that can be gated; the sub DAC <1>2b performs a working period, enters an idle mode and is in a state of being capable of being gated; sub-DAC <2>2c starts to enter the amplifier resetting and amplifier setup phase, i.e. it is still in operation mode and therefore cannot be gated during the T4 period. In this example, sub-DAC <0>2a is gated to enter the DAC reset phase and DAC sample phase phases during sample period T3, while sub-DAC <1>2b is in the standby mode.
By analogy, the above procedure constitutes the complete operational sequence of one pipeline stage of the analog-to-digital converter.
Although the embodiment shown in fig. 2 and 3 comprises only 3 working channels, i.e. 3 sub-DACs, it will be appreciated that more working channels may be added, i.e. more redundant channels are introduced, so that there are more working channels to choose from at the beginning of each sampling period. Thus, the effect of suppressing the spurious caused by the time domain interleaving is better, but correspondingly, the more the working channels are, the greater the consumption of area and power consumption is.
The above detailed description is only exemplary embodiments of the present invention and should not be taken as limiting the invention, the scope of which is defined by the appended claims. Various modifications and equivalent arrangements of parts may be made by those skilled in the art, which modifications and equivalents are intended to fall within the spirit and scope of the present invention.
Claims (5)
1. A pipelined analog-to-digital converter comprising a plurality of pipeline stages, characterized in that,
at least one of the pipeline stages is configured to: a plurality of sub-DACs connected in parallel with each other are connected in series between the sub-ADC and the amplifier, the plurality of sub-DACs are also respectively provided with a plurality of gates,
each of the gates is configured to: when the gating device gates, the sub-DAC corresponding to the gating device is in a working mode; when the gate is closed, the sub-DAC corresponding thereto is in a standby mode,
at least one of the pipeline stages further comprises a random number generator, at least one of the pipeline stages controls gating and closing of the plurality of gates according to random numbers output by the random number generator, and the frequency of the random numbers output by the random number generator is a random number output by the pipeline analog-to-digital converter for the sampling period of each pipeline analog-to-digital converter; the number of the values of the random numbers is the same as the number of the sub-DACs in the waiting mode, the values of the random numbers are in one-to-one correspondence with the sub-DACs in the waiting mode, when a random number is output by the random number generator, at least one pipeline stage controls gating of the gating device configured by the sub-DAC corresponding to the random number, and simultaneously controls gating devices configured by other sub-DACs in the waiting mode to be closed, wherein the random number generator is configured to generate the random numbers by adopting a DEM algorithm.
2. The pipelined analog-to-digital converter of claim 1 wherein said amplifier is an operational transconductance amplifier.
3. A method of increasing the sampling rate of an analog-to-digital converter for a pipelined analog-to-digital converter, the pipelined analog-to-digital converter comprising a plurality of pipeline stages, comprising:
at least one of the pipeline stages is configured to: a plurality of sub-DACs which are mutually connected in parallel are connected in series between the sub-ADC and the amplifier, and are respectively provided with a plurality of gates;
each of the gates is configured to: when the gating device gates, the sub-DAC corresponding to the gating device is in a working mode, when the gating device is closed, the sub-DAC corresponding to the gating device is in a waiting mode, a random number generator is arranged for at least one pipeline stage, the gating and closing of the gating devices are controlled according to random numbers output by the random number generator, and the frequency of the random number output by the random number generator is a random number output by the sampling period of each pipeline analog-to-digital converter; the number of the values of the random numbers is the same as the number of the sub-DACs in the waiting mode, the values of the random numbers are in one-to-one correspondence with the sub-DACs in the waiting mode, and the method further comprises: when the random number generator outputs a certain random number, the gating device configured by the sub-DAC corresponding to the certain random number is controlled to gate, and the gating devices configured by other sub-DACs in a waiting mode are controlled to be turned off, wherein the random number generator is configured to generate the random number by adopting a DEM algorithm.
4. A method of increasing the sampling rate of an analog to digital converter as claimed in claim 3, further comprising: when each sub DAC is in the working mode, in one working period, the following four working phases are sequentially passed: DAC reset, DAC sample phase, amplifier reset, and amplifier setup phase; the sum of the duration of the DAC resetting and DAC sampling phases and the sum of the duration of the amplifier resetting and amplifier establishing phases are one sampling period of the pipelined analog-to-digital converter.
5. A method of increasing the sampling rate of an analog to digital converter as claimed in claim 3 in which the random number generator generates random numbers using a DEM algorithm and the amplifier is an operational transconductance amplifier.
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| CN107896111B (en) * | 2017-10-16 | 2021-02-26 | 西安电子科技大学 | Pipelined analog-to-digital converter analog front end circuit |
| CN111313901B (en) * | 2020-02-28 | 2021-08-24 | 清华大学 | Threshold voltage generating circuit with jitter function, FlashADC and pipeline ADC |
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