CN106788437A - The method of the sampling rate of flow-line modulus converter and raising analog-digital converter - Google Patents
The method of the sampling rate of flow-line modulus converter and raising analog-digital converter Download PDFInfo
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Abstract
The invention provides a kind of flow-line modulus converter, including multiple pipelining-stages, wherein, pipelining-stage is configured to described at least one：Many sub- DAC being connected in parallel with each other are connected in series between sub- ADC and amplifier, the multiple sub- DAC is also each configured with multiple gates, and each gate is configured to：When the gate is gated, corresponding described sub- DAC is in mode of operation；When the gate is closed, corresponding described sub- DAC is in standby mode.Present invention also offers a kind of method of the sampling rate for improving analog-digital converter, the sampling rate of analog-digital converter is improved using time interleaved modulators, while also retains the high-precision advantage of flow-line modulus converter.
Description
Technical field
It is more particularly to a kind of to be handed over based on time domain the present invention relates to a kind of flow-line modulus converter
Knit the flow-line modulus converter and the raising analog-to-digital conversion based on this analog-digital converter of technology
The method of the sampling rate of device.
Background technology
Analog-digital converter (ADC) is used to for analog signal to switch to data signal, is widely used in each
In kind data acquisition and communication system, and the sampling rate of ADC is directly determined and can processed
Signal bandwidth.With being continuously increased for data bandwidth, the requirement to the sampling rate of ADC
Increasingly improve.
Existing ADC has various frameworks, such as streamline (pipelined) type ADC, gradually forces
Closely (SAR) type ADC, quick flashing (flash) type ADC, time domain interweave (interleaved)
Type ADC etc..In these frameworks, production by assembly line can simultaneously realize precision higher
And speed, thus be used widely.
And time domain intertexture framework is that a sampling high is constituted using the ADC of multiple low sampling rates
The ADC of speed, it is obvious to improving the sampling rate effect of ADC.Such as, adopted N number of
After sample rate carries out time domain intertexture for the low speed ADC of fs, the sample rate of N × fs can be reached.So
And the framework has two significant problems：First, it is logical it comprises (such as N number of) son of multiple
Road, so power consumption and area are N times of each subchannel；Secondly, between this N number of subchannel
Gain error (gain error), offset voltage (offset voltage), sample time offset (timming
) etc. skew factor can in the output spectrum introduce many spuious (spur), significantly limit
The precision of ADC, and in these all of error sources, belong to again sample time offset be most difficult to treatment (because
It is strongly related to temperature with the amplitude of input signal, frequency and manufacturing process).
Therefore, while the sampling rate of ADC is improved using time domain intertexture framework, it is necessary to
Various errors are reduced, to ensure sampling precision.
The content of the invention
Therefore, the invention provides a kind of flow-line modulus converter, including multiple pipelining-stages,
Wherein, pipelining-stage is configured to described at least one：It is connected in series between sub- ADC and amplifier
There are many sub- DAC being connected in parallel with each other, the multiple sub- DAC to be also each configured with multiple
Gate, each gate is configured to：When the gate is gated, corresponding institute
State sub- DAC and be in mode of operation；When the gate is closed, the corresponding son
DAC is in standby mode.
Further, pipelining-stage described at least one also includes random number generator, at least one
The pipelining-stage controls the multiple gating according to the random number that the random number generator is exported
The gating of device and closing, the frequency of the random number generator output random number is described in each
The sampling period of flow-line modulus converter exports a random number.The value of the random number
Number with standby mode described sub- DAC number it is identical, the value of the random number
Corresponded with the described sub- DAC in standby mode, when the random number generator exports certain
During individual random number, pipelining-stage control is corresponding with described certain random number described described at least one
The gate gating that sub- DAC is configured, while controlling other to be in the described of standby mode
The gate that sub- DAC is configured is closed.
Preferably, the random number generator is configured to generate random number, institute using DEM algorithms
Amplifier is stated for operation transconductance amplifier.
Present invention also offers a kind of method of the sampling rate for improving analog-digital converter, for flowing
Pipeline type analog-digital converter, the flow-line modulus converter includes multiple pipelining-stages, the party
Method includes：Pipelining-stage described at least one is configured to：Connected between sub- ADC and amplifier
Many sub- DAC being connected in parallel with each other are connected with, the multiple sub- DAC is also each configured with
Multiple gates；Each gate is configured to：It is right with it when the gate is gated
The described sub- DAC for answering is in mode of operation, when the gate is closed, corresponding institute
State sub- DAC and be in standby mode.
Further, methods described also includes：Pipelining-stage sets random number described at least one
Maker, the multiple gate is controlled according to the random number that the random number generator is exported
Gating and closing, the frequency of random number generator output random number is the stream described in each
The sampling period of pipeline type analog-digital converter exports a random number.The value of the random number
Number with standby mode described sub- DAC number it is identical, the value of the random number with
Described sub- DAC in standby mode is corresponded, and the method also includes：When the random number
When maker exports certain random number, the sub- DAC corresponding with described certain random number is controlled
The gate gating for being configured, while controlling other to be in the described sub- DAC of standby mode
The gate for being configured is closed.
Further, methods described also includes：When each sub- DAC is in mode of operation,
In one work period, following four operating phase is sequentially passed through：DAC resets phase, DAC
Sampling phase, amplifier reset phase and amplifier set up phase；Wherein, the DAC reset mutually and
The duration summation of DAC sampling phases and amplifier reset are mutually and amplifier sets up phase
Duration summation, be a sampling period of the flow-line modulus converter.
Preferably, the random number generator generates random number, the amplification using DEM algorithms
Device is operation transconductance amplifier.
The side of the sampling rate of flow-line modulus converter of the invention and raising analog-digital converter
Method, the sampling rate of analog-digital converter is improved using time interleaved modulators, while also retains
The high-precision advantage of flow-line modulus converter.
Brief description of the drawings
Fig. 1 is the structural representation of existing flow-line modulus converter；
Fig. 2 is one embodiment for pipelining-stage for flow-line modulus converter of the invention
Structural representation；
Fig. 3 is a schematic diagram for example of the work schedule of Fig. 2.
Specific embodiment
With reference to the accompanying drawings and detailed description to flow-line modulus converter of the invention and
The method for improving the sampling rate of analog-digital converter is described in further detail, but not as right
Restriction of the invention.
As shown in figure 1, being the structural representation of existing flow-line modulus converter.Its bag
Input buffer 40, the pipelining-stage of multiple cascades are included (for example, the first pipelining-stage 10, second
Water level 20 etc.) and afterbody FLASH ADC 30, each pipelining-stage output letter
Number VADC output is finally spliced to form the numeral of the analog-digital converter to figure adjustment module 50
Signal Vout is exported.The digit of each pipelining-stage can carry out value according to required precision, for example,
Comprising 6 flow-line modulus converters of pipelining-stage, its first pipelining-stage 10 can be 4 ratios
Spy, the second pipelining-stage 20 to the 6th pipelining-stage (not shown) and FLASH ADC 30
3 bits are, the data signal Vout of final output is 16 bits.
Flow-line modulus converter of the invention, it is mainly characterized in that, flowed at least one
The structure of water level is made that improvement.Fig. 2 show one the one of pipelining-stage after the present invention is improved
The structural representation of individual embodiment.It is understood that pipeline-type modulus conversion of the invention
Device can have part pipelining-stage to use this structure, it is also possible to which whole pipelining-stages use this structure.
Preferably, each pipelining-stage of flow-line modulus converter of the invention uses the structure.
As shown in Fig. 2 being at least one pipelining-stage of flow-line modulus converter of the invention
Structural representation.It is connected in series between sub- ADC 1 and amplifier 3 and is connected in parallel with each other
Many sub- DAC, Fig. 2 show 3, i.e., sub- DAC 2a, 2b, 2c.Each sub- DAC
2a, 2b, 2c receive the signal of the outputs of sub- ADC 1 respectively, and respective output is respectively fed to
Next pipelining-stage is arrived in amplifier 3, the signal Vo outputs after amplified device 3 amplifies.Sub- ADC
1 output signal also sends into encoder 4, the signal VADC outputs after coding to figure adjustment mould
Block 50.
Many sub- DAC 2a, 2b, 2c are also each configured with multiple gates, as indicated with 2 for many
Individual gating switch sw1, sw2, sw3.Each gate is configured to：When gate gating (is selected
Pass sw1, sw2, sw3 is opened up to close) when, at corresponding sub- DAC 2a, 2b, 2c
In mode of operation；When gate closes (i.e. gating switch sw1, sw2, sw3 disconnections),
Corresponding sub- DAC 2a, 2b, 2c is in standby mode (idle mode).
Each sub- DAC 2a, 2b, 2c be in mode of operation when, within a work period, according to
It is secondary by following four operating phase：DAC resets phase (DAC reset phase), DAC are adopted
Sample phase (sampling phase), amplifier reset phase (OTA reset phase) and amplifier are built
Vertical phase (OTA settling phase).Wherein, DAC resets and mutually continues with DAC samplings phase
The summation and amplifier of time reset mutually and amplifier sets up the summation of the duration of phase,
It is a sampling period of flow-line modulus converter, i.e., the every mode of operation of sub- DAC
Continue two sampling periods.
Wherein, DAC reset mutually be used to remove it is residual on a phason DAC capacitor array
Electric charge is stayed, to reduce the distortion in sampling process (distortion)；When sampling phase in DAC,
The electric capacity of sub- DAC follows input signal, and " freezes " input voltage in sampling end moment；
Amplifier resets and is mutually used to understand the upper phase that is remained on OTA and feedback capacity CFB
Electric charge, to reduce distortion；When setting up phase (OTA settling phase) in amplifier, son
DAC arrays according to the output result of sub- ADC to transmitting corresponding electric charge on feedback capacity CFB,
Set up by OTA and exported.
For each sub- DAC, once it leaves standby mode enters mode of operation, it is necessary to
Aforementioned four operating phase is sequentially passed through, this four operating phases constitute a complete work
Make the cycle.
Further, the pipelining-stage also includes random number generator 5, and the random number generator 5 is every
The individual sampling period exports a random number, and each sampling period of the pipelining-stage is random according to output
Count to control gating and the closing of multiple gates.It is corresponding with gate for the ease of random number,
The number of the value of random number is identical with the number of the sub- DAC in standby mode, random number
Multiple values are corresponded with the sub- DAC in standby mode, when random number generator 5 is exported
During certain random number, pipelining-stage controls that choosing that sub- DAC corresponding with the random number is configured
Logical device gating, while the gate for controlling other sub- DAC for being in standby mode to be configured is closed.
Preferably, random number generator 5 is using dynamic random matching (DEM) algorithm generation random number.
In one embodiment, sub- ADC 1 is multiple comparators and resistance string composition, sub- DAC
2a, 2b, 2c are respectively capacitor array, and amplifier 3 is operation transconductance amplifier (OTA).
Although it is understood that the number of the sub- DAC be given in the present embodiment be 3,
Its number can be any more than one multiple.
In this way, each pipelining-stage of flow-line modulus converter of the invention includes many height
DAC, forms multiple service aisles in each pipelining-stage, and can be randomly chosen needs every time
The service aisle to be used, spuious can break up what is caused by sample time offset equal error
With making an uproar, so as to improve the SFDR (SFDR) of analog-digital converter.
Further, since sub- ADC 1 and amplifier 3 are have shared between multiple service aisles, therefore
Significantly reduce the area and power consumption of analog-digital converter.
Each pipelining-stage of flow-line modulus converter of the invention is illustrated referring to Fig. 3
Operation principle and sequential.Wherein, ADC clock are the master clock of analog-digital converter, its frequency etc.
In the sample frequency of analog-digital converter.Dash area represents that the sub- DAC is in standby mode in figure.
Sub- ADC in Fig. 2 is sampled when ADC clock are high all the time, in ADC clock
For it is low when be compared, and output result is to corresponding sub- DAC passages and encoder 4.
As shown in figure 3, in sampling period T1, it is assumed that sub- DAC<0>2a resets in DAC
Mutually with DAC sampling phases, sub- DAC<1>2b is in amplifier and resets and mutually set up phase with amplifier,
Sub- DAC<2>2c is in standby mode.
In sampling period T2, sub- DAC<0>2a is resetted mutually into amplifier and amplifier sets up phase
In the stage, it is also in mode of operation when starting due to sampling period T2, therefore can not be selected at
Sampling task is performed in the T2 cycles；And sub- DAC<1>2b is due to having performed a work week
Phase, so it has been in standby mode at first in sampling period T2, can be strobed
To perform sampling task；Sub- DAC<2>2c is due to being constantly in standby mode, therefore it also may be used
Sampling task is performed to be strobed.Analog-digital converter can be produced according to random number generator 5
Which sub- DAC is random numbers select perform sampling.In this example, analog-digital converter selection
Sub- DAC<1>2b performs the sampling task of sampling period T2, and it enters DAC reset phases
Sampled the phase stage with DAC；And sub- DAC<2>2c then keeps standby mode.
Similarly, when the sampling period, T3 started, due to sub- DAC<0>2a completes a work
Make the cycle, be thus in idle pulley, sub- DAC<0>2a is the state that can be strobed；Son
DAC<1>2b is resetted mutually into amplifier and amplifier sets up the phase stage, i.e., it is also in work
Pattern, therefore can not be strobed within the T3 cycles；Meanwhile, sub- DAC<2>2c is remained in
Idle pulley, can be strobed.In this example, in sampling period T3, sub- DAC<2>
2c is strobed and initially enters DAC resets mutually and the DAC sampling phase stages, and sub- DAC<0>2a
Then it is in standby mode.
When the sampling period, T4 started, due to sub- DAC<0>2a is constantly in idle pulley,
It is the state that can be strobed；Sub- DAC<1>2b has performed a work period, into sky
Not busy pattern, is also the state that can be strobed；Sub- DAC<2>2c initially enters amplifier reset
Mutually and amplifier sets up the phase stage, i.e., it is also in mode of operation, therefore can not be within the T4 cycles
It is strobed.In this example, in sampling period T3, sub- DAC<0>2a is strobed beginning
Resetted into DAC and mutually sampled the phase stage with DAC, and sub- DAC<1>2b is then in wait mould
Formula.
The rest may be inferred, and said process constitutes the complete work of a pipelining-stage of analog-digital converter
Make sequential.
Although only including 3 service aisles in the embodiment shown in Fig. 2 and 3, i.e., including 3
Sub- DAC, but it is understood that, more service aisles can be added, that is, introduce more
Redundant channel, to cause that it is for selection that each sampling period begins with more service aisles.
In this way, the spuious inhibition for causing that interweaves to time domain is just more preferable, but correspondingly, work is logical
Road is more, and the consuming to area and power consumption is bigger.
Above specific embodiment is only illustrative embodiments of the invention, it is impossible to for limiting
The present invention, protection scope of the present invention is defined by the claims.Those skilled in the art can be with
In essence of the invention and protection domain, various modifications or equivalent are made to the present invention,
These modifications or equivalent also should be regarded as being within the scope of the present invention.
Claims (10)
1. a kind of flow-line modulus converter, including multiple pipelining-stages, it is characterised in that
Pipelining-stage is configured to described at least one：It is connected in series between sub- ADC and amplifier
Many sub- DAC being connected in parallel with each other, the multiple sub- DAC are also each configured with multiple choosings
Logical device,
Each gate is configured to：When the gate is gated, the corresponding son
DAC is in mode of operation；When the gate is closed, corresponding described sub- DAC
In standby mode.
2. flow-line modulus converter according to claim 1, it is characterised in that extremely
A few pipelining-stage also includes random number generator, and pipelining-stage described at least one is according to institute
The random number of random number generator output is stated to control gating and the closing of the multiple gate,
The frequency of the random number generator output random number is the pipeline-type modulus conversion described in each
The sampling period of device exports a random number.
3. flow-line modulus converter according to claim 2, it is characterised in that institute
The number for stating the value of random number is identical with the number of the described sub- DAC in standby mode, institute
The value and the described sub- DAC in standby mode for stating random number are corresponded, when described random
Number makers are when exporting certain random number, pipelining-stage control described at least one with it is described certain with
The gate gating that the corresponding sub- DAC of machine number is configured, while controlling other to be in
The gate that the described sub- DAC of standby mode is configured is closed.
4. flow-line modulus converter according to claim 2, it is characterised in that institute
Random number generator is stated to be configured to generate random number using DEM algorithms.
5. flow-line modulus converter according to claim 1, it is characterised in that institute
Amplifier is stated for operation transconductance amplifier.
6. a kind of method of the sampling rate for improving analog-digital converter, turns for pipeline-type modulus
Parallel operation, the flow-line modulus converter includes multiple pipelining-stages, it is characterised in that including：
Pipelining-stage described at least one is configured to：It is connected in series between sub- ADC and amplifier
There are many sub- DAC being connected in parallel with each other, the multiple sub- DAC to be also each configured with multiple
Gate；
Each gate is configured to：When the gate is gated, corresponding is described
Sub- DAC is in mode of operation, when the gate is closed, corresponding described sub- DAC
In standby mode.
7. it is according to claim 6 improve analog-digital converter sampling rate method, its
It is characterised by, also includes：Pipelining-stage sets random number generator described at least one, according to
The random number of random number generator output controls gating and the pass of the multiple gate
Close, the frequency of the random number generator output random number is the pipeline-type modulus described in each
The sampling period of converter exports a random number.
8. it is according to claim 7 improve analog-digital converter sampling rate method, its
It is characterised by, the number of the value of the random number is with the described sub- DAC's in standby mode
Number is identical, and the value of the random number is corresponded with the described sub- DAC in standby mode,
The method also includes：When the random number generator exports certain random number, control with it is described
The gate gating that the corresponding sub- DAC of certain random number is configured, while controlling it
The gate that the described sub- DAC that he is in standby mode is configured is closed.
9. it is according to claim 6 improve analog-digital converter sampling rate method, its
It is characterised by, also includes：When each sub- DAC is in mode of operation, in a work period
It is interior, sequentially pass through following four operating phase：DAC resets phase, DAC samplings phase, amplification
Device reset phase and amplifier set up phase；Wherein, the DAC resets phase and DAC sampling phases
Duration summation and the amplifier resets mutually and amplifier sets up duration of phase
Summation, is a sampling period of the flow-line modulus converter.
10. it is according to claim 7 improve analog-digital converter sampling rate method,
Characterized in that, the random number generator generates random number, the amplification using DEM algorithms
Device is operation transconductance amplifier.
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| CN107896111A (en) * | 2017-10-16 | 2018-04-10 | 西安电子科技大学 | Flow-line modulus converter analog front circuit |
| CN111313901A (en) * | 2020-02-28 | 2020-06-19 | 清华大学 | Threshold voltage generating circuit with jitter function, FlashADC and pipeline ADC |
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| Publication number | Publication date |
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| CN106788437B (en) | 2024-02-27 |
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