CN113014263B - Capacitor array and switch logic circuit of successive approximation type ADC - Google Patents

Capacitor array and switch logic circuit of successive approximation type ADC Download PDF

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CN113014263B
CN113014263B CN202110257650.4A CN202110257650A CN113014263B CN 113014263 B CN113014263 B CN 113014263B CN 202110257650 A CN202110257650 A CN 202110257650A CN 113014263 B CN113014263 B CN 113014263B
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comparator
polar plate
capacitor
vrefp
vrefn
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CN113014263A (en
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孙杰
闫成刚
刘伟强
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Nanjing University of Aeronautics and Astronautics
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Nanjing University of Aeronautics and Astronautics
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a capacitance array and a switch logic circuit of a successive approximation type ADC (analog to digital converter), which comprises two groups of DAC (digital to analog converter) arrays, three comparators and an SAR logic circuit; the DAC array adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before each step of quantization begins, and meanwhile, the upper polar plate of the capacitor is connected with the input end of the comparator and is short-circuited to the common-mode voltage VCM; disconnecting the upper polar plate from the common mode voltage VCM when sampling is completed, disconnecting the lower polar plate from the input signal, and connecting the lower polar plate to a preset fixed voltage to perform 2-bit data quantization in the first step; and the SAR logic output signal controls the capacitor lower polar plate voltage of the step to generate the threshold value of the next quantization. The invention can eliminate the problem that a period of time is needed to be inserted as a pre-charge phase before each comparator works in order to generate different thresholds in the traditional 2b/cycle structure or even higher-order structure, and can realize simple switch control logic.

Description

Capacitor array and switch logic circuit of successive approximation type ADC
Technical Field
The invention relates to the technical field of successive approximation type ADCs, in particular to a capacitor array and a switch logic circuit of a successive approximation type ADC.
Background
Modern high-speed communication systems, such as ultra-bandwidth radios, high-speed serial links, and ethernet transceivers, require analog-to-digital converters with medium resolution and hundreds of megasample rates, and common types of high-speed ADCs are mainly full-parallel (Flash) ADCs, pipelined (Pipeline) ADCs, and Successive Approximation (SAR) ADCs. The 2b/cycle SAR ADC is an idea of combining with FlashADC, and a plurality of comparators are introduced into a traditional 1b/cycle 1e SARADC structure to compare a multi-bit structure in parallel at a time, so compared with a 1b/cycle mode, the analog ADC can achieve the same resolution through fewer comparison times, and has the main advantage of improving the speed of the successive approximation type ADC.
However, since the conventional 2b/cyc1e SAR ADC is composed of a plurality of DACs and requires a precharge operation to generate different threshold voltages to complete each comparison, this incurs additional overhead in time and power consumption, which not only reduces the efficiency and speed of conversion, but also makes the architecture more sensitive to temperature and voltage factor variations due to additional phase and logic operations. Especially when the number of bits of the ADC is higher, the time and power consumption required to be occupied will be greater.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a capacitor array and a switch logic circuit of a successive approximation type ADC, which can eliminate the problem that a period of time is needed to be inserted as a pre-charge phase before a comparator works each time in order to generate different thresholds in the traditional 2b/cyc1e structure or even higher-order structure, and can realize simple switch control logic.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a capacitance array and a switch logic circuit of a successive approximation type ADC, wherein the capacitance array and the switch logic circuit comprise two groups of DAC arrays, three comparators and an SAR logic circuit;
the DAC array comprises 2 n+1 The positive and negative differential input ends of the unit capacitors are respectively provided with 2 n A unit capacitor, n is the number of bits of the ADC; each step of quantization process control corresponds to 4 unit capacitors, the unit capacitors corresponding to each step of quantization process control are not repeated, and the capacitor weight of the j-th step of quantization corresponding control is as followsAnd->
The DAC array adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before each step of quantization begins, and meanwhile, the upper polar plate of the capacitor is connected with the input end of the comparator and is short-circuited to a common-mode voltage VCM; when sampling is completed, the connection between the upper polar plate and the common-mode voltage VCM is disconnected, the connection between the lower polar plate and an input signal is disconnected, the lower polar plate is connected to a preset fixed voltage, and a threshold resetting operation required by first-step quantization comparison is generated while the charge of the lower polar plate is transferred to the upper polar plate, so that the comparator starts to work to perform first-step 2-bit data quantization;
the input end of the SAR logic circuit is connected with the output end of the comparator, the output end of the SAR logic circuit is connected with the lower polar plate switch grid electrode of the DAC array, so that each step of quantization of the DAC array is realized, and the capacitor lower polar plate voltage of the step is controlled by the SAR logic output signal so as to generate a new threshold value required by the next step of quantization.
In order to optimize the technical scheme, the specific measures adopted further comprise:
further, resetting the lower electrode plate of the capacitor array to preset fixed reference levels Vrefp and Vrefn after sampling is set;
the three comparators are a first comparator, a second comparator and a third comparator respectively; the lower electrode plates of the capacitors at the same phase end of the first comparator are respectively connected to Vrefp, vrefp, vrefn, vrefp, and the lower electrode plates of the capacitors at opposite phase ends of the first comparator are respectively connected to Vrefn, vrefn, vrefp, vrefn; the lower electrode plates of the capacitors at the same phase end of the third comparator are respectively connected to Vrefn, vrefn, vrefp, vrefn, and the lower electrode plates of the capacitors at opposite phase ends of the third comparator are respectively connected to Vrefp, vrefp, vrefn, vrefp; the non-inverting end of the second comparator is connected with the non-inverting end of the first comparator, and the inverting end of the second comparator is connected with the inverting end of the third comparator; wherein vref=vrefp-Vrefn such that the equivalent thresholds of the first comparator, the second comparator, and the third comparator are-1/2×vref, 0, and 1/2×vref, respectively;
the SAR logic circuit judges the position of the Vip-Vin falling between the three thresholds according to the results of the three comparators to obtain 2-bit data in the first step;
the lower 4-bit capacitor is connected with Vin in the sampling process, and is connected with Vrefp or Vrefn in the resetting process according to the quantity ratio of 3:1 so as to construct the total capacitor of the integer power of 2 and form the corresponding threshold voltage of the comparator.
Further, three of the four capacitors at the lowest position in the DAC at two ends of the comparator are connected with Vrefp, and the other capacitor is connected with Vrefn.
Further, two differential capacitors of the lowest-order capacitors are connected with the same Vrefp or Vrefn, and the other two differential capacitors are connected with a common-mode voltage.
Further, the output quantized result of the SAR logic circuit is connected to the lower plate switch grid of the DAC array, and the level of the lower plate of the in-phase end capacitor array of the first comparator and the third comparator is subjected to D of the output quantized result<i>Control, the electrode plate level under the capacitor array of the reversed phase end is output with the quantized resultControl continues to quantize the signal to generate new three thresholds.
Further, the capacitor array and the switching logic circuit comprise 2 M -1 comparator with a high-order capacitance split ratio of (2 M -1) to 1; m is a positive integer greater than or equal to 2.
The beneficial effects of the invention are as follows:
the invention provides a 2 b/cycle-oriented capacitor array and a switch logic circuit of a Successive Approximation-Register (SAR) Analog-to-Digital Converter Analog-to-digital converter (ADC). The circuit generates three different thresholds respectively through two groups of Digital-to-Analog (DAC) arrays and three comparators during each quantization step, so as to realize the function of outputting 2-bit data in each step. The invention also realizes a very simple switch control logic scheme, and the switching of the capacitor array is realized by the output of the SAR logic circuit at the rear end part of the circuit, namely the quantized result D of each step<i>Or after it has passed through an inverterTo control directly so that a corresponding threshold value for the next quantization can be generated.
Drawings
Fig. 1 is a schematic diagram of a capacitive array and switching logic of a successive approximation ADC.
Fig. 2 is a schematic diagram of a reset phase of a capacitor array.
Fig. 3 is a schematic diagram of a switching phase of a capacitor array.
FIG. 4 is a schematic diagram of a 2b/cycle 8-bit SARADC oriented capacitor array.
FIG. 5 is a diagram showing the quantization of 2b/cycle 8-bit SARADC.
FIG. 6 is a schematic diagram of the operational timing sequence of a 2b/cycle 8-bit SAR ADC.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings.
It should be noted that the terms like "upper", "lower", "left", "right", "front", "rear", and the like are also used for descriptive purposes only and are not intended to limit the scope of the invention in which the invention may be practiced, but rather the relative relationship of the terms may be altered or modified without materially altering the teachings of the invention.
In connection with fig. 1, the present invention refers to a capacitive array and switching logic circuit of a successive approximation ADC, comprising two sets of DAC arrays, three comparators and SAR logic circuits.
The DAC array comprises 2 n+1 The positive and negative differential input ends of the unit capacitors are respectively provided with 2 n A unit capacitor, n is the number of bits of the ADC; each step of quantization process control corresponds to 4 unit capacitors, the unit capacitors corresponding to each step of quantization process control are not repeated, and the capacitor weight of the j-th step of quantization corresponding control is as followsAnd->
The DAC array adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before each step of quantization begins, and meanwhile, the upper polar plate of the capacitor is connected with the input end of the comparator and is short-circuited to a common-mode voltage VCM; and when the sampling is finished, the connection between the upper polar plate and the common-mode voltage VCM is disconnected, the connection between the lower polar plate and an input signal is disconnected, the lower polar plate is connected to a preset fixed voltage, and the threshold resetting operation required by the first-step quantization comparison is generated while the charge of the lower polar plate is transferred to the upper polar plate, so that the comparator starts to work to perform the first-step 2-bit data quantization.
The input end of the SAR logic circuit is connected with the output end of the comparator, the output end of the SAR logic circuit is connected with the lower polar plate switch grid electrode of the DAC array, so that each step of quantization of the DAC array is realized, and the capacitor lower polar plate voltage of the step is controlled by the SAR logic output signal so as to generate a new threshold value required by the next step of quantization.
For an n-bit ADC, the positive and negative differential inputs thereof each require 2 n A total of 2 are required for the ADC per unit capacitance n+1 The unit capacitance adopts a 2b/cycle schemeThe step quantization operation, each step of the controlled capacitance has 4, the four capacitance weights are 4:4:3:1, wherein the step 1 quantization corresponds to the controlled capacitance weight of +.>Step 2, quantifying the capacitance weight of the corresponding control to be +.>And so forth->The capacitance weight of the corresponding control of the step quantization is 4 multiplied by 4 0 ，4×4 0 ，3×4 0 ，1×4 0 . The circuit adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before each step of quantization begins, and the upper polar plate of the capacitor is connected with the input end of the comparator and is short-circuited to a common-mode voltage V CM Disconnecting the upper polar plate from V when sampling is completed CM The lower polar plates are disconnected from the input signal and are connected to a preset fixed voltage, the threshold reset operation required by the first step of comparison is generated while the charge of the lower polar plates is transferred to the upper polar plates, and the comparator starts to work after the DAC is established to quantize the 2-bit data of the first step. The method of splitting the capacitor can be generalized to quantization of 3 bits/cycle or higher, for example, when used for M bits/cycle, a total of 2 M -1 comparator with a high-order capacitance split ratio of (2 M -1) to 1 can realize similar functions.
After the quantization of the first step is finished, the control of the reset signal on the four capacitors of the step is turned off, and the capacitor of the step is controlled by the SAR logic output quantization signal to generate a new threshold value.
According to the capacitor array of the successive approximation type ADC facing to the 2b/cycle, no additional precharge operation is needed for each step of quantization, and only similar operation as that of the traditional SAR ADC is needed, namely, the SAR logic output controls DAC switching to perform next operation, so that the generation of a needed new threshold value can be realized, and a large amount of precharge time and power consumption are saved. The reset phase after sampling resets the bottom plates of the capacitor array to preset fixed levels Vrefp and Vrefn, wherein the bottom plates of the capacitors at the in-phase end of CMP1 are respectively connected to Vrefp, vrefp, vrefn, vrefp and the bottom plates of the capacitors at the opposite phase end are respectively connected to Vrefn, vrefn, vrefp, vrefn, and the bottom plates of the capacitors at the in-phase end of CMP3 are respectively connected to Vrefn, vrefn, vrefp, vrefn and the bottom plates of the capacitors at the opposite phase end are respectively connected to Vrefp, vrefp, vrefn, vrefp.
Wherein, due to the weight distribution of 4:4:3:1 and assuming Vref=Vrefp-Vrefn, the voltage value of the non-inverting terminal of CMP1 at the beginning of the comparison of the first step isThe voltage value of the inverting terminal is Thus the value of CMP1 comparison is V ip -V in Whether +1/2Vref is greater than 0, the equivalent threshold is-1/2 Vref, the equivalent thresholds of the same CMP2 and CMP3 are 0 and 1/2Vref, so that V can be judged according to the results respectively output by the three comparators ip -V in The position falling between the three thresholds is used for obtaining 2-bit data in the first step; low 4-bit capacitor at sampling phase V in The Vrefp or Vrefn is connected according to 3:1 during resetting to construct the total capacitance of the integer power of 2 andforming a corresponding comparator threshold voltage. In the conversion process up to the last step, three connections Vrefp and one connection Vrefn are arranged in the four Cu capacitors at the lowest bit in the DACs at the two ends of the comparator. There are many equivalent connections for the lowest capacitance. For example, two of them are connected to Vrefp and the other two are connected to common mode voltage. Connecting the two differential capacitors with the same Vrefp or Vrefn can realize differential zero level through the connection of the equivalent common mode voltage.
After the quantization result is output in the first step, the control of the reset signal on the four capacitors in the step is turned off, and the voltage of the lower polar plate of the capacitor in the step is controlled by the SAR logic output signal to generate a new threshold value. Wherein the output quantized result of SAR logic is connected to the lower plate switch gate of DAC capacitor array, and the in-phase end capacitor array lower plate level of CMP1 and CMP3 is subjected to D of output quantized result<i>Control, the electrode plate level under the capacitor array of the reversed phase end is output with the quantized resultControl, then generate new three thresholds on the same principle to continue quantizing the signal; the method has the advantages that the three comparator outputs directly control the corresponding capacitance pole plate switches, so that the logic circuit is simplified, and the quantization speed is further improved.
FIG. 1 is a schematic diagram of a dedicated n-bit capacitor array in this embodiment, which is composed of two DAC arrays DAC1 and DAC2 and three comparators CMP3, CMP2 and CMP1, which can generate D respectively 3 <i>、D 2 <i>、D 1 <i>And a three-bit quantization result, wherein the quantization result is used for controlling the grid electrode of the lower polar plate switch of the capacitor. An n-bit SAR ADC is commonly requiredFour capacitors are controlled in each step of quantization operation, and the capacitors in each step are rearranged into a weight ratio of 4:4:3:1 by a capacitor segmentation method. In addition, the circuit adopts a mode of sampling a lower polar plate, and the lower polar plate of the capacitor and an input signal V are connected before each quantization step begins in And V ip Connection sampling, at this timeThe capacitive plate is connected with the input end of the comparator and is short-circuited to the common mode level V CM Disconnecting the upper polar plate from V when sampling is completed CM Simultaneously disconnect their lower plates from the input signal to effect charge transfer of the lower plates so that the in-phase terminal voltage of the comparator is V CM -V in Its inverting terminal voltage is V CM -V ip . After the sampling phase is finished, the DAC capacitor array is reset, as shown in fig. 2, before the first-step quantization is started, the capacitor array needs to be reset by using preset fixed levels Vrefp and Vrefn, each step of capacitor at the in-phase end of CMP3 is connected with a fixed level with a value of Vrefn, vrefn, vrefp, vrefn, and the opposite-phase end is connected with a fixed level with a value of Vrefp, vrefp, vrefn, vrefp; similarly, the lower plates of the capacitors of the same phase end of the CMP1 are respectively connected to Vrefp, vrefp, vrefn, vrefp and the lower plates of the capacitors of the opposite phase end are respectively connected to Vrefn, vrefn, vrefp, vrefn, and Vref=Vrefp-Vrefn is assumed, so that the voltage of the same phase end of the CMP1 is +.>The voltage at the inverting terminal is +.>Thus the value of CMP1 comparison is V ip -V in Whether +Vref/2 is greater than 0, the equivalent threshold is-Vref/2, the equivalent thresholds of the same CMP2 and CMP3 are 0 and Vref/2 respectively, so that V can be judged according to the results output by the three comparators respectively ip -V in And (3) falling in the position between the three thresholds to obtain the 2-bit data of the first step. After the reset is finished, the SAR ADC starts each step of conversion, as shown in FIG. 3, the first step is to obtain three quantized output signals D by three comparators 3 <1>D 2 <1>D 1 <1>The grid electrodes of the electrode plate switches under the capacitor arrays at the same phase ends of the CMP3 and the CMP1 are controlled, and then the access signals of the electrode plates under the capacitors are controlled to be Vrefp or Vrefn; the gates of the plate switches under the inverted-end capacitor arrays of CMP3 and CMP1 are not +.>And (5) controlling.
As shown in fig. 4, the lower plate of this 8-bit capacitor array has been connected to a preset fixed voltage. The reference level Vrefp is denoted by 1, vrefn is denoted by 0, and then the preset fixed voltages of each step of capacitor access at the in-phase end of CMP3 are 0, 1, 0, and the preset fixed voltages of each step of capacitor access at the opposite phase end are 1, 0, and 1, and the preset fixed voltage connection method of CMP1 is shown in fig. 4. Due to the weight distribution of the capacitance 4:4:3:1 and assuming Vref=Vrefp-Vrefn, the voltage value at the non-inverting terminal of CMP3 at the beginning of the first step comparison is V CM -V in +64/256×Vrefp+192/256×Vrefn, and the voltage value at the inverting terminal is V CM -V ip +192/256×Vrefp+64/256×Vrefn, so that the value compared by CMP3 is V ip -V in Whether 1/2×Vref is greater than 0, the equivalent threshold is 1/2×Vref, the equivalent thresholds of the same CMP2 and CMP1 are 0 and-1/2 Vref, and V is determined according to three equivalent thresholds of 1/2×Vref, 0 and-1/2×Vref respectively generated by CMP3, CMP2 and CMP1 ip -V in Falling between the above three thresholds to obtain quantized output result, and using D 3 <i>D 2 <i>D 1 <i>To represent. A total of four quantization results are produced, namely: 111. 011, 001, 000, wherein 011 denotes V ip -V in The other quantization results are the same in the interval of 0 to 1/2 XVref, thereby obtaining the 2-bit data of the first step.
FIG. 5 shows a specific quantization process of the present embodiment, assuming that the sampled input signal is +201/256×Vref, the whole circuit is reset to obtain the threshold value required for the first step comparison, and the input signal falls between 1/2×Vref and Vref according to the three threshold values-1/2×Vref, 0 and 1/2×Vref generated before the first step quantization, and the output quantization results obtained by the circuit back-end portion SAR logic circuit are 1, 1 and 1, respectively denoted as D 3 <1>、D 2 <1>、D 1 <1>The quantized result D is used to control the first four capacitors of the capacitor array of FIG. 4 i <1>(i＝1、2. 3) or after passing through an inverterThe voltage of the lower electrode plate of the first-step capacitor at the same phase end of the CMP3 is changed from a preset fixed voltage 0010 to 0000, the voltage of the lower electrode plate of the first-step capacitor at the opposite phase end of the CMP3 is changed from a preset fixed voltage 1101 to 1111, the process changes the threshold value used in the first-step comparison, thereby generating the threshold voltage required in the second-step comparison, such as the voltage value of the same phase end of the CMP3 is changed from V CM -V in +64/256×vrefp+192/256×vrefn becomes V CM -V in +16/256×Vrefp+240/256×Vrefn, and the voltage value at the inverting terminal is from V CM -V ip +192/256×vrefp+64/256×vrefn becomes V CM -V ip +240/256×Vrefp+16/256×Vrefn, so that the value compared by CMP3 is V ip -V in Whether 224/256×Vref is greater than 0 or not, the equivalent threshold is 224/256×Vref, and similarly, the equivalent thresholds of CMP2 and CMP1 are 192/256×Vref and 160/256×Vref, thereby generating the threshold required for the second comparison, and the quantization result is 011, recorded as D, can be obtained by the SAR logic circuit as in the process of the first comparison 3 <2>D 2 <2>D 1 <2>The method comprises the steps of carrying out a first treatment on the surface of the As shown in FIG. 4, the quantized result or the quantized result is not connected to the grid electrode of the second-step capacitor lower electrode plate switch of CMP1 and CMP3, the level of the second-step capacitor lower electrode plate connection of the in-phase end of CMP3 is changed from 0010 to 0011, the level of the second-step capacitor lower electrode plate connection of the opposite-phase end is changed from 0010 to 1100, the equivalent threshold value generated by CMP3 is 216/256×Vref, the equivalent threshold values generated by CMP2 and CMP1 are 208/256×Vref and 200/256×Vref respectively, the positions among the three equivalent threshold values of the input signal are observed, the quantized result finally output by the SAR logic circuit is 001 and is marked as D 3 <3>D 2 <3>D 1 <3>Repeating the above operation, and finally obtaining a value approaching to the input signal, the ADC conversion is completed.
As can be seen from the detailed quantization process description above,the 4:4:3:1 capacitance weight distribution can produce the three threshold voltages we need. The preset fixed voltages 1101 and 0010 achieve the threshold voltage scalability, for example, when the capacitance lower plate of the in-phase end of the CMP1 in fig. 4 is connected to the fixed voltage of 1101, the capacitance upper plate level is V CM -V in +192/256 xVrefp+64/256 xVrefn, if the lower plate changes to the level of 1111, the level of the upper plate becomes V CM -V in +240/256×Vrefp+16/256×Vrefp, i.e., the upper plate increases the level of 48/256×Vref. Conversely, when the lower electrode plate of the capacitor at the same phase end of the CMP1 is connected with the level of 0000, the level of the upper electrode plate is changed into V CM -V in The +48/256×Vrefp+208/256×Vrefp, i.e. the upper plate is reduced by 144/256×Vref, and these increase or decrease changes of the fixed voltage just can meet the threshold voltage required for each step of comparison.
The above processes of sampling, threshold generation and conversion are performed under the working time sequence of fig. 6, when CKS is at high level, a signal is input to the lower polar plate of the capacitor array, the circuit starts sampling, then waits for charge transfer to the upper polar plate after a certain time, then starts the reset operation before the first bit comparison, the reset process is to charge the whole DAC array in fig. 1, namely, the high level stages S1, S2, S3 and S4 of clk_charge in fig. 6, after the reset is finished, the first bit comparison is started, after the comparison is finished, the turn-off of the S1 reset signal is controlled by a logic circuit, the circuit is controlled to generate a new threshold value by utilizing the output quantization result, then the comparison output result is obtained sequentially, and the reset signal corresponding to the current comparison is turned off sequentially.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.

Claims (3)

1. The capacitive array and the switching logic circuit of the successive approximation type ADC are characterized by comprising two groups of DAC arrays, three comparators and SAR logic circuits;
the DAC array comprisesThe positive and negative differential input terminals of each unit capacitor are respectively provided with +.>A unit capacitor, n is the number of bits of the ADC; DAC array adopts +.>Step quantization operation, wherein 2 digital code words are quantized in each quantization period, 4 unit capacitors are corresponding to each step quantization process control, the unit capacitors corresponding to each step quantization process control are not repeated, and the capacitor weight of the j-th step quantization corresponding control is->、/>、/>And->；
The DAC array adopts a lower polar plate sampling mode, the lower polar plate of the capacitor is connected with an input signal for sampling before each step of quantization begins, and meanwhile, the upper polar plate of the capacitor is connected with the input end of the comparator and is short-circuited to a common-mode voltage VCM; when sampling is completed, the connection between the upper polar plate and the common-mode voltage VCM is disconnected, the connection between the lower polar plate and an input signal is disconnected, the lower polar plate is connected to a preset fixed voltage, and a threshold resetting operation required by first-step quantization comparison is generated while the charge of the lower polar plate is transferred to the upper polar plate, so that the comparator starts to work to perform first-step 2-bit data quantization;
resetting the lower polar plate of the capacitor array to a preset fixed reference level Vrefp and Vrefn by a reset phase after sampling;
the input end of the SAR logic circuit is connected with the output end of the comparator, the output end of the SAR logic circuit is connected with the lower polar plate switch grid electrode of the DAC array, so that each step of quantization of the DAC array is realized, and the capacitor lower polar plate voltage of the step is controlled by the SAR logic output signal to generate a new threshold value required by the next step of quantization;
the three comparators are a first comparator, a second comparator and a third comparator respectively;
the lower electrode plates of the capacitors at the same phase end of the first comparator are respectively connected to Vrefp, vrefp, vrefn, vrefp, and the lower electrode plates of the capacitors at opposite phase ends of the first comparator are respectively connected to Vrefn, vrefn, vrefp, vrefn; the lower electrode plates of the capacitors at the same phase end of the third comparator are respectively connected to Vrefn, vrefn, vrefp, vrefn, and the lower electrode plates of the capacitors at opposite phase ends of the third comparator are respectively connected to Vrefp, vrefp, vrefn, vrefp; the non-inverting end of the second comparator is connected with the non-inverting end of the first comparator, and the inverting end of the second comparator is connected with the inverting end of the third comparator; wherein vref=vrefp-Vrefn such that the equivalent thresholds of the first comparator, the second comparator, and the third comparator are-1/2×vref, 0, and 1/2×vref, respectively;
the SAR logic circuit judges the position of the Vip-Vin falling between the three thresholds according to the results of the three comparators to obtain 2-bit data in the first step;
the low 4-bit capacitor is connected with Vin in the sampling process, and is connected with Vrefp or Vrefn in the resetting process according to the quantity ratio of 3:1 so as to construct the total capacitor of the integer power of 2 and form the corresponding threshold voltage of the comparator;
three of four capacitors at the lowest position in the DAC at two ends of the comparator are connected with Vrefp, and the other capacitor is connected with Vrefn;
two differential capacitors of the lowest-order capacitors are connected with the same Vrefp or Vrefn, and the other two differential capacitors are connected with a common-mode voltage.
2. The capacitive array and switching logic circuit of a successive approximation ADC of claim 1, whereinThe output quantized result of the SAR logic circuit is connected to the lower polar plate switch grid of the DAC array, and the lower polar plate level of the in-phase end capacitor array of the first comparator and the third comparator is subjected to the output quantized resultControl, the electrode plate level under the capacitor array of the inverting terminal is output quantized result +.>Control continues to quantize the signal to generate new three thresholds.
3. The capacitive array and switching logic circuit of a successive approximation ADC of claim 1, wherein the capacitive array and switching logic circuit comprises 2 M -1 a comparator for constructing an M-bit quantization mode with a high-order capacitance split ratio of (2 M -1) 1; m is a positive integer greater than or equal to 2.
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CN110190854A (en) * 2019-05-13 2019-08-30 东南大学 A kind of realization circuit and method sharing one group of reference voltage towards two-step SAR ADC
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