CN109660259B - Successive approximation type analog-digital converter with constant output common mode voltage and switching method thereof - Google Patents

Successive approximation type analog-digital converter with constant output common mode voltage and switching method thereof Download PDF

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CN109660259B
CN109660259B CN201811531891.8A CN201811531891A CN109660259B CN 109660259 B CN109660259 B CN 109660259B CN 201811531891 A CN201811531891 A CN 201811531891A CN 109660259 B CN109660259 B CN 109660259B
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capacitor
capacitor array
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CN109660259A (en
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王浩
谢文明
陈知新
蔡思静
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Fujian University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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Abstract

The invention discloses a successive approximation type analog-to-digital converter with constant output common mode voltage and a switching method thereof. The invention can greatly reduce the cost and has good economic benefit. The invention can greatly reduce the cost and has good economic benefit.

Description

Successive approximation type analog-digital converter with constant output common mode voltage and switching method thereof
Technical Field
The invention relates to the field of analog-digital mixed signal integrated circuits, in particular to a successive approximation type analog-digital converter with constant output common-mode voltage and a switching method thereof.
Background
The conversion of biomedical signals (such as electrocardiograms, electroencephalograms, etc.) requires a successive approximation analog-to-digital converter with ultra-low power consumption, medium precision and low sampling rate capacitance split architecture. The power consumption of the successive approximation type analog-digital converter with the capacitor splitting structure mainly lies in a digital-analog converter, a digital control circuit and leakage current, wherein the digital-analog converter consists of a comparator and a capacitor array. The comparator adopts a dynamic structure, and the digital control circuit benefits from an advanced CMOS process. In addition, the area and energy consumption of the capacitor array in the successive approximation type analog-to-digital converter with the capacitor splitting structure are large, so that the energy consumption of a capacitor array switch needs to be reduced, the area of the capacitor array is reduced, the manufacturing cost of a chip is reduced, and the economic benefit is improved.
Disclosure of Invention
The invention aims to provide a successive approximation type analog-to-digital converter with constant output common-mode voltage and a switching method thereof, and compared with a 10-bit traditional structure, the area of a capacitor is reduced by 87.5%, and the power consumption generated in the switching process is reduced by 98% under the same precision.
The technical scheme adopted by the invention is as follows:
the successive approximation type analog-to-digital converter comprises a capacitor array, a comparator and a control logic circuit which are connected in sequence, wherein the capacitor array comprises a forward capacitor array of a capacitor splitting structure connected to the positive input end of the comparator and a reverse capacitor array of the capacitor splitting structure connected to the negative input end of the comparator, the output end of the comparator is connected with the input end of the control logic circuit, the forward capacitor array and the reverse capacitor array are of capacitor splitting structures and respectively comprise an MSB part and an LSB part, and the MSB part and the LSB part are completely consistent and are binary weighted capacitor arrays;
the MSB part and the LSB part comprise N-3 high-order capacitors, an LSB capacitor and a dummy capacitor, the capacitance values of the N-3 high-order capacitors are sequentially weighted down, wherein the capacitance value of the high-order capacitor with the highest weight is 2 N-4 C, N is the precision of the analog-to-digital converter and N is an integer greater than 4
Wherein the upper electrode plate of the forward capacitor array passes through a sampling switch S P And positive input terminal voltage V INP Connected with the lower polar plate through a selection switch and V REF 、V CM Is connected with gnd; sampling switch S for upper pole plate of reverse capacitor array N And a negative input terminal voltage V INN Connected with the lower polar plate via a selection switch and V REF 、V CM Connected to gnd, V REF Is a reference voltage, V CM Is the common mode voltage.
Further, the LSB capacitance and dummy capacitance of the analog-to-digital converter are both unit capacitances, and the analog-to-digital converter comprises 2 in total N-1 Unit capacitance, N is the precision of the analog-to-digital converter.
The invention further discloses a switching method of the successive approximation type analog-digital converter for constant output common mode voltage, which adopts the successive approximation type analog-digital converter for constant output common mode voltage and comprises the following steps;
step 1, sampling stage: positive input voltage V INP By means of a sampling switch S P Is conductively connected to the upper plate of the forward capacitor array, all the lower plates of the capacitor array of the MSB part of the forward capacitor array are connected to gnd, all the lower plates of the capacitor array of the LSB part are connected to V REF (ii) a Negative input voltage V INN By means of a sampling switch S N Conductively connected to an array of inverse capacitorsUpper plate, all lower plates of capacitor array of MSB part in reverse capacitor array are connected to gnd, and all lower plates of capacitor array of LSB part are connected to V REF ；
Step 2, constructing digital codes D for each comparison M If M represents the current comparison serial number, then the specific Mth digit code, D M The calculation formula is as follows:
when V is INP -V INN Is greater than
Figure BDA0001905867230000021
When D is M ＝1；
When M is more than or equal to 2 and
Figure BDA0001905867230000022
where m is such that | m | < 2 M-1 All of the integers of (1);
then
Figure BDA0001905867230000023
When V is INP -V INN Is less than or equal to
Figure BDA0001905867230000024
When D is M ＝0；
And 3, carrying out first comparison: sampling switch S P 、S N Disconnecting, starting to compare for the first time to obtain a digital code D 1 (ii) a When V is INP Greater than V INN Time, digital code D 1 1 is ═ 1; when V is INP V is less than or equal to INN Time, digital code D 1 ＝0；
When D is present 1 When the voltage of the connection position of the lower electrode plates of the capacitors of the forward capacitor array and the capacitors of the reverse capacitor array is equal to the common-mode voltage V of the input signal, the voltage of the connection position of the lower electrode plates of the capacitors of the forward capacitor array and the capacitors of the reverse capacitor array is equal to 1 CM I.e. when D 1 The lower plate of all capacitors of the LSB part of the forward capacitor array is formed by V when the value is 1 REF Switch to V CM ComparatorPositive input terminal voltage reduced by V REF (ii)/4; the lower plate of all capacitors of the MSB part of the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator increases by V REF (ii)/4; otherwise D 1 0, the lower plate of all capacitors of the MSB part in the forward capacitor array is switched to V by gnd CM The positive input voltage of the comparator increases by V REF (ii)/4; the lower polar plate of all LSB capacitors in the reverse capacitor array is formed by V REF Switch to V CM The comparator negative input terminal voltage is reduced by V REF /4；
And 4, sequentially carrying out comparison from the second time to the N-2 times, wherein N is the precision of the analog-to-digital converter:
each time of comparison is firstly passed through D M Calculating the digital code D of the comparison by a calculation formula M (ii) a Determining the weight capacitance corresponding to the second comparison, wherein the weight capacitance corresponding to the second comparison is the high-order capacitance with the maximum weight of the forward capacitor array and the reverse capacitor array, the weight of the capacitance corresponding to the second comparison is sequentially reduced along with the increase of the comparison times, and the weight capacitance corresponding to the N-2 th comparison is the LSB capacitance of the forward capacitor array and the reverse capacitor array;
the corresponding converter switch switching relationship for this comparison is as follows:
when V is INP -V INN Is greater than
Figure BDA0001905867230000025
When, D M 1 is ═ 1; the lower plate of the upper capacitor weighted by V corresponding to the comparison in the LSB part of the forward capacitor array CM Switching to gnd, and changing the lower plate connection of the high-order capacitor with the weight corresponding to the comparison in the MSB part of the reverse capacitor array from V CM Switch to V REF ；
When in use
Figure BDA0001905867230000031
m is defined as | m | < 2 M-1 All of the integers of (1);
then
Figure BDA0001905867230000032
The corresponding switches are switched as follows:
when D is present 1 1 and D M 1, the lower plate of the capacitor corresponding to the weight of the comparison in the LSB part of the forward capacitor array is formed by V CM Switching to gnd, the lower plate connection of the capacitor with the weight corresponding to the comparison in MSB part of the reverse capacitor array changes from V CM Switch to V REF ；
When D is present 1 1 and D M When the weight of the capacitor lower plate corresponding to the comparison in the MSB part of the forward capacitor array is switched from gnd to V CM The connection of the lower electrode plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is changed from V REF Switch to V CM ；
When D is present 1 0 and D M 1, the lower plate of the capacitor corresponding to the weight of the comparison in the LSB part of the forward capacitor array is formed by V REF Switch to V CM The lower plate of the capacitor corresponding to the weight of the comparison in the MSB part of the reverse capacitor array is switched from gnd to V CM ；
When D is present 1 Not greater than 0 and D M 0, the lower plate of the capacitor corresponding to the weight of the comparison in the MSB part of the forward capacitor array is formed by V CM Switch to V REF The lower plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is V REF Switch to V CM ；
When V is INP -V INN Is less than or equal to
Figure BDA0001905867230000033
When D is M 0; the lower plate of the capacitor with the weight corresponding to the comparison in the MSB part of the forward capacitor array is divided by V CM Switch to V REF The lower plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is V CM Switching to gnd;
step 5, carrying out the comparison for the N-1 th time and adopting D M The calculation formula obtains the digital code D of the N-1 th comparison N-1 A value of (d); thenThe switching relation of the switch of the converter in the N-1 th comparison is as follows:
if D is 1 1 and D N-1 1, the lower plate of dummy capacitor in LSB part of forward capacitor array is formed by V CM Switching to gnd reduces the positive input terminal voltage of the comparator by V REF /2 N-1 The connection of all capacitor lower electrode plates in the reverse capacitor array is kept unchanged;
if D is 1 1 and D N-1 0, the lower plate of dummy capacitor in LSB part of forward capacitor array is formed by V REF Switch to V CM The positive input terminal voltage of the comparator is reduced by V REF /2 N-1 The connection of all capacitor lower electrode plates in the reverse capacitor array is kept unchanged;
if D is 1 0 and D N-1 1, the lower plate of dummy capacitor in LSB part of the reverse capacitor array is formed by V REF Switch to V CM The negative input voltage of the comparator is reduced by V REF /2 N-1 All capacitor lower polar plate connections in the forward capacitor array are kept unchanged;
if D is 1 0 and D N-1 0, the lower plate of dummy capacitor in LSB part of the reverse capacitor array is formed by V CM Switching to gnd reduces the negative input voltage of the comparator by V REF /2 N-1 The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged;
step 6, carrying out the Nth comparison by adopting D M The calculation formula calculates to obtain the digital code D of the Nth comparison N And outputs, ends the conversion.
By adopting the technical scheme, the upper polar plate is adopted for sampling, the capacitor array at the positive and negative input ends of the comparator adopts a capacitor splitting structure, and the negative switch energy is introduced by presetting a reference voltage sequence, so that the design complexity and the overall power consumption of the digital logic circuit are reduced. The invention can greatly reduce the cost and has good economic benefit.
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The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a block diagram of an N-bit successive approximation register analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sampling operation of a 4-bit successive approximation type analog-to-digital converter according to an embodiment of the present invention;
FIG. 3 shows the switching operation principle (D) of the 4-bit successive approximation type ADC according to the embodiment of the present invention 1 D 2 ＝11)；
FIG. 4 shows an embodiment of the present invention, in which the switching operation principle (D) of the 4-bit successive approximation type ADC 1 D 2 ＝10)；
FIG. 5 shows the switching operation principle (D) of the 4-bit successive approximation type analog-to-digital converter according to an embodiment of the present invention 1 D 2 ＝01)；
FIG. 6 shows the switching operation principle of the 4-bit successive approximation type ADC according to the embodiment of the present invention (D) 1 D 2 ＝00)；
Fig. 7 is an MATLAB simulation result of the switch power consumption varying with the output code in the conversion process of the 10-bit successive approximation type analog-to-digital converter according to the embodiment of the present invention;
FIG. 8 is a DAC voltage variation during the conversion process of the 10-bit successive approximation type analog-to-digital converter according to the embodiment of the present invention;
FIG. 9 shows the DAC voltage variation during the conversion process of the 10-bit successive approximation type analog-to-digital converter according to the embodiment of the present invention.
Detailed Description
As shown in fig. 1, an N-bit successive approximation type analog-to-digital converter is taken as an example and includes a sampling switch, a comparator, an SAR control logic circuit, and a capacitor array. The capacitor array comprises two parts: the capacitor array connected with the positive input end of the comparator is called a forward capacitor array, and the MSB part and the LSB part are formed by binary weighted capacitor arrays and are completely consistent; the capacitor array connected with the negative input end of the comparator is called a reverse capacitor array and is completely consistent with the forward capacitor array; for an N-bit precision analog-to-digital converter, the integral capacitor array comprises 2 N-1 Unit capacitance. As shown in fig. 1, when N is 4, the maximum capacitance is C.
A sampling stage:
as shown in fig. 2, the sampling switch S P 、S N Conduction ofInput signal V INP 、V INN Respectively sampling the upper plates of the forward capacitor array and the reverse capacitor array, simultaneously connecting all the lower plates of the capacitors in the MSB part of the forward capacitor array to gnd, and connecting all the lower plates of the capacitors in the LSB part to V REF ，V REF Is a reference voltage, V CM Is a common mode voltage; the connection mode of the lower electrode plate of the capacitor in the reverse capacitor array is the same as that of the lower electrode plate of the capacitor in the forward capacitor array.
And a comparison stage:
after sampling is finished, a sampling switch S P 、S N And when the capacitor is opened, the upper electrode plate of the capacitor is disconnected with the input signal, and the consumed switch energy in the process is 0.
As shown in fig. 3, when (V) INP -V INN ) Greater than V REF At/2 time, i.e. D 1 D 2 11; the connection of the lower electrode plate of the corresponding capacitor (maximum weight capacitor) in the LSB part of the forward capacitor array is changed from V CM Switching to gnd reduces the positive input terminal voltage of the comparator by V REF /8, the bottom plate connection of the corresponding capacitor (maximum weight capacitor) in the MSB part of the reverse capacitor array changes from V CM Switch to V REF The negative input voltage of the comparator is increased by V REF 8; if D is 1 D 2 D 3 When the letter is 111, (V) INP -V INN ) Greater than (3/4) V REF If the connection of the lower plate of the corresponding capacitor (dummy capacitor) in the LSB part of the forward capacitor array changes, then V is changed CM Switching to gnd reduces the positive input terminal voltage of the comparator by V REF 8, connecting all lower electrode plates of capacitors in the reverse capacitor array to be kept unchanged; if D is 1 D 2 D 3 110, (V) INP -V INN ) Greater than (1/2) V REF And is not more than (3/4) V REF If the capacitance of the corresponding capacitor (dummy capacitor) in the LSB part of the negative capacitance array changes from V REF Switch to V CM The comparator negative input terminal voltage is reduced by V REF The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged; d is obtained by the fourth comparison 4 ；
As shown in fig. 4, when (V) INP -V INN ) Greater than 0 and less than or equal to V REF At/2, i.e. D 1 D 2 10; the lower plate connection of the corresponding capacitor (maximum weight capacitor) in the MSB part of the forward capacitor array is changed, and the Gnd is switched to V CM The positive input voltage of the comparator is increased by V REF /8, the corresponding capacitance (maximum weighted capacitance) lower plate connection in the MSB part of the reverse capacitance array changes from V REF Switch to V CM The voltage at the negative input terminal of the comparator is reduced by V REF 8; if D is 1 D 2 D 3 101, then (V) INP - V INN ) Greater than (1/4) V REF V is less than or equal to REF When the capacitance is V2, the connection of the lower electrode plate of the corresponding capacitor (dummy capacitor) in the LSB part in the forward capacitor array changes CM Switching to gnd reduces the positive input terminal voltage of the comparator by V REF 8, connecting all lower electrode plates of capacitors in the reverse capacitor array to be kept unchanged; if D is 1 D 2 D 3 When the value is 100, (V) INP -V INN ) Greater than (1/4) V REF And less than or equal to 0, the connection of the lower electrode plate of the corresponding capacitor (dummy capacitor) in the LSB part of the negative capacitor array changes from V REF Switch to V CM The comparator negative input terminal voltage is reduced by V REF The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged; obtaining D through the fourth comparison 4 ；
As shown in fig. 5, when (V) INP -V INN ) Greater than-V REF When the ratio is 0 or less, i.e. D 1 D 2 01; the connection of the lower electrode plate of the corresponding capacitor (maximum weight capacitor) in the LSB part of the forward capacitor array is changed from V REF Switch to V CM The voltage at the positive input terminal of the comparator is reduced by V REF 8, the connection of the lower plate of the corresponding capacitor (maximum weight capacitor) in the MSB part in the reverse capacitor array changes, and the GND is switched to the V CM The negative input voltage of the comparator is increased by V REF 8; if D is 1 D 2 D 3 011 then (V) INP -V INN ) Greater than (-1/4) V REF When the capacitance is less than or equal to 0, the forward capacitanceThe connection of the lower electrode plate of the corresponding capacitor (dummy capacitor) in the LSB part of the array changes from V REF Switch to V CM The positive input terminal voltage of the comparator is reduced by V REF 8, connecting all lower electrode plates of capacitors in the reverse capacitor array to be kept unchanged; if D is 1 D 2 D 3 010, then (V) INP -V INN ) Greater than (-1/2) V REF And is less than or equal to (-1/4) V REF If the capacitance of the negative capacitor array is changed, the connection of the lower electrode plate of the corresponding capacitor (dummy capacitor) in the LSB part is changed from V CM Switching to gnd, the negative input terminal voltage of the comparator decreases by V REF The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged; obtaining D through the fourth comparison 4 ；
As shown in fig. 6, when (V) INP -V INN ) Less than or equal to (-1/2) V REF When is at D 1 D 2 00; the connection of the lower plate of the corresponding capacitor (maximum weight capacitor) in the MSB part of the forward capacitor array is changed from V CM Switch to V REF The positive input voltage of the comparator is increased by V REF /8, the bottom plate connection of the corresponding capacitor (maximum weight capacitor) in the MSB part of the reverse capacitor array changes from V CM Switching to gnd reduces the negative input voltage of the comparator by V REF 8; if D is 1 D 2 D 3 When the root is 001, (V) INP -V INN ) Greater than (-3/4) V REF Less than or equal to (-1/2) V REF In the meantime, the connection of the lower plate of the corresponding capacitor (dummy capacitor) in the LSB part of the forward capacitor array changes from V REF Switch to V CM The positive input terminal voltage of the comparator is reduced by V REF 8, connecting all lower electrode plates of capacitors in the reverse capacitor array to be kept unchanged; if D is 1 D 2 D 3 000, then (V) INP -V INN ) Less than or equal to (-3/4) V REF If the capacitance of the negative capacitor array is changed, the connection of the lower electrode plate of the corresponding capacitor (dummy capacitor) in the LSB part is changed from V CM Switching to gnd, the negative input terminal voltage of the comparator decreases by V REF The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged; obtaining D through the fourth comparison 4 ；
As shown in fig. 7, taking a 10-bit successive approximation analog-to-digital converter as an example, a MATLAB simulation result graph of the variation of the switching power consumption with the digital output code during the conversion process is shown. The average energy consumption of the switching algorithm provided by the invention is-10.67 CV REF 2 Compared with the traditional structure, 100.78% is saved; if the negative energy (physically absent, meaning that the capacitor discharges and returns energy to the reference voltage source) is taken into account and this part of the energy is calculated as 0, the average energy consumption is 21.33CV REF 2 Compared with the traditional structure, the structure saves 98.44 percent and has good economic benefit.
As shown in fig. 8 and 9, a 10-bit successive approximation analog-to-digital converter is taken as an example, and the DAC voltage and the common mode voltage change during the conversion process. The common mode voltage is constant, V, for the rest of the bit conversion periods except the last bit conversion period CM 。
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and the modifications and improvements should be construed as the scope of the present invention.

Claims (2)

1. A switch method of a successive approximation type analog-digital converter for outputting constant common mode voltage comprises a capacitor array, a comparator and a control logic circuit which are connected in sequence, wherein the capacitor array comprises a forward capacitor array of a capacitor splitting structure connected to the positive input end of the comparator and a reverse capacitor array of the capacitor splitting structure connected to the negative input end of the comparator, the output end of the comparator is connected with the input end of the control logic circuit, the forward capacitor array and the reverse capacitor array both adopt capacitor splitting structures and respectively comprise an MSB part and an LSB part, and the MSB part and the LSB part are completely consistent and are binary weighted capacitor arrays; the MSB part and the LSB part comprise N-3 high-order capacitors, an LSB capacitor and a dummy capacitor, the capacitance values of the N-3 high-order capacitors are sequentially weighted down, wherein the capacitance value of the high-order capacitor with the highest weight is 2 N-4 C, N is the precision of the analog-to-digital converter and N is an integer greater than 4;
wherein the upper electrode plate of the forward capacitor array passes through a sampling switch S P And positive input terminal voltage V INP Connected with the lower polar plate through a selection switch and V REF 、V CM Is connected with gnd; sampling switch S for upper pole plate of reverse capacitor array N And a negative input terminal voltage V INN Connected with the lower polar plate through a selection switch and V REF 、V CM Connected to gnd, V REF As reference voltage, V CM Is a common mode voltage; the method is characterized in that: the switching method comprises the following steps;
step 1, sampling stage: positive input voltage V INP By means of a sampling switch S P Is conductively connected to the upper plate of the forward capacitor array, all the lower plates of the capacitor array of the MSB part of the forward capacitor array are connected to gnd, all the lower plates of the capacitor array of the LSB part are connected to V REF (ii) a Negative input voltage V INN By means of a sampling switch S N Is conductively connected to the upper plate of the reverse capacitor array, all the lower plates of the capacitor array of the MSB part of the reverse capacitor array are connected to gnd, all the lower plates of the capacitor array of the LSB part are connected to V REF ；
Step 2, constructing a digital code D for each comparison M M represents the current comparison serial number, and then the specific mth digital code, D M The calculation formula is as follows:
when V is INP -V INN Is greater than
Figure FDA0003782063630000011
When D is M ＝1；
When M is not less than 2 and
Figure FDA0003782063630000012
where m is such that | m | < 2 M-1 All of the integers of (1);
then the
Figure FDA0003782063630000013
When V is INP -V INN Is less than or equal to
Figure FDA0003782063630000014
When, D M ＝0；
Step 3, carrying out first comparison: sampling switch S P 、S N Disconnecting, starting to compare for the first time to obtain a digital code D 1 (ii) a When V is INP Greater than V INN Time, digital code D 1 1 is ═ 1; when V is INP V is less than or equal to INN Time, digital code D 1 ＝0；
When D is 1 When the voltage of the connection position of the lower electrode plates of the capacitors of the forward capacitor array and the capacitors of the reverse capacitor array is equal to the common-mode voltage V of the input signal, the voltage of the connection position of the lower electrode plates of the capacitors of the forward capacitor array and the capacitors of the reverse capacitor array is equal to 1 CM And V is CM ＝V REF 2, i.e. when D 1 1, the lower plate of all capacitors of the LSB part of the forward capacitor array is formed by V REF Switch to V CM The positive input terminal voltage of the comparator is reduced by V REF (ii)/4; the lower plate of all capacitors of the MSB part of the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator increases by V REF (ii)/4; otherwise D 1 0, the lower plate of all capacitors of the MSB part in the forward capacitor array is switched to V by gnd CM The positive input voltage of the comparator increases by V REF 4,/4; the lower polar plate of all LSB capacitors in the reverse capacitor array is formed by V REF Switch to V CM The comparator negative input terminal voltage is reduced by V REF /4；
And 4, sequentially carrying out comparison from the second time to the N-2 times, wherein N is the precision of the analog-to-digital converter:
each comparison is first passed through D M Calculating the digital code D of the comparison by a calculation formula M (ii) a Determining the weight capacitance corresponding to the second comparison, wherein the weight capacitance corresponding to the second comparison is the high-order capacitance with the maximum weight of the forward capacitance array and the reverse capacitance array, and the weights of the capacitances corresponding to the second comparison are sequentially increased along with the increase of the comparison timesReducing that the corresponding weight capacitor is the LSB capacitor of the forward capacitor array and the reverse capacitor array in the N-2 th comparison;
the corresponding converter switch switching relationship for this comparison is as follows:
when V is INP -V INN Is greater than
Figure FDA0003782063630000021
When, D M 1; the lower plate of the high-order capacitor with the weight corresponding to the comparison in the LSB part of the forward capacitor array is divided by V CM When the capacitor is switched to gnd, the lower plate connection of the high-order capacitor of the MSB part in the reverse capacitor array, which corresponds to the weight of the comparison, is changed from V CM Switch to V REF ；
When the temperature is higher than the set temperature
Figure FDA0003782063630000022
m is defined as M-1 All of the integers of (1);
then
Figure FDA0003782063630000023
The corresponding switches are switched as follows:
when D is present 1 1 and D M 1, the lower plate of the capacitor with the weight corresponding to the comparison in the LSB part of the forward capacitor array is set by V CM Switching to gnd, the capacitance bottom plate connection of MSB part in reverse capacitance array corresponding to the weight of the comparison is changed from V CM Switch to V REF ；
When D is present 1 1 and D M When the weight of the capacitor lower plate corresponding to the comparison in the MSB part of the forward capacitor array is switched from gnd to V CM The connection of the lower electrode plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is changed from V REF Switch to V CM ；
When D is present 1 0 and D M 1, the lower plate of the capacitor corresponding to the weight of the comparison in the LSB part of the forward capacitor array is formed by V REF Switch to V CM Reverse electricityThe lower plate of the capacitor corresponding to the weight of the comparison in the MSB part of the capacitor array is switched from gnd to V CM ；
When D is present 1 0 and D M When the value is equal to 0, the lower electrode plate of the capacitor with the weight corresponding to the comparison in the MSB part in the forward capacitor array is V CM Switch to V REF The lower plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is V REF Switch to V CM (ii) a When V is INP -V INN Is less than or equal to
Figure FDA0003782063630000024
When D is M 0; the lower plate of the capacitor with the weight corresponding to the comparison in the MSB part of the forward capacitor array is divided by V CM Switch to V REF The lower plate of the capacitor with the weight corresponding to the comparison in the LSB part of the reverse capacitor array is V CM Switching to gnd;
step 5, carrying out the comparison for the N-1 th time and adopting D M The calculation formula obtains the digital code D of the N-1 th comparison N-1 A value of (d); the switching relationship of the converter switch in the N-1 th comparison is as follows:
if D is 1 1 and D N-1 1, the lower plate of dummy capacitor in LSB part of forward capacitor array is formed by V CM Switching to gnd reduces the positive input terminal voltage of the comparator by V REF /2 N-1 The connection of all capacitor lower electrode plates in the reverse capacitor array is kept unchanged;
if D is 1 1 and D N-1 0, the lower plate of dummy capacitor in LSB part of forward capacitor array is formed by V REF Switch to V CM The positive input terminal voltage of the comparator is reduced by V REF /2 N-1 The connection of all capacitor lower electrode plates in the reverse capacitor array is kept unchanged;
if D is 1 0 and D N-1 1, the lower plate of dummy capacitor in LSB part of the reverse capacitor array is formed by V REF Switch to V CM The negative input voltage of the comparator is reduced by V REF /2 N-1 All capacitor lower polar plate connections in the forward capacitor array are kept unchanged;
if D is 1 0 and D N-1 0, the lower plate of dummy capacitor in LSB part of the reverse capacitor array is formed by V CM Switching to gnd reduces the negative input voltage of the comparator by V REF /2 N-1 The connection of all capacitor lower electrode plates in the forward capacitor array is kept unchanged;
step 6, carrying out Nth comparison by adopting D M The calculation formula calculates to obtain the digital code D of the Nth comparison N And output.
2. The method of claim 1, wherein the step of switching the successive approximation analog-to-digital converter with constant output common mode voltage comprises: LSB capacitance and dummy capacitance of the analog-to-digital converter are both unit capacitance, and the analog-to-digital converter comprises 2 in total N-1 Unit capacitance, N is the precision of the analog-to-digital converter.
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