CN106972860B - Successive approximation type analog-to-digital converter and switching method thereof - Google Patents

Successive approximation type analog-to-digital converter and switching method thereof Download PDF

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CN106972860B
CN106972860B CN201710295297.2A CN201710295297A CN106972860B CN 106972860 B CN106972860 B CN 106972860B CN 201710295297 A CN201710295297 A CN 201710295297A CN 106972860 B CN106972860 B CN 106972860B
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capacitor array
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CN106972860A (en
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王浩
谢文明
陈知新
蔡思静
郑少烽
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Fujian University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention provides a successive methodAn approximation type analog-to-digital converter comprises a positive input voltage, a negative input voltage, a comparator and a sampling switch S P Sampling switch S N The output end of the comparator is connected to the successive approximation register control logic circuit, and the positive input end of the comparator passes through the sampling switch S P Connected to a positive input voltage, the negative input of the comparator being connected to the positive input voltage via a sampling switch S N Is connected to a negative input voltage; the invention also provides a switching method of the successive approximation type analog-to-digital converter; the energy consumption of the capacitor array switch is reduced, the area of the capacitor array is reduced, the manufacturing cost of the chip is reduced, and the economic benefit is improved.

Description

Successive approximation type analog-to-digital converter and switching method thereof
Technical Field
The invention relates to a successive approximation type analog-to-digital converter and a switching method thereof.
Background
The successive approximation type analog-to-digital converter has the advantages of simple structure, low power consumption and small area, and is widely applied to the fields of wireless sensors, implanted medical devices and the like with high requirements on power consumption and area. The capacitor array occupies a large area and consumes a large amount of energy in the successive approximation type analog-to-digital converter.
Disclosure of Invention
The invention aims to provide a successive approximation type analog-to-digital converter and a switching method thereof, which can reduce the energy consumption of a capacitor array switch, reduce the area of the capacitor array, reduce the manufacturing cost of a chip and improve the economic benefit.
One of the present invention is realized by: a successive approximation type analog-to-digital converter comprises a positive input voltage, a negative input voltage, a comparator and a sampling switch S P Sampling switch S N The output end of the comparator is connected to the successive approximation register control logic circuit, and the positive input end of the comparator passes through the sampling switch S P Is connected to a forward input voltage, thereforThe negative input end of the comparator passes through a sampling switch S N Is connected to a negative input voltage;
the capacitor array comprises a positive capacitor array and a negative capacitor array, the positive capacitor array comprises two first capacitors, an upper polar plate of each first capacitor is connected to a positive input end of the comparator, and a lower polar plate of each first capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd; the negative capacitance array comprises an MSB capacitance array and an LSB capacitance array, the MSB capacitance array is composed of binary weighted capacitances, the MSB capacitance array comprises N-2 second capacitances, the LSB capacitance array is composed of binary weighted capacitances, the LSB capacitance array comprises N-2 second capacitances, N is the precision of a successive approximation type analog-to-digital converter, and the maximum value of the capacitance is 2 N-4 A unit capacitance; the upper polar plate of each second capacitor is connected to the negative input end of the comparator, and the lower polar plate of each second capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd.
Further, the V REF ＝2V CM ，gnd＝0V。
Further, the value of the first capacitor is C, and C is a unit capacitor.
Further, the maximum value of the second capacitance is 2 N-4 And C is unit capacitance.
The second invention is realized by the following steps: a method of switching a successive approximation analog to digital converter, the method providing a successive approximation analog to digital converter as claimed in any one of claims 1 to 4; the method specifically comprises the following steps:
a sampling stage:
positive input voltage V INP By means of a sampling switch S P Is connected to the upper plate of the forward capacitor array, the lower plate of one of the two unit capacitors in the forward capacitor array is connected to gnd, and the other unit capacitor is connected to V CM (ii) a Negative input voltage V INN By means of a sampling switch S N Is conductively connected to the upper plate of the reverse capacitor array, reverse electricityAll lower plates in the MSB capacitor array in the capacitor array are connected to gnd, and all lower plates in the LSB capacitor array are connected to V CM ；
And a comparison stage:
first, a sampling switch S P 、S N Disconnecting, and starting first comparison to obtain MSB; if V INP Greater than V INN Then the voltage of the lower plate of each capacitor in the reverse capacitor array is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; conversely, the lower plate of each capacitor in the forward capacitor array is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
then starting a second comparison; if V INP Greater than (V) INN +V REF /2), then the forward capacitor array is connected to V CM The lower plate of the unit capacitor is switched to gnd, and the positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +V REF /2) and greater than 0, the lower plate of the unit capacitor connected to gnd in the forward direction capacitor array is switched to V CM The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Greater than (V) INN -V REF /2) and 0 or less, the connection to V in the forward direction capacitance array REF Lower plate of the unit capacitor is switched to V CM The positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN -V REF /2), then the forward capacitor array is connected to V CM Lower plate of the unit capacitor is switched to V REF The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
a third comparison is then made; if V INP Greater than (V) INN +(3/4)V REF ) And the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is V CM Switch to V REF Voltage increase at negative input of comparatorIs additionally provided with V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +(3/4)V REF ) And is greater than (V) INN +(1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V REF Switch to V CM The negative input voltage of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN +(1/4)V REF ) And is less than or equal to (V) INN +(1/2)V REF ) And the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is V CM Switch to V REF The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +(1/4)V REF ) And is greater than V INN And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is changed from V REF Switch to V CM The voltage at the negative input terminal of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN -(1/4)V REF ) And V is INP V is less than or equal to INN Then the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN -(1/4)V REF ) And is greater than (V) INN -(1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V CM Switched to gnd, the negative input voltage of the comparator decreases by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN -(3/4)V REF ) And is not more than (V) INN -(1/2)V REF ) Then the corresponding capacitor bottom plate in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to(V INN -(3/4)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V CM Switching to gnd reduces the negative input voltage of the comparator by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged;
and sequentially comparing step by step until LSB is obtained, and completing analog-to-digital conversion.
The invention has the advantages that: according to the successive approximation type analog-to-digital converter and the switching method thereof, the energy consumption of a capacitor array switch is reduced, the area of the capacitor array is reduced, the manufacturing cost of a chip is reduced, and the economic benefit is improved; under the same precision, compared with a 10-bit traditional structure, the area of the capacitor is reduced by 87.4%, and the power consumption generated in the switching process is reduced by 99.23%.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a diagram of a four-bit successive approximation type analog-to-digital converter;
FIG. 2 is a schematic diagram of the first switching operation of a four-bit successive approximation type analog-to-digital converter;
FIG. 3 is a diagram of the second switching operation of a four-bit successive approximation type analog-to-digital converter;
FIG. 4 is a schematic diagram of a third switching operation of a four-bit successive approximation type analog-to-digital converter;
FIG. 5 is a diagram of a fourth switching operation of a four-bit successive approximation type ADC;
fig. 6 is an MATLAB simulation result of the switch power consumption varying with the output code in the conversion process of the ten-bit successive approximation type analog-to-digital converter.
Detailed Description
The successive approximation type analog-to-digital converter comprises a positive input voltage, a negative input voltage, a comparator and a sampling switch S P Sampling switch S N The output end of the comparator is connected to the successive approximation register control logic circuit, and the positive input end of the comparator passes through a sampling switch S P Connected to a forward input voltageThe negative input end of the comparator passes through a sampling switch S N Is connected to a negative input voltage;
the capacitor array comprises a positive capacitor array and a negative capacitor array, the positive capacitor array comprises two first capacitors, an upper polar plate of each first capacitor is connected to a positive input end of the comparator, and a lower polar plate of each first capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd; the negative capacitance array comprises an MSB capacitance array and an LSB capacitance array, the MSB capacitance array is composed of binary weighted capacitances, the MSB capacitance array comprises N-2 second capacitances, the LSB capacitance array is composed of binary weighted capacitances, the LSB capacitance array comprises N-2 second capacitances, N is the precision of a successive approximation type analog-to-digital converter, and the maximum value of the capacitance is 2 N-4 A unit capacitance; the upper polar plate of each second capacitor is connected to the negative input end of a comparator, and the lower polar plate of each second capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd.
The V is REF ＝2V CM Gnd =0V, the first capacitance has a value C, C is a unit capacitance, and the second capacitance has a maximum value of 2 N-4 C, the C is unit capacitance.
The invention relates to a switching method of a successive approximation type analog-to-digital converter, which needs to provide the successive approximation type analog-to-digital converter; the method specifically comprises the following steps:
a sampling stage:
positive input voltage V INP By means of a sampling switch S P Is connected to the upper plate of the forward capacitor array, the lower plate of one of the two unit capacitors in the forward capacitor array is connected to gnd, and the other unit capacitor is connected to V CM (ii) a Negative input voltage V INN By means of a sampling switch S N Is conductively connected to the upper plate of the reverse capacitor array, all the lower plates of the MSB capacitor array in the reverse capacitor array are connected to gnd, and all the lower plates of the LSB capacitor array are connected to V CM ；
And a comparison stage:
first, a sampling switch S P 、S N Disconnecting, and starting first comparison to obtain MSB; if V INP Greater than V INN Then the voltage of the lower plate of each capacitor in the reverse capacitor array is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; conversely, the lower plate of each capacitor in the forward capacitor array is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
then starting a second comparison; if V INP Greater than (V) INN +V REF /2), then the forward capacitor array is connected to V CM The lower plate of the unit capacitor is switched to gnd, and the positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +V REF /2) and greater than 0, the lower plate of the unit capacitor connected to gnd in the forward capacitor array is switched to V CM The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Greater than (V) INN -V REF /2) and 0 or less, the connection to V in the forward direction capacitance array REF Lower plate of the unit capacitor is switched to V CM The positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN -V REF /2), then the forward capacitor array is connected to V CM Lower plate of the unit capacitor is switched to V REF The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
a third comparison is then made; if V INP Greater than (V) INN +(3/4)V REF ) Then the corresponding capacitance in the MSB capacitor array in the inverted capacitor array (maximum capacitance, i.e., 2) N-4 C) Lower polar plate V CM Switch to V REF The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +(3/4)V REF ) And is greater than (V) INN +(1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V REF Switch to V CM The negative input voltage of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN +(1/4)V REF ) And is less than or equal to (V) INN +(1/2)V REF ) Then the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is driven from V CM Switch to V REF The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +(1/4)V REF ) And is greater than V INN And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V REF Switch to V CM The voltage at the negative input terminal of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN -(1/4)V REF ) And V is INP Is less than or equal to V INN Then the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN -(1/4)V REF ) And is greater than (V) INN -(1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V CM Switching to gnd reduces the negative input voltage of the comparator by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN -(3/4)V REF ) And is less than or equal to (V) INN -(1/2)V REF ) Then the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN -(3/4)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V CM Switch tognd, the negative input voltage of the comparator has been reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged;
and sequentially comparing step by step until LSB is obtained, and completing analog-to-digital conversion.
The following detailed description is made with reference to the accompanying drawings and examples.
As shown in fig. 1, a 4-bit small-area low-power consumption successive approximation type analog-to-digital converter is taken as an example and includes a comparator, a control logic circuit and a capacitor array. The capacitor array comprises a forward capacitor array connected to the positive input end of the comparator and a reverse capacitor array of a split structure connected to the negative input end of the comparator. The forward capacitance network comprises only two unit capacitances and does not vary with the accuracy of the analog-to-digital converter. The reverse capacitor array adopts a split structure and consists of an MSB capacitor array and an LSB capacitor array, and the MSB capacitor array and the LSB capacitor array are completely consistent and are binary weights. The maximum capacitance increases exponentially with increasing accuracy of the analog-to-digital converter and is 2 N-4 C. As shown in fig. 1, when N =4, the maximum capacitance is C, and C is the unit capacitance.
When N =5, the MSB capacitor array includes three capacitors, two of which have a value of C and one of which has a value of 2C; the LSB capacitor array comprises three capacitors, wherein two capacitors have the value of C, and one capacitor has the value of 2C;
when N =6, the MSB capacitor array includes four capacitors, where two capacitors have a value of C, one capacitor has a value of 2C, and one capacitor has a value of 4C; the LSB capacitor array comprises four capacitors, wherein two capacitors have the value of C, one capacitor has the value of 2C, and one capacitor has the value of 4C;
and so on.
Sampling phase
As shown in fig. 2 (a), the sampling switch S P 、S N On, input signal V INP 、V INN Respectively sampling the upper electrode plates of the forward capacitor array and the reverse capacitor array, simultaneously connecting one unit capacitor lower electrode plate in the forward capacitor array to gnd, and connecting the other unit capacitor lower electrode plate to V CM (ii) a Bottom plate connection of MSB capacitor array in reverse capacitor arrayTo gnd, the lower plate of the LSB capacitor array is connected to V CM 。
Comparison phase
After sampling is finished, a sampling switch S P 、S N And the upper plate of the capacitor is opened, the connection with the input signal is disconnected, and the switch energy consumed in the process is 0, as shown in fig. 2 (b).
Starting the first comparison, if V INP -V INN If greater than 0, the digital code B is output 3 Is 1; if V INP -V INN If the value is less than or equal to 0, the digital code B is output 3 Is 0;
as shown in FIG. 3, if B 3 To be 1, the lower plate of MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The lower polar plate of LSB capacitor array is composed of V CM Switch to V REF The forward capacitor array remains unchanged, and the switch energy consumed in the process is 0; if V INP -V INN If the value is less than or equal to 0, the digital code B is output 3 Is 0, and the lower plate of a unit capacitor in the forward capacitor array is switched from gnd to V CM One unit capacitance is formed by V CM Switch to V REF The reverse capacitor array remains unchanged, and the switch energy consumed in the process is 0;
then, the second comparison is carried out to obtain an output digital code B 2 . When B is present 3 If V is not less than 1 INP -V INN Greater than V REF A/2, then the digital code B is output 2 =1; when B is present 3 If V is not less than 1 INP -V INN V is less than or equal to REF A/2, then the digital code B is output 2 =0; when B is present 3 When =0, if V INP -V INN Greater than-V REF A/2, then the digital code B is output 2 =1; when B is present 3 When =0, if V INP -V INN Is less than or equal to-V REF A/2, then the digital code B is output 2 ＝0；
As shown in FIG. 4, when B 3 B 2 When =11, V is compared with V in the forward capacitor array CM The lower plate of the unit capacitor connected is switched to gnd, the lower plate of the unit capacitor connected with gnd is kept unchanged, the reverse capacitor array is kept unchanged, and the upper plate of the unit capacitor is switched to gndThe switch energy consumed by the program is 0; when B is present 3 B 2 When =10, V is compared with V in the forward capacitor array CM The lower plate of the unit capacitor connected with gnd is switched to V CM The reverse capacitor array remains unchanged, and the switch energy consumed in the process is 0; when B is present 3 B 2 When =01, V is summed in the forward capacitor array REF The lower plate of the connected unit capacitor is switched to V CM And V and CM the lower electrode plate of the connected unit capacitor is kept to be 0, the reverse capacitor array is kept to be constant, and the switch energy consumed in the process is 0; when B is present 3 B 2 When =00, V is compared with V in forward capacitor array CM The lower plate of the connected unit capacitor is switched to V REF And V and REF the lower electrode plate of the connected unit capacitor is kept unchanged, the reverse capacitor array is kept unchanged, and the switch energy consumed in the process is 0;
followed by a third comparison to obtain B 1 . When B is present 3 B 2 If V is not less than 11 INP -V INN Greater than (3/4) V REF Then outputs the digital code B 1 =1; when B is present 3 B 2 If V is not less than 11 INP -V INN Less than or equal to (3/4) V REF Then outputs the digital code B 1 =0; when B is present 3 B 2 If V is 10 = V INP -V INN Greater than (1/4) V REF Then outputs the digital code B 1 =1; when B is present 3 B 2 If V is 10, if V INP -V INN Less than or equal to (1/4) V REF Then outputs the digital code B 1 =0; when B is present 3 B 2 If V is =01 INP -V INN Greater than (-1/4) V REF Then output the digital code B 1 =1; when B is present 3 B 2 If V is =01 INP -V INN Less than or equal to (-1/4) V REF Then outputs the digital code B 1 =0; when B is present 3 B 2 When =00, if V INP -V INN Greater than (-3/4) V REF Then outputs the digital code B 1 =1; when B is present 3 B 2 When =00, if V INP -V INN Less than or equal to (-3/4) V REF Then outputs the digital code B 1 ＝0；
As shown in FIG. 5, when B 3 B 2 B 1 =111, the lower plate of the capacitor (maximum capacitor) in the MSB capacitor array in the reverse capacitor array is shifted from V CM Switch to V REF The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 When =110, the lower plate of the corresponding capacitor (maximum capacitor) in the LSB capacitor array in the inverse capacitor array is from V REF Switch to V CM The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 =101, the lower plate of the capacitor (maximum capacitor) in the MSB capacitor array in the reverse capacitor array is shifted from V CM Switch to V REF The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 When =100, the lower plate of the corresponding capacitor (maximum capacitor) in the LSB capacitor array in the inverse capacitor array is from V REF Switch to V CM The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 When =011, the lower plate of the capacitor (maximum capacitor) in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 When =010, the lower plate of the corresponding capacitor (maximum capacitor) in the LSB capacitor array in the reverse capacitor array is V CM The lower plate of the rest capacitor is kept unchanged after being switched to gnd, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 =001, the lower plate of the capacitor (maximum capacitor) in the MSB capacitor array in the inverse capacitor array is switched from gnd to V CM The lower plate of the rest capacitor is kept unchanged, and the switch energy consumed in the process is (1/16) CV REF 2 (ii) a When B is present 3 B 2 B 1 When the capacitance is not less than 000, the lower polar plate of the corresponding capacitor in the LSB capacitor array in the reverse capacitor array is V CM The lower plate of the rest capacitor is kept unchanged after being switched to gnd, and the switch energy consumed in the process is (1/16) CV REF 2 ；
Then, a fourth comparison is performed to obtain B 0 . When B is present 3 B 2 B 1 If V is not less than 111, if V is not less than INP -V INN Greater than (7/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 =111, if V INP -V INN Less than or equal to (7/8) V REF Then output the digital code B 0 =0; when B is present 3 B 2 B 1 If V is not less than 110 = V INP -V INN Greater than (5/8) V REF Then output the digital code B 0 =1; when B is present 3 B 2 B 1 If V is not less than 110 = V INP -V INN Less than or equal to (5/8) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 If V is not less than 101 INP -V INN Greater than (3/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 If V is not less than 101 INP -V INN Less than or equal to (3/8) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 If V is 100, then INP -V INN Greater than (1/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 If V is 100, then INP -V INN Less than or equal to (1/4) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 When =011, if V INP -V INN Greater than (-1/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 If V is 011 INP -V INN Less than or equal to (-1/8) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 If V is not less than 010 INP -V INN Greater than (-3/8) V REF Then, thenOutput digital code B 0 =1; when B is present 3 B 2 B 1 If =010, if V INP -V INN Less than or equal to (-3/8) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 When =001, if V INP -V INN Greater than (-5/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 When =001, if V INP -V INN Less than or equal to (-5/8) V REF Then outputs the digital code B 0 =0; when B is present 3 B 2 B 1 If V is not less than 000 INP -V INN Greater than (-7/8) V REF Then outputs the digital code B 0 =1; when B is present 3 B 2 B 1 When =000, if V INP -V INN Less than or equal to (-7/8) V REF Then output the digital code B 0 ＝0；
For the N-bit successive approximation type analog-to-digital converter, the average switching power consumption in the conversion process meets the formula by adopting the switching method provided by the invention:
Figure BDA0001282920570000101
wherein: n is the precision of the analog-to-digital converter; i is the serial number of the bit conversion cycle; c is the capacitance value of the unit capacitor in the capacitor array, V REF Is the high level of the supply voltage of the analog-to-digital converter.
As shown in fig. 6, taking a 10-bit successive approximation analog-to-digital converter as an example, a MATLAB simulation result graph of the variation of the switching power consumption with the digital output code during the conversion process is shown. It can be seen that the switching method provided by the invention has very low energy consumption, compared with the traditional structure, the average energy consumption is saved by 99.23%, the total area of the capacitor is saved by 87.4%, and the switching method has good economic benefit.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims (3)

1. A successive approximation analog-to-digital converter, comprising: comprises a positive input voltage, a negative input voltage, a comparator and a sampling switch S P Sampling switch S N The output end of the comparator is connected to the successive approximation register control logic circuit, and the positive input end of the comparator passes through the sampling switch S P Connected to a positive input voltage, the negative input of the comparator being connected to the positive input voltage via a sampling switch S N Is connected to a negative input voltage;
the capacitor array comprises a positive capacitor array and a negative capacitor array, the positive capacitor array comprises two first capacitors, an upper plate of each first capacitor is connected to a positive input end of the comparator, and a lower plate of each first capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd; the negative capacitance array comprises an MSB capacitance array and an LSB capacitance array, the MSB capacitance array is composed of binary weighted capacitances, the MSB capacitance array comprises N-2 second capacitances, the LSB capacitance array is composed of binary weighted capacitances, the LSB capacitance array comprises N-2 second capacitances, N is the precision of a successive approximation type analog-to-digital converter, and the maximum value of the capacitance is 2 N-4 A unit capacitance; the upper polar plate of each second capacitor is connected to the negative input end of the comparator, and the lower polar plate of each second capacitor is selectively connected with a reference voltage V through a switch REF 、V CM And gnd;
the V is REF =2V CM Gnd =0V; the value of the first capacitor is C, and C is a unit capacitor.
2. A successive approximation analog to digital converter as claimed in claim 1, characterized in that: the maximum value of the second capacitance is 2 N-4 And C is unit capacitance.
3. A switching method of a successive approximation type analog-to-digital converter is characterized by comprising the following steps: the switching method entails providing a successive approximation analog to digital converter as claimed in any one of claims 1 and 2; the method specifically comprises the following steps:
a sampling stage:
positive input voltage V INP By means of a sampling switch S P Is connected to the upper plate of the forward capacitor array, the lower plate of one of the two unit capacitors in the forward capacitor array is connected to gnd, and the other unit capacitor is connected to V CM (ii) a Negative input voltage V INN By means of a sampling switch S N Is conductively connected to the upper plate of the reverse capacitor array, all the lower plates of the MSB capacitor array in the reverse capacitor array are connected to gnd, and all the lower plates of the LSB capacitor array are connected to V CM ；
A comparison stage:
first, a sampling switch S P 、S N Disconnecting, and starting first comparison to obtain MSB; if V INP Greater than V INN Then the voltage of the lower plate of each capacitor in the reverse capacitor array is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; conversely, the lower plate of each capacitor in the forward capacitor array is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
then starting a second comparison; if V INP Greater than (V) INN + V REF /2), then the forward capacitor array is connected to V CM The lower plate of the unit capacitor is switched to gnd, and the positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN +V REF /2) and greater than 0, the lower plate of the unit capacitor connected to gnd in the forward capacitor array is switched to V CM The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Greater than (V) INN - V REF /2) and 0 or less, the forward directionConnection to V in a capacitor array REF Lower plate of the unit capacitor is switched to V CM The positive input terminal voltage of the comparator is reduced by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN - V REF /2), then the forward capacitor array is connected to V CM Lower plate of the unit capacitor is switched to V REF The positive input voltage of the comparator is increased by V REF The voltage of the lower electrode plate of the reverse capacitor array is kept unchanged;
a third comparison is then made; if V INP Greater than (V) INN + (3/4)V REF ) And the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is V CM Switch to V REF The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN + (3/4)V REF ) And is greater than (V) INN + (1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is changed from V REF Switch to V CM The negative input voltage of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN + (1/4)V REF ) And is not more than (V) INN + (1/2)V REF ) And the lower plate of the corresponding capacitor in the MSB capacitor array in the reverse capacitor array is V CM Switch to V REF The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN + (1/4)V REF ) And is greater than V INN And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is changed from V REF Switch to V CM The voltage at the negative input terminal of the comparator is reduced by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN - (1/4)V REF ) And V is INP V is less than or equal to INN Then the corresponding capacitor bottom plate in the MSB capacitor array in the reverse capacitor array is switched from gndTo V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN - (1/4)V REF ) And is greater than (V) INN - (1/2)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is changed from V CM Switched to gnd, the negative input voltage of the comparator decreases by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Greater than (V) INN - (3/4)V REF ) And is not more than (V) INN - (1/2)V REF ) Then the corresponding capacitor bottom plate in the MSB capacitor array in the reverse capacitor array is switched from gnd to V CM The negative input voltage of the comparator is increased by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged; if V INP Is less than or equal to (V) INN - (3/4)V REF ) And the voltage of the lower plate of the capacitor corresponding to the LSB capacitor array in the reverse capacitor array is from V CM Switched to gnd, the negative input voltage of the comparator decreases by V REF The voltage of the lower plate of the forward capacitor array is kept unchanged;
and sequentially comparing step by step until LSB is obtained, and completing analog-to-digital conversion.
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