CN109039332B - Successive approximation type analog-to-digital converter and low-power-consumption switching algorithm thereof - Google Patents
Successive approximation type analog-to-digital converter and low-power-consumption switching algorithm thereof Download PDFInfo
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- CN109039332B CN109039332B CN201810613627.2A CN201810613627A CN109039332B CN 109039332 B CN109039332 B CN 109039332B CN 201810613627 A CN201810613627 A CN 201810613627A CN 109039332 B CN109039332 B CN 109039332B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Abstract
The invention discloses a successive approximation type analog-to-digital converter and a low-power-consumption switching algorithm thereof, and energy consumed by a capacitor array in an SAR ADC in the switching process is greatly reduced by adopting a split capacitor array structure and reasonable control logic setting. Compared with the traditional switching algorithm, the switching algorithm provided by the invention saves 99.76% of conversion energy and 75% of capacitance area, and improves economic benefits. In addition, the open algorithm provided by the invention enables the output common-mode voltage of the capacitor array to have slight change only in the conversion of the lowest bit, thereby greatly reducing the complexity of the design of the comparator.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a successive approximation type analog-to-digital converter structure adopting an upper polar plate sampling technology and a low-power-consumption switching algorithm.
Background
Successive approximation analog-to-digital converter (SARADC) is widely applied to the fields of low power consumption, such as wireless sensor nodes, biomedical electronics, environmental monitoring and the like. The sar adc is mainly composed of a capacitor array, a comparator and digital control logic. The power consumption of the digital control logic is continuously reduced along with the progress of the process size, and the use of the dynamic comparator causes the power consumption of the comparator to be smaller and smaller in proportion to the power consumption of the sar adc. The traditional switching algorithm can cause the power consumption and occupied area consumed in the capacitor array to be larger, and is not beneficial to being widely applied to the current low-power-consumption field.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects of the prior art, a successive approximation type analog-to-digital converter adopting an upper polar plate sampling technology and a low-power-consumption switching algorithm thereof are provided, so that the switching energy consumption of the SARADC consumed in a capacitor array is greatly reduced.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
a successive approximation type analog-to-digital converter structure comprises a sampling switch, a capacitor array, a comparator and digital control logic; the sampling switch adopts a differential structure, the capacitor array comprises an upper capacitor array and a lower capacitor array, and an input signal VipThe same phase end of the sampling switch is connected to the upper polar plate of the upper capacitor array, and an input signal VinThe sampling switch is connected to the upper pole plate of the lower capacitor array through the inverting terminal, the upper pole plate of the upper capacitor array is connected with the inverting input terminal of the comparator, the upper pole plate of the lower capacitor array is connected with the inverting input terminal of the comparator, and the differential output of the comparator generates a corresponding control signal to control the lower pole plate switch of the capacitor array after passing through the digital control logic, so that the lower pole plate of the capacitor array is connected to the corresponding reference voltage.
As a further preferable scheme of the successive approximation type analog-to-digital converter structure of the present invention, in the N-bit sar adc, the capacitor array is divided into an upper capacitor array and a lower capacitor array which are identical to each other, and each capacitor array includes a dummy capacitor CdLowest order capacitor C0And highest order capacitance CN-3And other capacitors are distributed according to binary weights, specifically:
highest bit capacitance CN-3
Highest order capacitor CN-3Split into structures identical to all other low-level capacitor structures, i.e. CN-3Is numerically equal to the sum of all other low-side capacitances, expressed as:
CN-3＝CD+C0+C1+C2+…+CN-4＝2N-3Cu
lowest order capacitor C0To the next highest capacitor CN-4The binary capacitance weight is satisfied, and the expression is as follows:
Ci＝2iCu,0≤i≤N-4
dummy capacitor Cd；
dummy capacitor and lowest bit capacitor C0The capacitance values of (A) are the same and are the unit capacitance value of Cd＝Cu；
Wherein all lower plates of the highest-order capacitors of the upper capacitor array are connected to a reference voltage VrefThe lower polar plates of all other low-level capacitors are connected to GND; all lower pole plates of the highest-order capacitor of the lower capacitor array are connected to a reference voltage GND, and all other lower-order capacitor lower pole plates are connected to Vref。
A low-power consumption switching algorithm based on a successive approximation type analog-to-digital converter structure obtains an N-bit digital output code after N times of comparison of SARADC for a differential input signal, and the N times of comparison comprises two stages, specifically:
a sampling stage:
step A1, input signal VipAnd VinThe sampling switches are respectively connected to the upper polar plates of the upper capacitor array and the lower capacitor array;
step A2, connecting all the lower plates of the highest-order capacitors of the upper capacitor array to a reference voltage VrefThe lower polar plates of all other low-level capacitors are connected to GND;
step A3, connecting all lower plates of the highest capacitor of the lower capacitor array to reference voltage GND, and connecting all other lower capacitor plates to Vref；
A conversion stage:
step B1, determining the highest position D (N) and the next highest position D (N-1);
step B2, determining the 3 rd high position D (N-2);
step B3, determining D (N +1-k) according to the k comparison result, wherein k is more than or equal to 4 and less than or equal to N-1;
and step B4, determining D (1) according to the comparison result of D (N) and D (2).
As a further preferable scheme of the low power consumption switching algorithm based on the successive approximation type analog-to-digital converter structure of the present invention, the B1 specifically includes the following steps:
after the sampling stage is finished, the sampling switch disconnects the upper and lower capacitor arrays from the input signal, and the connection relationship of the lower polar plates of the upper and lower capacitor arrays is kept unchanged; at this time, the comparator directly compares the magnitudes of the sampled input signals Vip and Vin to obtain the values of D (N)A value; if D (N) is 1, the lower plate of the highest capacitor of the upper capacitor array needs to be driven from VrefIs connected to Vcm(Vcm＝1/2Vref) The lower plate of the highest capacitor of the lower capacitor array is connected to V from GNDcm(ii) a If D (N) is 0, the lower plates of all the capacitors except the highest capacitor in the upper capacitor array need to be connected from GND to VcmThe lower polar plates of all other capacitors except the highest capacitor in the lower capacitor array are V-shapedrefIs connected to Vcm(ii) a And when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-1).
As a further preferable scheme of the low power consumption switching algorithm based on the successive approximation type analog-to-digital converter structure of the present invention, the B2 specifically includes the following steps:
determining D (N-2) according to the comparison result of D (N) and D (N-1);
the first condition is as follows: if D (N) is equal to 1 and D (N-1) is equal to 1, the upper capacitor array C is needed to be arranged at the momentMSB-1,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-1,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case two: if D (N) is equal to 1 and D (N-1) is equal to 0, the upper capacitor array C is needed to be arranged at the momentMSB-2Is located to CdThe lower plate of the capacitor is connected to V from GNDcmLower capacitor array CMSB-2Is located to CdCapacitor lower plate from VrefIs connected to Vcm(ii) a When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case three: if D (N) is 0 and D (N-1) is 1, the upper capacitor array C is neededMSB-2,MIs located to Cd,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2,MIs located to Cd,MThe lower plate of the bit capacitor is connected to V from GNDcm(ii) a When the reference voltage is completely established, the comparator is used for electrically connecting the upper electrode plates of the upper capacitor array and the lower capacitor arrayComparing the pressures to obtain D (N-2);
case four: if D (N) is equal to 0 and D (N-1) is equal to 0, the upper capacitor array C is neededMSB-1Lower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-1The lower plate of the bit capacitor is connected to GND from Vcm; and when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2).
As a further preferable scheme of the low power consumption switching algorithm based on the successive approximation type analog-to-digital converter structure, the step B3 specifically includes the following steps:
determining D (N +1-k) according to the comparison result of D (N) and D (N-1);
the first condition is as follows: in the case of D (N) -1 and D (N-1) -1, if D (N +2-k) -1, the upper capacitor array C needs to be connected to the capacitor array C at this timeMSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref; if D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kThe lower plate of the bit capacitor is connected to V from GNDcmLower capacitor array CMSB-2+kLower plate of bit capacitor from VrefIs connected to VcmAfter the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
case two: in the case where D (N) is 1 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MThe lower plate of the bit capacitor is connected to GND from Vcm, and the lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmConnecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k);
case three: in the case where D (N) is 0 and D (N-1) is 1, if D (N +2-k) is 1, the above is requiredCapacitor array CMSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmConnecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k);
case four: in the case where D (N) is 0 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2+k,MThe lower plate of the bit capacitor is connected to Vcm from GND; if D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+kLower plate of bit capacitor from VcmAnd connecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k).
As a further preferable scheme of the low power consumption switching algorithm based on the successive approximation type analog-to-digital converter structure, the step B4 is specifically as follows:
the first condition is as follows: in the case where D (n) is 1, if D (2) is 1, C of the upper capacitor array is required at this timed,MBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededd,MBit capacitance slave VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1);
case two: in the case where D (n) is 0, if D (2) is 1, C of the upper capacitor array is required at this timedBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededdBit capacitance slave VcmConnected to GND, and the comparator is coupled to the upper and lower capacitor arrays when the reference voltage is completely establishedThe plate voltages are compared to obtain D (1).
Has the advantages that: compared with the prior art, the successive approximation type analog-to-digital converter structure adopting the upper polar plate sampling technology has the following advantages:
1. the invention adopts a split capacitor structure, an upper polar plate sampling technology and an LSB (least significant bit) single-ended switch switching technology, so that the area of a capacitor array is saved by 75% compared with the area of a traditional switch algorithm;
2. in the switching process of the switch, the energy consumption does not exist in the first comparison, and a part of energy is fed back to the reference voltage source by the capacitor array in the second comparison;
3. except the LSB conversion process, other conversion processes are all to switch the upper capacitor array and the lower capacitor array simultaneously, so that the common mode voltage of the capacitor arrays is basically unchanged, and the design of the comparator is simplified;
4. according to the invention, through optimizing the control logic, the energy consumption of switching of the capacitor array is greatly reduced.
Drawings
FIG. 1 is a structural diagram of an N-bit SARADC employed in the present invention;
FIG. 2 is a schematic diagram of a low-power capacitor switching algorithm applied to a 4-bit SARADC according to the present invention;
FIG. 3 is a waveform diagram of the output signal of the capacitor array when the switching algorithm of the present invention is applied to a 4bit SARADC;
fig. 4 is a diagram of switching power consumption when the switching algorithm of the present invention is applied to a 10bit sar adc.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
Fig. 1 shows a successive approximation type analog-to-digital converter structure using an upper plate sampling technique.
The capacitor array shown in FIG. 1 can realize the conversion of N-bit SARADC, the whole capacitor is divided into an upper capacitor array and a lower capacitor array which are identical, and each capacitor array mainly comprises a dummy capacitor CdLowest order capacitor CuAnd highest bit capacitanceCN-3And other capacitors are distributed according to binary weights, specifically:
highest bit capacitance CN-3
Highest order capacitor CN-3Split into structures identical to all other low-level capacitor structures, i.e. CN-3Is numerically equal to the sum of all other low-side capacitances, expressed as:
CN-3＝CD+C0+C1+C2+…+CN-4＝2N-3Cu
lowest order capacitor C0To the next highest capacitor CN-4The binary capacitance weight is satisfied, and the expression is as follows:
Ci＝2iCu,0≤i≤N-4
dummy capacitor Cd
dummy capacitor and lowest bit capacitor C0The capacitance values of (A) are the same and are the unit capacitance value of Cd＝Cu
According to the N-bit sar adc structure shown in fig. 1, for a differential input signal, after N times of comparison, an N-bit digital output code is obtained, and the N times of comparison includes two stages, specifically:
a sampling stage:
input signal VipAnd VinThe sampling switches are respectively connected to the upper polar plates of the upper capacitor array and the lower capacitor array; all lower plates of the highest-order capacitor of the upper capacitor array are connected to a reference voltage VrefThe lower polar plates of all other low-level capacitors are connected to GND; all lower pole plates of the highest-order capacitor of the lower capacitor array are connected to a reference voltage GND, and all other lower-order capacitor lower pole plates are connected to Vref。
A conversion stage:
(1) determining the highest bit D (N) and the second highest bit D (N-1):
and after the sampling stage is finished, the sampling switch disconnects the upper and lower capacitor arrays from the input signal, and the connection relation of the lower polar plates of the upper and lower capacitor arrays is kept unchanged. In this case, the comparator directly compares the sampled input signalComparison of Vip and Vin yields the value of D (N). If D (N) is 1, the lower plate of the highest capacitor of the upper capacitor array needs to be connected to V from VrefcmThe lower plate of the highest capacitor of the lower capacitor array is connected to V from GNDcm(ii) a If D (N) is 0, the lower plates of all the capacitors except the highest capacitor in the upper capacitor array need to be connected from GND to VcmThe lower polar plates of all other capacitors except the highest capacitor in the lower capacitor array are V-shapedrefIs connected to Vcm. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-1);
(2) determination of the 3 rd high position D (N-2):
determining D (N-2) according to the comparison result of D (N) and D (N-1)
The first condition is as follows: if D (N) is equal to 1 and D (N-1) is equal to 1, the upper capacitor array C is needed to be arranged at the momentMSB-1,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-1,MLower plate of bit capacitor from VcmIs connected to Vref. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case two: if D (N) is equal to 1 and D (N-1) is equal to 0, the upper capacitor array C is needed to be arranged at the momentMSB-2Is located to CdThe lower plate of the capacitor is connected to V from GNDcmLower capacitor array CMSB-2Is located to CdCapacitor lower plate from VrefIs connected to Vcm. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case three: if D (N) is 0 and D (N-1) is 1, the upper capacitor array C is neededMSB-2,MIs located to Cd,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2,MIs located to Cd,MThe lower plate of the bit capacitor is connected to V from GNDcm. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case four: if D (N) is equal to 0 and D (N-1) is equal to 0, then the requirement is thatUpper capacitor array CMSB-1Lower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-1Lower plate of bit capacitor from VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
(3) determining D (N +1-k) according to the k comparison result, wherein k is more than or equal to 4 and less than or equal to N-1
Determining D (N +1-k) according to the comparison result of D (N) and D (N-1)
The first condition is as follows: in the case of D (N) -1 and D (N-1) -1, if D (N +2-k) -1, the upper capacitor array C needs to be connected to the capacitor array C at this timeMSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kThe lower plate of the bit capacitor is connected to V from GNDcmLower capacitor array CMSB-2+kLower plate of bit capacitor from VrefIs connected to Vcm. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
case two: in the case where D (N) is 1 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MThe lower plate of the bit capacitor is connected to GND from Vcm, and the lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
case three: in the case where D (N) is 0 and D (N-1) is 1, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ D0, at this time, the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
in the case where D (N) is 0 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C needs to be used at this timeMSB-2+k,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2+k,MThe lower plate of the bit capacitor is connected to Vcm from GND; if D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+kLower plate of bit capacitor from VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
(4) determining D (1) according to the comparison result of D (N) and D (2);
the first condition is as follows: in the case where D (n) is 1, if D (2) is 1, C of the upper capacitor array is required at this timed,MBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededd,MBit capacitance slave VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1);
case two: in the case where D (n) is 0, if D (2) is 1, C of the upper capacitor array is required at this timedBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededdBit capacitance slave VcmIs connected to GND. And when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1).
The present invention will be described in detail with reference to an example, and fig. 2 shows a specific conversion process of the 4bit sar adc according to the present invention, which is implemented in detail as follows:
a sampling stage:
as shown in fig. 2 a, an input signal VipAnd VinThe sampling switches are respectively connected to the upper polar plates of the upper capacitor array and the lower capacitor array; all lower plates of the highest-order capacitor of the upper capacitor array are connected to a reference voltage VrefThe lower polar plates of all other low-level capacitors are connected to GND; all lower pole plates of the highest-order capacitor of the lower capacitor array are connected to a reference voltage GND, and all other lower-order capacitor lower pole plates are connected to Vref。
A conversion stage:
(1) determining the highest position D (4) and the second highest position D (3):
as shown in fig. 2B, after the sampling phase is finished, the sampling switch disconnects the upper and lower capacitor arrays from the input signal, and the connection relationship between the lower plates of the upper and lower capacitor arrays remains unchanged. At this time, the comparator directly compares the sampled input signal VipAnd VinThe values of (3) are compared to obtain the value of D (4). As shown in c.1 in fig. 2, if D (4) is 1, the lower plate of the highest capacitor of the upper capacitor array needs to be moved from VrefIs connected to VcmThe lower plate of the highest capacitor of the lower capacitor array is connected to V from GNDcmAfter the voltage has been completely built, Vp＝Vip-1/4Vref,Vn＝Vin+1/4Vref(ii) a As shown in c.2 in fig. 2, if D (4) ═ 0, it is necessary to connect the lower plates of all the capacitors in the upper capacitor array except the highest-order capacitor from GND to VcmThe lower polar plates of all other capacitors except the highest capacitor in the lower capacitor array are V-shapedrefIs connected to VcmAfter the voltage has been completely built, Vp＝Vip+1/4Vref,Vn＝Vin-1/4Vref. When the reference voltage is completely established, the comparator compares the voltages V of the upper electrode plates of the upper capacitor array and the lower capacitor arraypAnd VnComparing to obtain D (3);
(2) determination of the 3 rd high position D (2):
determining D (2) from the comparison of D (4) and D (3)
The first condition is as follows: if D (4) is 1 and D (3) is 1, as shown in d.1 in fig. 2, then it is necessary to addCapacitor array C0,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array C0,MCapacitor lower plate from VcmIs connected to VrefAfter the voltage has been completely built, Vp＝Vip-3/8Vref,Vn＝Vin+3/8Vref. Then the comparator compares the upper electrode plate voltage V of the upper capacitor array and the lower capacitor arraypAnd VnComparing to obtain D (2);
case two: if D (4) is 1 and D (3) is 0, as shown in d.2 in fig. 2, it is necessary to put the upper capacitor array C on0The lower plate is connected to V from GNDcmLower capacitor array C0Is located to CdCapacitor lower plate from VrefIs connected to VcmAfter the voltage has been completely built, Vp＝Vip-1/8Vref,Vn＝Vin+1/8Vref. Then the comparator compares the upper electrode plate voltage V of the upper capacitor array and the lower capacitor arraypAnd VnComparing to obtain D (2);
case three: if D (4) is 0 and D (3) is 1, as shown in d.3 in fig. 2, it is necessary to put the upper capacitor array C on0,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array C0,MThe lower plate of the bit capacitor is connected to V from GNDcmAfter the voltage has been completely built, Vp＝Vip+1/8Vref,Vn＝Vin-1/8Vref. Then the comparator compares the upper electrode plate voltage V of the upper capacitor array and the lower capacitor arraypAnd VnComparing to obtain D (2);
case four: if D (4) is 0 and D (3) is 0, as shown in d.4 in fig. 2, it is necessary to put the upper capacitor array C on0Lower plate of bit capacitor from VcmIs connected to VrefLower capacitor array C0The lower polar plate of the bit capacitor is connected to GND from Vcm, and after the voltage is completely built, Vp＝Vip+3/8Vref,Vn＝Vin-3/8Vref. Then the comparator compares the upper electrode plate voltage V of the upper capacitor array and the lower capacitor arraypAnd VnComparing to obtain D (2);
(4) determining D (1) according to the comparison result of D (4) and D (2);
the first condition is as follows: in the case where D (4) is 1, if D (2) is 1, as shown in e.1 and e.3 in fig. 2, C of the capacitor array to be mounted at this time is requiredd,MBit capacitance slave VcmIs connected to GND; if D (2) ═ 0, as shown in e.2 and E.4 in fig. 2, then C for the lower capacitor array is neededd,MBit capacitance slave VcmIs connected to GND. When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1);
case two: in the case where D (n) is 0, if D (2) is 1, as shown in e.5 and e.7 in fig. 2, C of the capacitor array to be mounted at this time is requireddBit capacitance slave VcmIs connected to GND; if D (2) ═ 0, as shown in e.6 and E.8 in fig. 2, then C for the lower capacitor array is neededdBit capacitance slave VcmIs connected to GND. And when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1).
After the above steps, 4-bit digital output code can be obtained.
As shown in fig. 3, the waveform of the output signal of the capacitor array when the switching algorithm provided by the present invention is applied to the 4bit sar adc, it can be seen from the graph that the output common mode voltage of the capacitor array is kept constant in other conversion processes except for slight change of the LSB bit, thereby reducing the design difficulty of the comparator.
Fig. 4 is a schematic diagram showing energy consumption corresponding to different digital codes when the switching algorithm provided by the present invention is applied to a 10bit sar adc. As can be seen from the figure, the switch energy consumption is very low, and the average energy consumption is 3.21CVref 2Compared with the traditional 10bit SARADC, the energy consumption of switching is saved by 99.76%.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (6)
1. Successive approximation type mouldA digital converter, characterized by: the circuit comprises a sampling switch, a capacitor array, a comparator and digital control logic; the sampling switch adopts a differential structure, the capacitor array comprises an upper capacitor array and a lower capacitor array, and an input signal VipThe same phase end of the sampling switch is connected to the upper polar plate of the upper capacitor array, and an input signal VinThe sampling switch is connected to the upper pole plate of the lower capacitor array through the inverting terminal, the upper pole plate of the upper capacitor array is connected with the inverting input terminal of the comparator, the upper pole plate of the lower capacitor array is connected with the inverting input terminal of the comparator, and the differential output of the comparator generates a corresponding control signal to control the lower pole plate switch of the capacitor array after passing through the digital control logic, so that the lower pole plate of the capacitor array is connected to the corresponding reference voltage;
the capacitor array is characterized in that in the N-bit SAR ADC, the whole capacitor array is divided into an upper capacitor array and a lower capacitor array which are identical, and each capacitor array comprises a dummy capacitor CdLowest order capacitor C0And highest order capacitance CN-3And other capacitors are distributed according to binary weights, specifically:
highest bit capacitance CN-3
Highest order capacitor CN-3Split into structures identical to all other low-level capacitor structures, i.e. CN-3Is numerically equal to the sum of all other low-side capacitances, expressed as:
CN-3＝CD+C0+C1+C2+…+CN-4＝2N-3Cu
lowest order capacitor C0To the next highest capacitor CN-4The binary capacitance weight is satisfied, and the expression is as follows:
Ci＝2iCu,0≤i≤N-4
dummy capacitor Cd；
dummy capacitor and lowest bit capacitor C0The capacitance values of (A) are the same and are the unit capacitance value of Cd＝Cu；
Wherein all lower plates of the highest-order capacitors of the upper capacitor array are connected to a reference voltage VrefWhich isAll lower pole plates of the low-order capacitor are connected to GND; all lower pole plates of the highest-order capacitor of the lower capacitor array are connected to a reference voltage GND, and all other lower-order capacitor lower pole plates are connected to Vref。
2. A low power switching algorithm based on a successive approximation analog-to-digital converter according to claim 1, characterized in that: for a differential input signal, after N times of comparison of the SAR ADC, obtaining an N-bit digital output code, wherein the N times of comparison comprises two stages, specifically:
a sampling stage:
step A1, input signal VipAnd VinThe sampling switches are respectively connected to the upper polar plates of the upper capacitor array and the lower capacitor array;
step A2, connecting all the lower plates of the highest-order capacitors of the upper capacitor array to a reference voltage VrefThe lower polar plates of all other low-level capacitors are connected to GND;
step A3, connecting all lower plates of the highest capacitor of the lower capacitor array to reference voltage GND, and connecting all lower plates of other low capacitors to Vref；
A conversion stage:
step B1, determining the highest position D (N) and the next highest position D (N-1);
step B2, determining the 3 rd high position D (N-2);
step B3, determining D (N +1-k) according to the k comparison result, wherein k is more than or equal to 4 and less than or equal to N-1;
and step B4, determining D (1) according to the comparison result of D (N) and D (2).
3. The successive approximation analog-to-digital converter structure-based low power switching algorithm of claim 2, characterized in that: the B1 specifically comprises the following steps:
after the sampling stage is finished, the sampling switch disconnects the upper and lower capacitor arrays from the input signal, and the connection relationship of the lower polar plates of the upper and lower capacitor arrays is kept unchanged; at this time, the comparator directly compares the magnitudes of the sampled input signals Vip and Vin to obtain the value of d (n); if D (N)If 1, the lower plate of the highest capacitor of the upper capacitor array needs to be driven from VrefIs connected to Vcm(Vcm＝1/2Vref) The lower plate of the highest capacitor of the lower capacitor array is connected to V from GNDcm(ii) a If D (N) is 0, the lower plates of all the capacitors except the highest capacitor in the upper capacitor array need to be connected from GND to VcmThe lower polar plates of all other capacitors except the highest capacitor in the lower capacitor array are V-shapedrefIs connected to Vcm(ii) a And when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-1).
4. The successive approximation analog-to-digital converter based low power switching algorithm of claim 2, characterized in that: the B2 specifically comprises the following steps:
determining D (N-2) according to the comparison result of D (N) and D (N-1);
the first condition is as follows: if D (N) is equal to 1 and D (N-1) is equal to 1, the upper capacitor array C is needed to be arranged at the momentMSB-1,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-1,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case two: if D (N) is equal to 1 and D (N-1) is equal to 0, the upper capacitor array C is needed to be arranged at the momentMSB-2Is located to CdThe lower plate of the capacitor is connected to V from GNDcmLower capacitor array CMSB-2Is located to CdCapacitor lower plate from VrefIs connected to Vcm(ii) a When the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2);
case three: if D (N) is 0 and D (N-1) is 1, the upper capacitor array C is neededMSB-2,MIs located to Cd,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2,MIs located to Cd,MThe lower plate of the bit capacitor is connected to V from GNDcm(ii) a When the reference voltage is completely built up, the comparator is paired upComparing the voltages of the upper electrode plates of the lower two capacitor arrays to obtain D (N-2);
case four: if D (N) is equal to 0 and D (N-1) is equal to 0, the upper capacitor array C is neededMSB-1Lower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-1The lower plate of the bit capacitor is connected to GND from Vcm; and when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N-2).
5. The successive approximation analog-to-digital converter based low power switching algorithm of claim 2, characterized in that: the step B3 specifically includes the following steps:
determining D (N +1-k) according to the comparison result of D (N) and D (N-1);
the first condition is as follows: in the case of D (N) -1 and D (N-1) -1, if D (N +2-k) -1, the upper capacitor array C needs to be connected to the capacitor array C at this timeMSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref; if D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kThe lower plate of the bit capacitor is connected to V from GNDcmLower capacitor array CMSB-2+kLower plate of bit capacitor from VrefIs connected to VcmAfter the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (N + 1-k);
case two: in the case where D (N) is 1 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MThe lower plate of the bit capacitor is connected to GND from Vcm, and the lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmConnecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k);
case three: in thatIf D (N +2-k) is 1, the upper capacitor array C is needed to be used when D (N) is 0 and D (N-1) is 1MSB-2+k,MLower plate of bit capacitor from VcmConnected to GND, lower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmIs connected to Vref(ii) a If D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+k,MLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+k,MLower plate of bit capacitor from VcmConnecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k);
case four: in the case where D (N) is 0 and D (N-1) is 0, if D (N +2-k) is 1, the upper capacitor array C is required to be arranged at this timeMSB-2+k,MLower plate of bit capacitor from VrefIs connected to VcmLower capacitor array CMSB-2+k,MThe lower plate of the bit capacitor is connected to Vcm from GND; if D (N +2-k) ═ 0, then the upper capacitor array C is neededMSB-2+kLower plate of bit capacitor from VcmIs connected to VrefLower capacitor array CMSB-2+kLower plate of bit capacitor from VcmAnd connecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (N + 1-k).
6. The successive approximation analog-to-digital converter based low power switching algorithm of claim 2, characterized in that: the step B4 is specifically as follows:
the first condition is as follows: in the case where D (n) is 1, if D (2) is 1, C of the upper capacitor array is required at this timed,MBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededd,MBit capacitance slave VcmIs connected to GND; when the reference voltage is completely established, the comparator compares the voltages of the upper electrode plates of the upper capacitor array and the lower capacitor array to obtain D (1);
case two: in the case where D (n) is 0, if D (2) is 1, C of the upper capacitor array is required at this timedBit capacitance slave VcmIs connected to GND; if D (2) is 0, then C of the lower capacitor array is neededdBit capacitance slave VcmAnd connecting to GND, and comparing the voltages of the upper electrode plates of the upper and lower capacitor arrays by a comparator after the reference voltage is completely established to obtain D (1).
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| CN109936370B (en) * | 2019-03-04 | 2023-03-24 | 东南大学 | Low-power-consumption switching algorithm applied to SAR ADC |
| CN110198169B (en) * | 2019-05-09 | 2022-12-13 | 东南大学 | Self-adaptive predictive low-power-consumption switching method suitable for SAR ADC |
| CN110380730B (en) * | 2019-07-04 | 2023-02-24 | 东南大学 | Capacitor array switching method applied to low-voltage SAR ADC |
| CN110311677B (en) * | 2019-07-10 | 2023-01-03 | 湖北汽车工业学院 | SAR ADC based on novel capacitance switch switching algorithm |
| CN110912558B (en) * | 2019-11-29 | 2021-11-19 | 西安交通大学 | Two-step asymmetric alternating monotonic switching successive approximation type analog-to-digital converter |
| CN111371457B (en) * | 2020-03-12 | 2023-05-23 | 东南大学 | Analog-to-digital converter and three-level switching method applied to SAR ADC |
| CN112039528B (en) * | 2020-07-22 | 2022-11-29 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN111934689B (en) * | 2020-09-23 | 2021-07-06 | 电子科技大学中山学院 | High-precision analog-to-digital converter and conversion method |
| CN112332847B (en) * | 2020-12-07 | 2024-03-15 | 东南大学 | Two-level switching method applied to successive approximation type analog-to-digital converter |
| CN112583409B (en) * | 2020-12-28 | 2024-03-15 | 东南大学 | Successive approximation type analog-to-digital converter and three-level switching method thereof |
| CN113131934B (en) * | 2021-04-29 | 2022-11-08 | 东南大学 | Comparator offset voltage calibration method applied to 16-bit low-power-consumption successive approximation type analog-to-digital converter |
| CN114095029B (en) * | 2021-11-26 | 2023-08-22 | 江苏科技大学 | Successive approximation type analog-to-digital converter capable of reducing number of capacitors and switches |
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