CN111641413B - Capacitor array switching method of high-energy-efficiency SAR ADC - Google Patents
Capacitor array switching method of high-energy-efficiency SAR ADC Download PDFInfo
- Publication number
- CN111641413B CN111641413B CN202010733531.7A CN202010733531A CN111641413B CN 111641413 B CN111641413 B CN 111641413B CN 202010733531 A CN202010733531 A CN 202010733531A CN 111641413 B CN111641413 B CN 111641413B
- Authority
- CN
- China
- Prior art keywords
- capacitor array
- dac
- vref
- split capacitor
- vaq
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Abstract
The invention discloses a capacitor array switching method of an SAR ADC with high energy efficiency, wherein a capacitor array adopts two identical split capacitor structures, and a third level of Vaq =1/4 Vref is introduced to assist in switching of the capacitor array. The input signals Vip and Vin are compared for N times to obtain an N-bit digital output code, the N-bit digital output code is divided into two stages of sampling and conversion, the sampling stage is respectively connected to top polar plates of an upper capacitor array and a lower capacitor array through sampling switches according to the input signals Vip and Vin, and bottom polar plates of all capacitors of the upper capacitor array and bottom polar plates of all capacitors of the lower capacitor array are connected to corresponding voltages; the conversion stage comparator compares the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array from MSB bits to LSB bits to obtain corresponding digital codes, and controls the connection relation of the bottom electrode plates of the upper capacitor array and the lower capacitor array according to the digital codes; n times of comparison are carried out to obtain N-bit digital output codes. The third level is utilized to greatly reduce the power consumption of the DAC part in the conversion process, and the method is suitable for the design of the SAR ADC with high energy efficiency.
Description
Technical Field
The invention relates to a capacitor array switching method of an SAR ADC (successive approximation register analog-to-digital converter) with high energy efficiency and capacity area saving, and belongs to the technical field of capacitor type DACs of SAR ADCs.
Background
The SAR ADC is compatible with advanced technology because most of circuits are composed of digital circuits and no operational amplifier exists, and the SAR ADC has high energy efficiency. SAR ADCs of medium precision (8-12 bits), medium sampling rate (< 1 MHz) are widely used in the fields of biomedical electronics, wearable devices, implantable devices, portable devices, and wireless sensor network nodes. The power consumption of SAR ADCs comes mainly from capacitive DACs, comparators and digital control logic, while at low speeds, the switching power consumption of capacitive DACs accounts for a significant proportion of the overall power consumption.
In prior studies, various switching algorithms have been proposed to reduce the switching power consumption of capacitive DACs. The third reference level is introduced into the three-level switching algorithm, which is generally 0.5Vref, so that the switching algorithm is more flexible, and the switching power consumption of the DAC is usually lower. The value of the third level is selected to Vaq =1/4 Vref, and further reduction of power consumption can be achieved. Meanwhile, the area of the capacitor array can be effectively reduced by adopting the capacitor array with the split capacitor structure. Therefore, in low power SAR ADC designs, it is desirable to reduce the power consumption of the capacitive switches as much as possible, while reducing the value of the unit capacitance.
Disclosure of Invention
Technical problems: the invention provides a capacitor array switching method which has high energy efficiency and simultaneously saves a capacitor area SAR ADC, and aims at the design of the low-power SAR ADC, how to reduce the switching power consumption of a capacitor DAC as much as possible; the switching power consumption of the capacitor DAC is reduced by combining the split capacitor structure technology, the Vaq-based switching technology and the monotonic switching.
The technical scheme is as follows: the technical scheme adopted by the invention specifically solves the technical problems as follows:
the SAR ADC capacitor array switching method with high energy efficiency and capacity area saving is based on the capacitor array adopting two identical split capacitor structures, and simultaneously introducing a third level of Vaq =1/4 Vref to assist the switching of the capacitor array, and comprises a sampling switch, a capacitor array, a comparator and digital control logic; the input signal Vip is connected to the P-terminal split capacitor array high-stage DAC through a sampling switch PH And low-stage DAC PL Is connected to the upper stage DAC of the N-terminal split capacitor array through the sampling switch NH And low-stage DAC NL A top plate of (2); the top polar plate of the P-end capacitor array is connected with the non-inverting input end of the comparator, and the top polar plate of the N-end capacitor array is connected with the inverting input end of the comparator; the differential output end of the comparator generates a control signal to control the bottom plate switches of the P end and the N end capacitor arrays after digital control logic, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding reference voltages;
the P-end split capacitor arrays comprise a high-section capacitor array DAC PH And low-stage DAC PL The structures of the two sections of capacitor arrays are identical, the structure of the N-terminal split capacitor array is identical to the structure of the P-terminal, and the sizes of the capacitors of each section are as follows: c (C) i ＝2 i-2 C, wherein i is more than or equal to 2 and less than or equal to N-3, and capacitance C 1 ＝C 2 =c, where C is the unit capacitance size;
the method comprises the steps of comparing input signals Vip and Vin for N times to obtain an N-bit digital output code, wherein the N-bit digital output code is divided into two stages of sampling and conversion, and the method specifically comprises the following steps:
step A, sampling stage
Input signals Vip and Vin are respectively connected to the high-stage DAC of the P-end split capacitor array through sampling switches PH And low-stage DAC PL Top pole plate and N-terminal split capacitor array high-stage DAC (digital-to-analog converter) NH And low-stage DAC NL High Duan Dianrong array DAC PH And DAC NH The bottom electrode plates of all the capacitors in the capacitor array DAC are connected to the Vref reference voltage PL And DAC NL The bottom plates of all of the capacitors in (a) are connected to Gnd;
step B, transition stage
Step B1, the sampling switch is disconnected, and the comparator directly compares MSB bits of input signals Vip and Vin which are kept on the top polar plates of the P end capacitor array and the N end capacitor array respectively to obtain a digital code D N-1 According to the digital code D N-1 Controlling the connection relation of the bottom electrode plates of the capacitors in the P-end capacitor array and the N-end capacitor array;
case one: if D N-1 =1, for P-side split capacitor array high-side DAC PH And N-terminal split capacitor array low-stage DAC NL Simultaneously switching to Vaq to produce a voltage offset of-1/2 Vref;
and a second case: if D N-1 =0, for P-side split capacitor array low-side DAC PL And N-terminal split capacitor array high-stage DAC NH Simultaneously switching to Vaq to produce a voltage offset of 1/2 Vref;
step B2, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B1 N-2 According to the digital code D N-2 Controlling and controlling the connection relation of the capacitor bottom plates in the P-end and N-end capacitor arrays;
case one: if D N-2 =1, for P-side split capacitor array low-side DAC PL Is switched to Vaq and the N-terminal split capacitor array low-stage DAC NL Is switched to Vref to generate a voltage of-1/4 VrefOffset;
and a second case: if D N-2 =0, for P-side split capacitor array high-side DAC PH Is switched to Gnd and the N-terminal split capacitor array high-stage DAC NH To Vaq to produce a voltage offset of 1/4 Vref;
step B3, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B2 N-3 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D N-2 And D N-3 Controlling together;
(1)D N-1 ＝1
case one: if D N-2 D N-3 =11, for P-side split capacitor array low-side DAC PL The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array low-side DAC PL Is switched to Gnd and the N-terminal split capacitor array low-stage DAC NL The bottom plate of the highest capacitor is switched to Gnd to generate a voltage offset of 1/8 Vref;
and a third case: if D N-2 D N-3 For P-side split capacitor array, the bottom plates are all switched to Vaq, while N-side split capacitor array high-side DAC NH To Vref to produce a voltage offset of-1/8 Vref;
case four: if D N-2 D N-3 =00, for P-side split capacitor array high-side DAC PH The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/8 Vref;
(2)D N-1 ＝0
case one: if D N-2 D N-3 =11, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array high-side DAC NH To Vaq to produce a voltage offset of 1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array high-side DAC PH The bottom plates of the N-terminal split capacitor array are all switched to Vref and the bottom plates of the N-terminal split capacitor array are all switched to Vaq to produce a voltage offset of-1/8 Vref;
and a third case: if D N-2 D N-3 =01, for P-side split capacitor array low-side DAC PL The bottom plate of the highest capacitor is switched to Gnd, and the N-terminal split capacitor array low-stage DAC NL To Gnd to produce a voltage offset of 1/8 Vref;
case four: if D N-2 D N-3 =00, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array low-stage DAC PL To Vaq to produce a voltage offset of-1/8 Vref;
step B4, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B3 N-4 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D N-4 Monotone switching control is carried out;
(1)D N-2 D N-3 =11, 10 or 00
Case one: if D N-4 =1, for P-side split capacitor array high-side DAC PH The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-4 =0, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Gnd to Vaq, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/16 Vref;
(2)D N-2 D N-3 ＝01
case one: if D N-4 =1, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-4 =0 for the P-side split capacitor arrayThe bottom plate of the capacitor array is kept unchanged, and the N-terminal split capacitor array is low-stage DAC PL The bottom plate of the highest capacitor switches from Vaq to Gnd to produce a voltage offset of 1/16 Vref;
step B5, the next quantization procedure sequentially switches the capacitances in the capacitor array as described in step B4 until switch C 2 Obtaining LSB bit comparison result D 0 Final output D N-1 ,D N-2 …D 1 ,D 0 N-bit digital codes of (c).
The beneficial effects are that: by adopting the technical scheme, the invention can produce the following technical effects:
1. the capacitor array switching method of the low-power SAR ADC provided by the invention can realize high-energy-efficiency capacitor array switching method by adopting a Vaq switching technology and combining a split capacitor technology and a monotonic switching technology. The switching algorithm is more efficient and flexible, and meanwhile, 87.5% of capacitance area saving is achieved.
2. On the premise of introducing a third reference level Vaq =1/4 Vref, the invention also refers to a monotonic switching technology, and saves the power consumption generated during the switching of each bit of capacitor. The invention does not generate switching power consumption in the first three-bit comparison process, and the switching power consumption is further reduced in the subsequent switching process due to the third level Vaq =1/4 Vref.
3. Compared with the traditional switching algorithm, under the condition that the differential input signal ranges are the same, the capacitor array of the capacitor area SAR ADC and the switching method based on Vaq switching can be saved, 87.5% of capacitor area and 99.82% of switching power consumption can be saved, and the economic benefit is improved;
drawings
Fig. 1 is a schematic diagram of a single SAR ADC employed in the method of the present invention to achieve N-bit resolution.
Fig. 2 is a schematic diagram of the switching of the method of the present invention applied to a 5-bit SAR ADC.
Fig. 3 is a MATLAB simulation result diagram of the switching energy consumption of the 10-bit SAR ADC according to the change of the output code of the ADC.
Table 1 is a table corresponding to the third switching operation principle of the method of the present invention.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings.
The invention designs a high-energy-efficiency SAR ADC capacitor array switching method capable of simultaneously saving the capacitor area, wherein a capacitor array based on the method adopts two identical split capacitor structures, and simultaneously a Vaq =1/4 Vref third level is introduced to assist the switching of the capacitor array, and the capacitor array switching method comprises a sampling switch, a capacitor array, a comparator and digital control logic; the input signal Vip is connected to the P-terminal split capacitor array high-stage DAC through a sampling switch PH And low-stage DAC PL Is connected to the upper stage DAC of the N-terminal split capacitor array through the sampling switch NH And low-stage DAC NL A top plate of (2); the top polar plate of the P-end capacitor array is connected with the non-inverting input end of the comparator, and the top polar plate of the N-end capacitor array is connected with the inverting input end of the comparator; the differential output end of the comparator generates a control signal to control the bottom plate switches of the P end and the N end capacitor arrays after the digital control logic, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding reference voltages.
The P-end split capacitor arrays comprise a high-section capacitor array DAC PH And low-stage DAC PL The structures of the two sections of capacitor arrays are identical, the structure of the N-terminal split capacitor array is identical to the structure of the P-terminal, and the sizes of the capacitors of each section are as follows:
C i ＝2 i-2 c, wherein i is more than or equal to 2 and less than or equal to N-3;
C 1 ＝C 2 =c, where C is the unit capacitance size;
the method comprises the steps of comparing input signals Vip and Vin for N times to obtain an N-bit digital output code, wherein the N-bit digital output code is divided into two stages of sampling and conversion, and the method specifically comprises the following steps:
step A, sampling stage
Input signals Vip and Vin are respectively connected to the high-stage DAC of the P-end split capacitor array through sampling switches PH And low-stage DAC PL Top pole plate and N-terminal split capacitor array high-stage DAC (digital-to-analog converter) NH And low-stage DAC NL High Duan Dianrong array DAC PH And DAC NH The bottom electrode plates of all the capacitors in the capacitor array DAC are connected to the Vref reference voltage PL And DAC NL The bottom plates of all of the capacitors in (a) are connected to Gnd.
Step B, transition stage
Step B1, the sampling switch is disconnected, and the comparator directly compares MSB bits of input signals Vip and Vin which are kept on the top polar plates of the P end capacitor array and the N end capacitor array respectively to obtain a digital code D N-1 According to the digital code D N-1 Controlling the connection relation of the bottom electrode plates of the capacitors in the P-end capacitor array and the N-end capacitor array;
case one: if D N-1 =1, for P-side split capacitor array high-side DAC PH And N-terminal split capacitor array low-stage DAC NL Simultaneously switching to Vaq to produce a voltage offset of-1/2 Vref;
and a second case: if D N-1 =0, for P-side split capacitor array low-side DAC PL And N-terminal split capacitor array high-stage DAC NH Simultaneously switching to Vaq to produce a voltage offset of 1/2 Vref;
step B2, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B1 N-2 According to the digital code D N-2 Controlling and controlling the connection relation of the capacitor bottom plates in the P-end and N-end capacitor arrays;
case one: if D N-2 =1, for P-side split capacitor array low-side DAC PL Is switched to Vaq and the N-terminal split capacitor array low-stage DAC NL To Vref to produce a voltage offset of-1/4 Vref;
and a second case: if D N-2 =0, for P-side split capacitor array high-side DAC PH Is switched to Gnd and the N-terminal split capacitor array high-stage DAC NH To Vaq to produce a voltage offset of 1/4 Vref.
Step B3, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B2 N-3 Subsequent P-terminal and N-terminal capacitor arraysThe connection relation of the bottom-containing polar plates needs to be according to the digital code D N-2 And D N-3 Controlling together;
(1)D N-1 ＝1
case one: if D N-2 D N-3 =11, for P-side split capacitor array low-side DAC PL The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array low-side DAC PL Is switched to Gnd and the N-terminal split capacitor array low-stage DAC NL The bottom plate of the highest capacitor is switched to Gnd to generate a voltage offset of 1/8 Vref;
and a third case: if D N-2 D N-3 For P-side split capacitor array, the bottom plates are all switched to Vaq, while N-side split capacitor array high-side DAC NH To Vref to produce a voltage offset of-1/8 Vref;
case four: if D N-2 D N-3 =00, for P-side split capacitor array high-side DAC PH The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/8 Vref;
(2)D N-1 ＝0
case one: if D N-2 D N-3 =11, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array high-side DAC NH To Vaq to produce a voltage offset of 1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array high-side DAC PH The bottom plates of the N-terminal split capacitor array are all switched to Vref and the bottom plates of the N-terminal split capacitor array are all switched to Vaq to produce a voltage offset of-1/8 Vref;
and a third case: if D N-2 D N-3 =01, for P-side split capacitor array low-side DAC PL The bottom plate of the highest capacitor is switched to Gnd, and the N-terminal split capacitor array low-stage DAC NL Is switched to Gnd to produce a voltage offset of 1/8Vref；
Case four: if D N-2 D N-3 =00, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array low-stage DAC PL To Vaq to produce a voltage offset of-1/8 Vref.
Step B4, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B3 N-4 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D N-4 Monotone switching control is carried out;
(1)D N-2 D N-3 ＝11，10，00
case one: if D N-4 =1, for P-side split capacitor array high-side DAC PH The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-2 =0, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Gnd to Vaq, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/16 Vref;
(2)D N-2 D N-3 ＝01
case one: if D N-4 =1, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-2 =0, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array low-stage DAC PL The bottom plate of the highest capacitor switches from Vaq to Gnd to produce a voltage offset of 1/16 Vref;
step B5, the next quantization procedure sequentially switches the capacitances in the capacitor array as described in step B4 until switch C 2 Obtaining LSB bit comparison result D 0 Final output D N-1 ,D N-2 …D 1 ,D 0 N-bit digital codes of (c).
Therefore, the differential output end of the comparator of the method generates a control signal to control the bottom plate switch of the upper capacitor array and the lower capacitor array after the digital control logic, so that the bottom plate is connected to the corresponding reference voltage. The power consumption of the DAC part in the conversion process can be greatly reduced by specially constructing the core module capacitor array and combining the novel switching algorithm.
The invention will be described in detail with reference to one embodiment, since D 4 =1 and D 4 In both cases=0, the process of quantizing the poke-capacitance of MSB-1 to LSB bits is completely symmetrical, assuming D to avoid descriptive redundancy 4 Fig. 2 shows a specific conversion process of a 5bit SAR ADC according to an embodiment of the invention:
step A, sampling stage
Input signals Vip and Vin are respectively connected to the high-stage DAC of the P-end split capacitor array through sampling switches PH And low-stage DAC PL Top pole plate and N-terminal split capacitor array high-stage DAC (digital-to-analog converter) NH And low-stage DAC NL High Duan Dianrong array DAC PH And DAC NH The bottom electrode plates of all the capacitors in the capacitor array DAC are connected to the Vref reference voltage PL And DAC NL The bottom plates of all of the capacitors in (a) are connected to Gnd;
step B, transition stage
Step B1, the sampling switch is disconnected, and the comparator directly compares MSB bits of input signals Vip and Vin which are kept on the top polar plates of the P end capacitor array and the N end capacitor array respectively to obtain a digital code D 4 Because of D 4 =1, for P-side split capacitor array high-side DAC PH And N-terminal split capacitor array low-stage DAC NL The simultaneous switching of the bottom plates of (2) to Vaq produces a voltage offset of-1/2 Vref providing a voltage value for MSB-1 bit comparison.
Step B2, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B1 3 According to the digital code D 3 Controlling and controlling the connection relation of the capacitor bottom plates in the P-end and N-end capacitor arrays;
case one: if it isD 3 =1, for P-side split capacitor array low-side DAC PL Is switched to Vaq and the N-terminal split capacitor array low-stage DAC NL To Vref to produce a voltage offset of-1/4 Vref;
and a second case: if D 3 =0, for P-side split capacitor array high-side DAC PH Is switched to Gnd and the N-terminal split capacitor array high-stage DAC NH To Vaq to produce a voltage offset of 1/4 Vref.
Step B3, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B2 2 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D 2 And D 3 Controlling together;
case one: if D 2 D 3 =11, for P-side split capacitor array low-side DAC PL The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/8 Vref;
and a second case: if D 2 D 3 =10, for P-side split capacitor array low-side DAC PL Is switched to Gnd and the N-terminal split capacitor array low-stage DAC NL The bottom plate of the highest capacitor is switched to Gnd to generate a voltage offset of 1/8 Vref;
and a third case: if D 2 D 3 For P-side split capacitor array, the bottom plates are all switched to Vaq, while N-side split capacitor array high-side DAC NH To Vref to produce a voltage offset of-1/8 Vref;
case four: if D 2 D 3 =00, for P-side split capacitor array high-side DAC PH The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/8 Vref.
Similarly, when D 4 The switching cases when=0 are summarized in table 1.
Step B4, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B3 1 Next, the process is carried outThe connection relation between the P end and the N end capacitor bottom polar plate in the capacitor array is required according to the digital code D 1 Monotone switching control is carried out;
(1)D 2 D 3 =11, 10 or 00
Case one: if D 1 =1, for P-side split capacitor array high-side DAC PH The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D 1 =0, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Gnd to Vaq, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/16 Vref;
(2)D 2 D 3 ＝01
case one: if D 1 =1, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D 1 =0, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array low-stage DAC PL The bottom plate of the highest capacitor switches from Vaq to Gnd to produce a voltage offset of 1/16 Vref;
step B5, the next quantization procedure sequentially switches the capacitances in the capacitor array as described in step B4 until switch C 2 Obtaining LSB bit comparison result D 0 Final output D 0 ,D 1 …D 3 ,D 4 Is a 5-bit digital code.
In summary, the method of the invention further reduces the switching power consumption of the capacitor DAC by adopting the split capacitor technology and combining the monotonic switching technology on the premise of introducing the third reference level Vaq =1/4 Vref.
Table 1 is a table corresponding to the third switching operation principle of the method of the present invention.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.
TABLE 1
* Representing the connection voltage remaining unchanged
Claims (2)
1. The capacitor array switching method of the SAR ADC with high energy efficiency is characterized in that the capacitor array based on the method adopts two groups of identical capacitor structures, and simultaneously introduces a third level of Vaq =1/4 Vref to assist the switching of the capacitor array, and comprises a sampling switch, a capacitor array, a comparator and digital control logic; the first input signal Vip is connected to the P-terminal split capacitor array high-stage DAC through a sampling switch PH And low-stage DAC PL Is connected to the top plate of the N-terminal split capacitor array high-side DAC by a sampling switch NH And low-stage DAC NL A top plate of (2); the top polar plate of the P-end capacitor array is connected with the non-inverting input end of the comparator, and the top polar plate of the N-end capacitor array is connected with the inverting input end of the comparator; the differential output end of the comparator generates a control signal to control the bottom plate switches of the P end and the N end capacitor arrays after digital control logic, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding reference voltages;
the first input signal Vip and the second input signal Vin are compared N times to obtain an N-bit digital output code, and the N-bit digital output code is divided into two stages of sampling and conversion, and specifically comprises the following steps:
step A, sampling stage
The first input signal Vip and the second input signal Vin are respectively connected to the high-stage DAC of the P-end split capacitor array through sampling switches PH And low-stage DAC PL Top pole plate and N-terminal split capacitor array high-stage DAC (digital-to-analog converter) NH And low-stage DAC NL High Duan Dianrong array DAC PH And DAC NH The bottom plates of all of the capacitors in (a) are connected to the Vref referenceVoltage, low-stage capacitor array DAC PL And DAC NL The bottom plates of all of the capacitors in (a) are connected to Gnd;
step B, transition stage
Step B1, the sampling switch is disconnected, and the comparator directly compares the MSB highest bits of the input signals Vip and Vin which are kept on the top polar plates of the P end and the N end capacitor array respectively to obtain a digital code D N-1 According to the digital code D N-1 Controlling the connection relation of the bottom electrode plates of the capacitors in the P-end capacitor array and the N-end capacitor array;
case one: if D N-1 =1, for P-side split capacitor array high-side DAC PH And N-terminal split capacitor array low-stage DAC NL Simultaneously switching to Vaq to produce a voltage offset of-1/2 Vref;
and a second case: if D N-1 =0, for P-side split capacitor array low-side DAC PL And N-terminal split capacitor array high-stage DAC NH Simultaneously switching to Vaq to produce a voltage offset of 1/2 Vref;
step B2, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B1 N-2 According to the digital code D N-2 Controlling and controlling the connection relation of the capacitor bottom plates in the P-end and N-end capacitor arrays;
case one: if D N-2 =1, for P-side split capacitor array low-side DAC PL Is switched to Vaq and the N-terminal split capacitor array low-stage DAC NL To Vref to produce a voltage offset of-1/4 Vref;
and a second case: if D N-2 =0, for P-side split capacitor array high-side DAC PH Is switched to Gnd and the N-terminal split capacitor array high-stage DAC NH To Vaq to produce a voltage offset of 1/4 Vref;
step B3, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B2 N-3 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D N-2 And D N-3 Controlling together;
(1)D N-1 ＝1
case one: if D N-2 D N-3 =11, for P-side split capacitor array low-side DAC PL The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array low-side DAC PL Is switched to Gnd and the N-terminal split capacitor array low-stage DAC NL The bottom plate of the highest capacitor is switched to Gnd to generate a voltage offset of 1/8 Vref;
and a third case: if D N-2 D N-3 For P-side split capacitor array, the bottom plates are all switched to Vaq, while N-side split capacitor array high-side DAC NH To Vref to produce a voltage offset of-1/8 Vref;
case four: if D N-2 D N-3 =00, for P-side split capacitor array high-side DAC PH The bottom plate of the N-terminal split capacitor array is switched to Vaq while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/8 Vref;
(2)D N-1 ＝0
case one: if D N-2 D N-3 =11, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array high-side DAC NH To Vaq to produce a voltage offset of 1/8 Vref;
and a second case: if D N-2 D N-3 =10, for P-side split capacitor array high-side DAC PH The bottom plates of the N-terminal split capacitor array are all switched to Vref and the bottom plates of the N-terminal split capacitor array are all switched to Vaq to produce a voltage offset of-1/8 Vref;
and a third case: if D N-2 D N-3 =01, for P-side split capacitor array low-side DAC PL The bottom plate of the highest capacitor is switched to Gnd, and the N-terminal split capacitor array low-stage DAC NL To Gnd to produce a voltage offset of 1/8 Vref;
case four: if D N-2 D N-3 =00, the bottom plate for the P-side split capacitor array remains unchanged, whileN-terminal split capacitor array low-stage DAC PL To Vaq to produce a voltage offset of-1/8 Vref;
step B4, the comparator obtains a digital code D by comparing the voltages of the top electrode plates of the P-end capacitor array and the N-end capacitor array obtained in the step B3 N-4 The connection relation of the bottom plates of the capacitors in the next P-end and N-end capacitor arrays needs to be according to the digital code D N-4 Monotone switching control is carried out;
(1)D N-2 D N-3 =11, 10 or 00
Case one: if D N-4 =1, for P-side split capacitor array high-side DAC PH The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-4 =0, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Gnd to Vaq, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of 1/16 Vref;
(2)D N-2 D N-3 ＝01
case one: if D N-4 =1, for P-side split capacitor array low-side DAC PL The bottom plate of the highest order capacitor is switched from Vaq to Gnd, while the bottom plate of the N-terminal split capacitor array remains unchanged to produce a voltage offset of-1/16 Vref;
and a second case: if D N-4 =0, the bottom plate for the P-side split capacitor array remains unchanged, while the N-side split capacitor array low-stage DAC PL The bottom plate of the highest capacitor switches from Vaq to Gnd to produce a voltage offset of 1/16 Vref;
step B5, the next quantization procedure sequentially switches the capacitances in the capacitor array as described in step B4 until switch C 2 Obtaining LSB bit comparison result D 0 Final output D N-1 ,D N-2 …D 1 ,D 0 N-bit digital codes of (c).
2. The method for switching a capacitor array of an energy efficient SAR ADC of claim 1, whereinThe P-end split capacitor arrays comprise a high-stage capacitor array DAC PH And low-stage DAC PL The structures of the two sections of capacitor arrays are identical, the structure of the N-terminal split capacitor array is identical to the structure of the P-terminal, and the sizes of the capacitors of each section are as follows: c (C) i ＝2 i-2 C, wherein i is more than or equal to 2 and less than or equal to N-3, and capacitance C 1 ＝C 2 C, where C is the unit capacitance size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010733531.7A CN111641413B (en) | 2020-07-27 | 2020-07-27 | Capacitor array switching method of high-energy-efficiency SAR ADC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010733531.7A CN111641413B (en) | 2020-07-27 | 2020-07-27 | Capacitor array switching method of high-energy-efficiency SAR ADC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111641413A CN111641413A (en) | 2020-09-08 |
| CN111641413B true CN111641413B (en) | 2023-06-06 |
Family
ID=72332682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010733531.7A Active CN111641413B (en) | 2020-07-27 | 2020-07-27 | Capacitor array switching method of high-energy-efficiency SAR ADC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111641413B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112332846B (en) * | 2020-11-05 | 2022-11-08 | 东南大学 | Low-voltage SAR ADC switch switching method based on charge recovery |
| CN112583409B (en) * | 2020-12-28 | 2024-03-15 | 东南大学 | Successive approximation type analog-to-digital converter and three-level switching method thereof |
| CN114499533A (en) * | 2022-01-24 | 2022-05-13 | 福州大学 | Low-power-consumption capacitor array for sensor and switching method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105933007A (en) * | 2016-04-14 | 2016-09-07 | 西安电子科技大学昆山创新研究院 | Successive approximation type analog to digital converter and switching sequence thereof |
| CN111371457A (en) * | 2020-03-12 | 2020-07-03 | 东南大学 | Analog-to-digital converter and three-level switching method applied to SAR ADC |
-
2020
- 2020-07-27 CN CN202010733531.7A patent/CN111641413B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105933007A (en) * | 2016-04-14 | 2016-09-07 | 西安电子科技大学昆山创新研究院 | Successive approximation type analog to digital converter and switching sequence thereof |
| CN111371457A (en) * | 2020-03-12 | 2020-07-03 | 东南大学 | Analog-to-digital converter and three-level switching method applied to SAR ADC |
Non-Patent Citations (2)
| Title |
|---|
| Chun-Cheng Liu等."A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure".《IEEE JOURNAL OF SOLID-STATE CIRCUITS》.2010,第45卷(第4期),全文. * |
| 倪亚波等."一种新型的ＳＡＲ ＡＤＣ电容阵列混合转换方案".《微电子学》.2016,第46卷(第1期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111641413A (en) | 2020-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109039332B (en) | Successive approximation type analog-to-digital converter and low-power-consumption switching algorithm thereof | |
| CN111641413B (en) | Capacitor array switching method of high-energy-efficiency SAR ADC | |
| CN111371457B (en) | Analog-to-digital converter and three-level switching method applied to SAR ADC | |
| CN105391451A (en) | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof | |
| CN110380730B (en) | Capacitor array switching method applied to low-voltage SAR ADC | |
| CN112583409B (en) | Successive approximation type analog-to-digital converter and three-level switching method thereof | |
| US11418209B2 (en) | Signal conversion circuit utilizing switched capacitors | |
| CN111130550B (en) | Successive approximation register type analog-to-digital converter and signal conversion method thereof | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| CN110198169B (en) | Self-adaptive predictive low-power-consumption switching method suitable for SAR ADC | |
| CN112367084B (en) | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing | |
| CN111327324B (en) | Capacitor array structure suitable for successive approximation type analog-to-digital converter | |
| CN108880553B (en) | Low-power-consumption self-adaptive alternative successive approximation type analog-to-digital converter and control method | |
| KR20190071536A (en) | Successive approximation register analog digital converter and operating method thereof | |
| CN112332847B (en) | Two-level switching method applied to successive approximation type analog-to-digital converter | |
| CN112332846B (en) | Low-voltage SAR ADC switch switching method based on charge recovery | |
| CN112272027A (en) | Successive approximation analog-digital converter and capacitance switch switching method | |
| CN111585577A (en) | Capacitor array switching method for successive approximation type analog-to-digital converter | |
| CN112968704B (en) | Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode | |
| Wang et al. | Area-efficient capacitor-splitting switching scheme with a nearly constant common-mode voltage for SAR ADCs | |
| Liang et al. | Energy-efficient and area-saving asymmetric capacitor switching scheme for SAR ADCs | |
| CN109936370B (en) | Low-power-consumption switching algorithm applied to SAR ADC | |
| CN109660259B (en) | Successive approximation type analog-digital converter with constant output common mode voltage and switching method thereof | |
| WO2020228467A1 (en) | Error shaping circuit of analog-to-digital converter, and successive-approximation analog-to-digital converter | |
| CN109039338B (en) | Differential capacitor array and switch switching method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |