CN112968704B - Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode - Google Patents

Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode Download PDF

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CN112968704B
CN112968704B CN202110149181.4A CN202110149181A CN112968704B CN 112968704 B CN112968704 B CN 112968704B CN 202110149181 A CN202110149181 A CN 202110149181A CN 112968704 B CN112968704 B CN 112968704B
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capacitor
quantization
array
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capacitors
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CN112968704A (en
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宁宁
余先银
肖航
张中
李靖
于奇
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

Abstract

The invention belongs to the technical field of analog integrated circuits, and relates to a successive approximation type analog-to-digital converter based on a transient capacitance switching mode and a quantization method thereof. Based on the pole plate sampling technology, the invention directly carries out the first comparison after sampling, obtains the 1 st bit output code word according to the result of the first comparison, and then completes the capacitance switching in the second quantization process according to the result of the first comparison; and simultaneously, determining a target array required to be switched in a subsequent quantization process according to a result of the first comparison. In the subsequent quantization process, the transition is carried out by establishing an intermediate state, so that the capacitance switching in the target array is realized, the DAC capacitor array is formed in a manner similar to a single-ended capacitance switching manner, and the power consumption of the switched capacitor array is reduced; meanwhile, the N-bit quantization is performed by the N-2-bit quantization capacitor, so that the area is saved by 75% compared with the traditional DAC capacitor array, and the power consumption is reduced.

Description

Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a successive approximation type analog-to-digital converter based on a transient capacitance switching mode and a quantization method thereof.
Background
As a bridge for connecting an analog signal of the outside world and an internal signal of a system, an analog-to-digital converter (ADC) is widely used in the technical fields of multimedia, communication, biomedical, sensor control, and the like, and ADCs with different characteristics are suitable for different environments. In recent years, with the rapid development of portable, wearable, and implantable devices, in such device applications, the chip needs to operate in a state of ultra-low power consumption in the absence of a power supply or in a state of a relatively small power supply, so that it is important to reduce power consumption and volume.
The successive approximation type analog-to-digital converter (SAR ADC) has the advantages of simple structure, low power consumption, small area and the like, so that the SAR ADC is widely applied. For a successive approximation analog-to-digital converter (SAR ADC), its main power consumption comes from the capacitor array, the comparator and the SAR logic. With the development of CMOS process, the power consumption of digital circuit is further reduced, and for the adoption of fully dynamic comparator, the power consumption of comparator is mainly determined by noise and sampling rate, so the power consumption of capacitor array is the most main factor for determining the whole power consumption of sar adc converter.
The traditional switch capacitor of the traditional SAR ADC for realizing the successive approximation algorithm is mainly used for binary division of total charges stored in a capacitor array in a mode of attenuating reference voltage by a capacitor. In the traditional SAR ADC quantization method, the main advantage of the DAC module switching strategy is that the working principle is simple, but as the digit of the analog-digital converter increases, the capacitance value increases exponentially due to the binary weighting mode, and an N digit difference fractional-analog converter needs 2 N Unit capacitance. The occupied circuit area is increased, and the power consumption generated by capacitance switching is rapidly increased.
Disclosure of Invention
The invention aims to: a successive approximation type analog-to-digital converter based on a transient capacitance switching mode and a quantization method thereof are provided to overcome the problem that in the quantization process of a traditional successive approximation type analog-to-digital converter (SAR ADC), the analog converter needs 2 N The unit capacitor causes the problem that the occupied circuit area is increased, and the power consumption generated by capacitor switching is rapidly increased.
In order to achieve the purpose, the invention adopts the following technical scheme:
a successive approximation type analog-to-digital converter based on a transient capacitance switching mode comprises the following components: DAC module, comparator and digital logic control module.
The DAC module comprises a first DAC capacitor array and a second DAC capacitor array, the first DAC capacitor array and the second DAC capacitor array both comprise N-2 binary quantization capacitors and 1 redundant capacitor, and N is the bit number of the successive approximation type analog-to-digital converter; the N-2 quantized capacitors are arranged in order of weight from low to high and are numbered C 1 、C 2 、C 3 、……、C N-2 (ii) a Redundant capacitor C R1 And a quantization capacitor C 1 Are equal; the upper plates of N-2 quantization capacitors and 1 redundant capacitor in the first DAC capacitor array are connected A positive input terminal of the comparator is connected with an input signal V through a switch ip The lower pole plate is connected with a common mode voltage or a reference high voltage or a reference ground voltage after passing through the corresponding N-1 switches respectively, so that each capacitor realizes capacitor switching through the respective switch; the upper polar plates of N-2 quantization capacitors and 1 redundant capacitor in the second DAC capacitor array are connected with the negative input end of the comparator and are connected with an input signal V through a switch in The lower pole plate is connected with a common mode voltage or a reference high voltage or a reference ground voltage after passing through the corresponding N-1 switches respectively, so that each capacitor realizes capacitor switching through the respective switch. The voltage value of the common mode voltage is one half of the voltage value of the reference high voltage.
The output end of the comparator is respectively connected with the input end of the output module and the input end of the digital logic control module; and the output module finishes the output of the quantized code words according to the output signal provided by the comparator.
And the digital logic control module generates a control signal according to the received output signal of the comparator, and controls the capacitance switching in the capacitor array in the DAC module to realize quantization through the control signal.
Another aspect of the present invention is to adapt to the improvement of the structure of the successive approximation analog-to-digital converter, and provides a quantization method for a successive approximation analog-to-digital converter based on a transient capacitance switching manner, including the following steps:
Step one, sampling stage
(1) The successive approximation type analog-to-digital converter is electrified and reset, the DAC module carries out sampling, and the upper electrode plates of N-2 quantization capacitors and 1 redundant capacitor in the first DAC capacitor array are connected with an input signal V ip The lower plates of the two DAC capacitor arrays are connected with a reference ground voltage, and the upper plates of the N-2 quantization capacitors and the 1 redundant capacitor in the second DAC capacitor array are connected with an input signal V in And the lower polar plates are connected with a reference ground voltage.
(2) After the DAC module finishes sampling, the upper polar plates of all the quantization capacitors and the redundant capacitors are disconnected with the input signal, and the lower polar plate is kept connected with a reference ground voltage; then entering a comparison stage;
step two, a comparison stage: sequentially determining the highest bit output code to the lowest bit output code of the successive approximation type analog-to-digital converter through N times of comparison, and completing the quantization of the DAC capacitor array;
in the first N-1 comparisons, the method for performing the 1 st comparison is as follows: comparing the input signal of positive input end with the input signal of negative input end to obtain the 1 st comparison result d 1 (ii) a According to the 1 st comparison result d 1 Switching all capacitors in the first DAC capacitor array or the second AC capacitor array to a common-mode voltage, and simultaneously keeping the other DAC capacitor array connected with a reference ground voltage and not switching any more in a later quantization process; for convenience of description, we refer to the need to switch a set of DAC capacitor arrays as the target array.
The method for performing the ith comparison is as follows: firstly, the input signal of positive input end and input signal of negative input end of comparator are compared, and the ith comparison result d is obtained i (ii) a Re-comparison d 1 And d 2 、d i And d 1 Then d is 1 And d 2 Comparison result of (d) i And d 1 The comparison results are combined to be used as the basis of capacitance switching in the quantization process of the (i + 1) th time to complete the capacitance switching in the quantization process of the (i + 1) th time, i belongs to [2, N-2 ]]。
The method for the N-1 th comparison and the Nth comparison comprises the following steps: comparing the input signal of the positive input end with the input signal of the negative input end of the comparator, obtaining the N-1 th comparison result, and switching the redundant capacitor C in the target array according to the N-1 th comparison result R1 And obtaining the Nth comparison result. And then outputting the N comparison results as N-bit output codes of the successive approximation type analog-to-digital converter, and finishing the quantization.
Further, after the ith comparison in the second step, d is used 1 And d 2 In combination with the comparison result of (d) i And d 1 And according to the comparison result, completing the capacitance switching in the (i + 1) th quantization process according to the following conditions:
when d is 1 And d 2 Is different and d i Is not equal to d 1 When the target array is in the order of C N-i Quantization powerThe capacitor is switched from the common mode voltage to the reference ground voltage.
When d is 1 And d 2 Is different and d i Is equal to d 1 All the capacitors in the target array are switched to an intermediate state for transition. The intermediate states at this time are: and all capacitors with lower plates connected with the reference ground voltage in one state on the target array are switched to the common mode voltage, and the capacitors with lower plates connected with the common mode voltage are switched to the reference high voltage. After the intermediate state is established, the C-th in the target array is set N-i The lower plate of the quantization capacitor is switched to the reference ground voltage, C N-i-1 The lower plate of the quantized capacitor is switched to a common mode voltage, and the other bit capacitors maintain the last target array state.
When d is 1 And d 2 Same and d i Is not equal to d 1 All capacitances in the target array are switched to an intermediate state transition. The intermediate states at this time are: c in the target array N-i The lower plate of the quantization capacitor is connected with a common mode voltage, C N-i-1 The lower plate of the quantization capacitor is connected with a reference ground voltage, and the other high-order quantization capacitor (C) N-2 -C N-i-2 ) The state is determined by the last target array state; the capacitor with the lower polar plate connected with the common mode voltage in the target array is switched to a reference ground voltage, and the capacitor with the lower polar plate connected with the reference high voltage is switched to the common mode voltage; the other bit capacitors are connected to a reference ground voltage. After the intermediate state is established, the capacitor of the lower polar plate connected with the reference ground voltage in the target array is switched to the common mode voltage, and the capacitor of the lower polar plate connected with the common mode voltage is switched to the reference high voltage.
When d is 1 And d 2 Same and d i Is equal to d 1 All capacitances in the target array are switched to an intermediate state transition. The intermediate states at this time are: c in the target array N-i The lower plate of each quantization capacitor is connected with a common-mode voltage and other high-order capacitors (C) N-2 -C N-i-1 ) The state is determined by the last target array state; the capacitor with the lower polar plate connected with the common mode voltage in the target array is switched to a reference ground voltage, and the capacitor with the lower polar plate connected with the reference high voltage is switched to the common mode voltage; the other bit capacitors are connected to a reference ground voltage. After the intermediate state is established, the target array is arrangedThe capacitor with the lower polar plate connected with the reference ground voltage is switched to the common mode voltage, and the capacitor with the lower polar plate connected with the common mode voltage is switched to the reference high voltage.
The invention has the beneficial effects that: the invention is based on the upper polar plate sampling technology, directly carries out the first comparison after sampling, establishes an intermediate state for transition in the quantization process, and reduces the power consumption of the switched capacitor array. In addition, the last codeword is obtained by switching only the lowest bit capacitance comparison of the P-side or N-side in a manner similar to single-ended switching of capacitance. The invention carries out N-bit quantization by using the N-2-bit quantization capacitor, saves 75% of area compared with the traditional DAC capacitor array, and reduces power consumption.
Drawings
FIG. 1 is a system diagram of a successive approximation analog-to-digital converter according to the present invention;
FIG. 2 is a diagram illustrating the quantization capacitors and the redundancy capacitors of the capacitor array in the successive approximation type ADC according to the present invention;
FIG. 3 is a diagram illustrating a capacitor array in an embodiment of a successive approximation analog-to-digital converter quantization method according to the present invention;
reference numerals:
11. a DAC module; 12. a comparator; 13. an output module; 14. and a digital logic control module.
Detailed Description
The technical scheme of the invention is detailed below by combining the accompanying drawings and the embodiment.
Fig. 1 is a block diagram of a successive approximation type analog-to-digital converter system according to the present invention. As shown in fig. 1, the digital-to-analog converter includes a DAC module 11, a comparator module 12, a digital logic control module 13, and an output module 14. The DAC module 11 is configured to sample an input signal, and an output end of the DAC module is connected to an input end of the comparator module 12; the comparison result of the comparator 12 is connected on the one hand to the digital control logic module 13 and on the other hand to the output module 14; the digital logic control module 13 generates a control signal according to the output signal of the comparator 12, and controls the capacitance switching in the DAC capacitor array in the DAC module 11 through the control signal; the output module 14 outputs the quantized codeword D <1: N > according to the output signal of the comparator 12.
As shown in FIG. 2, the input signal of the DAC module is a differential input signal V ip And V in The DAC module comprises a first DAC capacitor array and a second DAC capacitor array, the first DAC capacitor array and the second DAC capacitor array both comprise N-2 binary quantization capacitors and 1 redundant capacitor, and N is the bit number of the successive approximation type analog-to-digital converter; the N-2 quantized capacitors are arranged in order of weight from low to high and are numbered C 1 、C 2 、C 3 、……、C N-2 (ii) a Redundant capacitor C R1 And a quantization capacitor C 1 Are equal in capacitance value and the redundant capacitor C R1 Connected to DAC capacitor array quantization capacitor C 1 And then.
N-2 quantization capacitors C in the first DAC capacitor array 1 To C N-2 And 1 redundant capacitor C R1 The upper pole plates of the two-way switch are connected with the positive input end (namely the P end) of the comparator and are connected with an input signal V through the switch ip The lower polar plate is respectively connected with a common-mode voltage V after passing through corresponding N-1 switches CM Or with reference to a high voltage V REF Or the reference ground voltage gnd. N-2 quantization capacitors C in the second DAC capacitor array 1 To C N-2 And 1 redundant capacitor C R1 The upper polar plates of the two-way switch are all connected with the negative input end (namely N end) of the comparator and are connected with an input signal V through the switch in The lower pole plate is connected with a common-mode voltage VCM or a reference high voltage V after passing through corresponding N-1 switches respectively REF Or the reference ground voltage gnd. The voltage value of the common mode voltage is one half of the voltage value of the reference high voltage.
According to another aspect of the present invention, a quantization method associated with the successive approximation type analog-to-digital converter with the above structure is provided, which includes the following steps:
step one, sampling stage
(1) The successive approximation type analog-to-digital converter is electrified and reset, the DAC module 11 carries out sampling, and the upper electrode plates of N-2 quantization capacitors and 1 redundant capacitor (namely P end) in the first DAC capacitor array are connected with an input signal V ip The lower plates of the two DAC capacitors are connected to a reference ground voltage gnd, and N-2 quantization capacitors and 1 redundancy capacitor in the second DAC capacitor array (i.e. N terminal)The upper polar plates of the capacitors are all connected with an input signal V in And the lower plates thereof are both connected with a reference ground voltage gnd.
(2) After sampling by the DAC module 11, disconnecting the upper electrode plates of all the quantization capacitors and the redundant capacitors from the differential signals, and keeping the lower electrode plates connected with the reference ground voltage gnd; and then step two is entered.
Step two, a comparison stage: and sequentially determining the highest bit output code to the lowest bit output code of the successive approximation type analog-to-digital converter through N times of comparison, and completing the quantization of the DAC capacitor array.
In the first N-1 comparisons, the method for performing the 1 st comparison is as follows: comparing the input signals of the positive input terminal (P terminal) and the negative input terminal (N terminal) of the comparator 12 to obtain the 1 st comparison result d 1 (ii) a According to the 1 st comparison result d 1 And determining one group of DAC capacitor arrays as a target array for capacitor switching in the quantization process of the invention, and simultaneously keeping the other group of DAC capacitor arrays connected with the reference ground voltage gnd and not switching any more in the subsequent quantization process. And switching all the capacitors in the target array to the common-mode voltage VCM according to the 1 st comparison result to finish the capacitor switching in the second quantization process.
A second comparison is then made. In the second comparison, the input signals of the positive input terminal (i.e., P terminal) and the negative input terminal (i.e., N terminal) of the comparator 12 are compared to obtain a second comparison result d 2 Then compare d again 1 And d 2 Then by d 1 And d 2 The comparison result is used as the basis of the capacitance switching of the target array in the third quantization process, and the capacitance switching in the third quantization process is completed.
A third comparison is then made. In the third comparison, the input signals of the positive input terminal (i.e., P terminal) and the negative input terminal (i.e., N terminal) of the comparator 12 are compared to obtain a third comparison result d 3 Then compare d again 1 And d 2 、d 3 And d 1 Then d is 1 And d 2 Comparison result of (d) 3 And d 1 The comparison results are combined to be used as the basis of capacitance switching in the fourth target array, and the fourth quantization process is completed The capacitance of (2) is switched.
And then a fourth comparison, … …. According to the method, the target array redundant capacitor C is switched according to the N-1 comparison result until the N-1 comparison result is obtained R1 Obtaining the Nth comparison result as d N And finishing the quantization. N comparison results d 1 d 2 d 3 ……d N Constituting the final output code.
Therefore, the quantization method provided by the invention can realize N-2 bit binary switch quantization capacitor array to obtain N bit output codes and complete analog-to-digital conversion.
Further, in the ith comparison method performed in the second step, d is used 1 And d 2 In combination with the comparison result of (d) i And d 1 And according to the comparison result, completing the capacitance switching in the (i + 1) th quantization process according to the following conditions:
when d is 1 And d 2 Is different and d i Is not equal to d 1 When the target array is in the order of C N-i The quantization capacitor is composed of a common-mode voltage V CM Switching to the reference ground voltage gnd.
When d is 1 And d 2 Is different and d i Is equal to d 1 All the capacitors in the target array are switched to an intermediate state for transition. The intermediate states at this time are: the capacitors of all the lower plates in one state on the target array connected to the reference ground voltage gnd are switched to the common mode voltage V CM The lower polar plate is connected with a common mode voltage V CM Is switched to a reference high voltage V REF . After the intermediate state establishment is completed, the C-th element in the target array is set N-i The lower plate of the quantization capacitor is switched to the reference ground voltage gnd, C N-i-1 The lower plate of the quantified capacitor is switched to a common-mode voltage V CM The other bit capacitances hold the last target array state.
When d is 1 And d 2 Same and d i Is not equal to d 1 All capacitances in the target array are switched to an intermediate state transition. The intermediate states at this time are: c in the target array N-i The lower electrode plate of the quantified capacitor is connected with a common-mode voltage V CM No. C N-i-1 The lower plate of the quantization capacitor is connected with a reference ground voltage gnd, and the other high-order quantization capacitor (C) N-2 -C N-i-2 ) The state is determined by the last target array state; the capacitor of the common-mode voltage connected with the lower polar plate in the target array is switched to the reference ground voltage gnd, and the reference high voltage V is connected with the lower polar plate REF Is switched to a common mode voltage V CM (ii) a The other bit capacitors are connected to the reference ground voltage gnd. After the intermediate state is established, the capacitor of the lower polar plate connected with the reference ground voltage gnd in the target array is switched to the common mode voltage V CM The lower polar plate is connected with a common mode voltage V CM Is switched to a reference high voltage V REF 。
When d is 1 And d 2 Same and d i Is equal to d 1 All capacitances in the target array are switched to an intermediate state transition. The intermediate states at this time are: c in the target array N-i The lower plate of the quantization capacitor is connected with a common mode voltage V CM Other high-order capacitors (C) N-2 -C N-i-1 ) The state is determined by the last target array state; common mode voltage V is connected to lower polar plate in target array CM The capacitor is switched to the reference ground voltage gnd, and the lower plate is connected to the reference high voltage V REF Is switched to a common mode voltage V CM (ii) a The other bit capacitors are connected to the reference ground voltage gnd. After the intermediate state is established, the capacitor of the lower polar plate connected with the reference ground voltage gnd in the target array is switched to the common mode voltage V CM The lower polar plate is connected with a common mode voltage V CM Is switched to a reference high voltage V REF 。
Further, the determination method of the target array is as follows: when the first comparison result d 1 Indicating that the comparator has a positive input signal greater than its negative input signal, i.e. d 1 When the voltage is equal to 1, the lower plate of the second DAC capacitor array (N terminal) is switched from the reference ground voltage gnd to the common mode voltage V CM And as the target array. When the first comparison result d 1 Indicating that the comparator has a positive input signal greater than its negative input signal, i.e. d 1 When the voltage is equal to 0, the lower plate of the first DAC capacitor array (P terminal) is switched from the reference ground voltage gnd to the common mode voltage V CM And as the target array.
Examples
The following describes an embodiment of the present invention in detail by taking a 4-bit successive approximation type analog-to-digital converter as an example. In the embodiment, the first and second DAC capacitor arrays each include 2 quantization capacitors and 1 redundancy capacitor C R1 And 2 quantized capacitors are numbered C in the order of weight from low to high 1 、C 2 Redundant capacitance C R1 And a quantization capacitor C 1 Are equal. Redundant capacitance is in turn C R1 Arranged at the quantization capacitor C 1 And then.
2 quantisation capacitances C in a first DAC capacitor array 1 、C 2 And 1 redundant capacitor C R1 Connected with the positive input end (P end) of the comparator, and the upper polar plate thereof is connected with an input signal V after passing through the switch ip (ii) a The lower polar plates are respectively connected with a common mode voltage V through a switch array CM Or with reference to a high voltage V REF Or the reference ground voltage gnd. 2 quantisation capacitances C in a second DAC capacitor array 1 C and 1 redundant capacitor C R1 Connected with the negative input end (N end) of the comparator, and the upper polar plate of the comparator is connected with an input signal V after passing through the switch in (ii) a The lower polar plate is connected with a common mode voltage V through a switch array CM Or with reference to a high voltage V REF Or the reference ground voltage gnd. Common mode voltage V CM Is one-half of the voltage value of the reference high voltage.
The operation of the present embodiment using the quantization method of the present invention is described in detail below, and as shown in fig. 3, fig. 3 shows all the cases of the 4-bit ADC during quantization, and the middle state is marked by a dashed box in the figure.
Assume that the quantized codeword of the present embodiment is 1111.
Step one, a sampling stage;
the successive approximation type analog-to-digital converter is electrified and reset, and the DAC module performs sampling, and the specific method comprises the following steps: 2 quantization capacitors C in the first DAC capacitor array (i.e. P terminal) 1 、C 2 And 1 redundant capacitor C R1 All the upper polar plates are connected with an input signal V ip The lower polar plates are all connected with reference ground voltage gnd; 2 quantization capacitors C in the second DAC capacitor array (i.e. N terminal) 1 、C 2 And 1 redundant capacitor C R1 All the upper polar plates are connected with an input signal V in The lower polar plates are all connected with a reference ground voltage gnd;
(2) after sampling of the DAC module is finished, the upper polar plates of all capacitors on the two groups of DAC capacitor arrays are disconnected from the input signal, and the lower polar plates are kept connected with the reference ground voltage gnd. Then there are:
and (3) P terminal: v P1 ＝V ip
And (3) N terminal: v N1 ＝V in
To obtain V P1 -V N1 ＝V ip -V in The comparator compares for the first time to obtain a first comparison result d 1 ＝1。
Based on the result of the first comparison d 1 1, the P-end capacitor array is kept unchanged, the N-end capacitor array is a target array, and the lower plate of the target array is switched from the reference ground voltage Gnd to the common-mode voltage V CM Then, there are:
and (3) P terminal: v P2 ＝V ip
And (3) N terminal:
Figure GDA0003645656960000071
to obtain
Figure GDA0003645656960000072
Performing a second comparison to obtain a second comparison result d 2 ＝1。
Based on the comparison result d 1 ＝1，d 2 As 1, the intermediate state is: in the target array C 2 Lower polar plate keeps connecting V CM Constant, capacitance C 1 And a redundant capacitor C R1 The lower polar plate is controlled by a common mode voltage V CM Switching to a reference ground voltage Gnd; c in the target array after intermediate state transition 2 The lower polar plate is controlled by a common mode voltage V CM Switching to a reference high voltage V REF Capacitor C 1 And a redundant capacitor C R1 The lower polar plate is switched to a common mode voltage V from a reference ground voltage Gnd CM . Then there are:
and a P terminal: v P3 ＝V ip
And (3) N terminal:
Figure GDA0003645656960000073
to obtain
Figure GDA0003645656960000074
Performing a third comparison to obtain a third comparison result d 3 ＝1。
Based on the comparison result d 1 ＝1，d 2 1 and d 3 As 1, the intermediate state is: in the target array C 2 The lower polar plate is controlled by a reference high voltage V REF Switching to a common mode voltage V CM Capacitor C 1 The lower polar plate is kept connected with a common mode voltage V CM (ii) a Redundant capacitor C R1 The lower polar plate is controlled by a common mode voltage V CM Switching to a reference ground voltage Gnd; c in the target array after intermediate state transition 2 The lower polar plate is controlled by a common mode voltage V CM Switching to a reference high voltage V REF Capacitor C 1 The lower polar plate is controlled by a common mode voltage V CM Switching to a reference high voltage V REF A redundant capacitor C R1 The lower polar plate is switched to a common mode voltage V from a reference ground voltage Gnd CM . Then there are:
and (3) P terminal: v P4 ＝V ip
And (3) N terminal:
Figure GDA0003645656960000081
to obtain
Figure GDA0003645656960000082
Performing a fourth comparison to obtain a fourth comparison result d 4 1. And finishing the quantization.
In summary, the successive approximation type analog-to-digital converter based on the transient capacitance switching mode and the quantization method thereof provided by the present invention are based on the upper plate sampling technology, the first comparison is directly performed after sampling, the 1 st bit output codeword is obtained from the result of the first comparison, and then the capacitance switching in the second quantization process is completed according to the result of the first comparison; and simultaneously, determining a target array required to be switched in a subsequent quantization process according to a result of the first comparison. In the subsequent quantization process, only the capacitors in the target array are switched by establishing an intermediate state for transition, so that the DAC capacitor array is formed in a manner similar to a single-ended capacitor switching manner, and the power consumption of the switched capacitor array is reduced. Meanwhile, the N-bit quantization is performed by the N-2-bit quantization capacitor, so that the area is saved by 75% compared with the traditional DAC capacitor array, and the power consumption is reduced.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (1)

1. A successive approximation type analog-to-digital converter quantization method based on a transient capacitance switching mode comprises the following steps: DAC module, comparator and digital logic control module, its characterized in that:
the DAC module comprises a first DAC capacitor array and a second DAC capacitor array, the first DAC capacitor array and the second DAC capacitor array both comprise N-2 binary quantization capacitors and 1 redundant capacitor, and N is the bit number of the successive approximation type analog-to-digital converter; the N-2 quantized capacitors are arranged in order of weight from low to high and are numbered C 1 、C 2 、C 3 、……、C N-2 (ii) a Redundant capacitor C R1 And a quantization capacitor C 1 Are equal; the upper electrode plates of N-2 quantization capacitors and 1 redundant capacitor in the first DAC capacitor array are connected with the positive input end of the comparator and are connected with an input signal V through a switch ip The lower polar plate is connected with a common mode voltage or a reference high voltage or a reference ground voltage after passing through the corresponding N-1 switches respectively; the upper polar plates of N-2 quantization capacitors and 1 redundant capacitor in the second DAC capacitor array are connected with the negative input end of the comparator and are connected with an input signal V through a switch in The lower polar plate is connected with a common mode voltage or a reference high voltage or a reference ground voltage after passing through the corresponding N-1 switches respectively; the voltage value of the common mode voltage is one half of that of the reference high voltage;
the output end of the comparator is respectively connected with the input end of the output module and the input end of the digital logic control module; the output module provides an output signal according to the comparator to finish the output of the quantized code word;
the digital logic control module generates a control signal according to the received output signal of the comparator, and controls the capacitance switching in the capacitor array in the DAC module to realize quantization through the control signal;
the method for quantizing the DAC capacitor array based on the successive approximation type analog-to-digital converter of the transient capacitance switching mode comprises the following steps:
step one, sampling stage
(1) The successive approximation type analog-to-digital converter is electrified and reset, the DAC module carries out sampling, and the upper electrode plates of N-2 quantization capacitors and 1 redundant capacitor in the first DAC capacitor array are connected with an input signal V ip The lower plates of the two DAC capacitor arrays are connected with a reference ground voltage, and the upper plates of the N-2 quantization capacitors and the 1 redundant capacitor in the second DAC capacitor array are connected with an input signal V in The lower polar plates are connected with a reference ground voltage;
(2) After the DAC module finishes sampling, the upper polar plates of all the quantization capacitors and the redundant capacitors are disconnected from the input signal, and the lower polar plates are kept connected with a reference ground voltage; then entering a comparison stage;
step two, a comparison stage: sequentially determining the highest bit output code to the lowest bit output code of the successive approximation type analog-to-digital converter through N times of comparison, and completing the quantization of the DAC capacitor array;
in the first N-1 comparisons, the method for performing the 1 st comparison is as follows: comparing the input signal of positive input end with the input signal of negative input end to obtain the 1 st comparison result d 1 (ii) a According to the 1 st comparison result d 1 Switching all capacitors in the first DAC capacitor array or the second DAC capacitor array to a common-mode voltage, and simultaneously keeping the other DAC capacitor array connected with a reference ground voltage and not switching any more in a later quantization process; for convenience of description, a group of DAC capacitor arrays needing to be switched is called a target array;
go on to the ithThe method of the secondary comparison is as follows: firstly, comparing the input signal of positive input end with the input signal of negative input end to obtain the ith comparison result d i (ii) a Re-comparison d 1 And d 2 、d i And d 1 Then d is 1 And d 2 Comparison result of (d) i And d 1 The comparison results are combined to be used as the basis for capacitance switching in the (i + 1) th quantization process in the target array, and the capacitance switching in the (i + 1) th quantization process of the target array is completed; i is an e [2, N-2 ]]；
When d is 1 And d 2 Is different and d i Is not equal to d 1 When the target array is in the order of C N-i The quantization capacitors are switched to a reference ground voltage gnd from a common-mode voltage VCM;
when d is 1 And d 2 Is different and d i Is equal to d 1 When the target array is switched to the intermediate state, all capacitors in the target array are switched to the intermediate state for transition; the intermediate states at this time are: all capacitors with lower plates connected with a reference ground voltage in one state on the target array are switched to a common mode voltage, and capacitors with lower plates connected with the common mode voltage are switched to a reference high voltage; after the intermediate state is established, the C-th in the target array is set N-i The lower plate of the quantization capacitor is switched to the reference ground voltage, C N-i-1 The lower electrode plate of the quantification capacitor is switched to a common mode voltage, and other capacitors keep the previous target array state;
when d is 1 And d 2 Same and d i Is not equal to d 1 When the target array is switched to the intermediate state, all capacitors in the target array are switched to the intermediate state for transition; the intermediate states at this time are: c in the target array N-i The lower plate of the quantization capacitor is connected with a common mode voltage, C N-i-1 The lower plate of the quantization capacitor is connected with a reference ground voltage, and the other high-order quantization capacitor (C) N-2 -C N-i-2 ) The state is determined by the last target array state; a capacitor with a lower electrode plate connected with a common-mode voltage in the target array is switched to a reference ground voltage, and a capacitor with a lower electrode plate connected with a reference high voltage is switched to the common-mode voltage; the other bit capacitors are connected with a reference ground voltage; after the intermediate state is established, the capacitor with the lower polar plate connected with the reference ground voltage in the target array is switched to the common mode voltage, and the lower polar plate is connected with the common mode voltageThe capacitance is switched to a reference high voltage;
when d is 1 And d 2 Same and d i Is equal to d 1 When the target array is switched to the intermediate state, all capacitors in the target array are switched to the intermediate state for transition; the intermediate states at this time are: c in the target array N-i The lower plate of each quantization capacitor is connected with a common-mode voltage and other high-order capacitors (C) N-2 -C N-i-1 ) The state is determined by the last target array state; the capacitor with the lower polar plate connected with the common mode voltage in the target array is switched to a reference ground voltage, and the capacitor with the lower polar plate connected with the reference high voltage is switched to the common mode voltage; the other bit capacitors are connected with a reference ground voltage; after the intermediate state is established, switching a capacitor of a lower polar plate connected with a reference ground voltage in the target array to a common mode voltage, and switching a capacitor of the lower polar plate connected with the common mode voltage to a reference high voltage;
the method for the N-1 th comparison and the Nth comparison comprises the following steps: comparing the input signal of the positive input end with the input signal of the negative input end of the comparator, obtaining the N-1 th comparison result, and switching the redundant capacitor C in the target array according to the N-1 th comparison result R1 Obtaining the Nth comparison result; and then outputting the N comparison results as N-bit output codes of the successive approximation type analog-to-digital converter, and finishing the quantization.
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