CN105897272B - Successive approximation analog-digital converter and its control method - Google Patents
Successive approximation analog-digital converter and its control method Download PDFInfo
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- CN105897272B CN105897272B CN201610193030.8A CN201610193030A CN105897272B CN 105897272 B CN105897272 B CN 105897272B CN 201610193030 A CN201610193030 A CN 201610193030A CN 105897272 B CN105897272 B CN 105897272B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The present invention provides a kind of successive approximation analog-digital converter and its control methods, the successive approximation analog-digital converter includes two capacitor arrays, two groups of switches, one Voltage Reference Buffer and a comparator, every group of switch includes sampling switch array, reference voltage switch arrays and over the ground switch arrays, the top crown of each capacitor array and an input terminal of comparator connect, the bottom crown of each capacitor array is connect with one group of sampling switch array, and two input terminals of comparator are selectively connect with Voltage Reference Buffer, two groups over the ground switch arrays be grounded, two groups of reference voltage switch arrays are connect with Voltage Reference Buffer.Successive approximation analog-digital converter of the invention uses bottom crown sample mode, so that capacitor array degree parasitic capacitance and the charge injection connecting with the input terminal of comparator are insensitive, improves the precision of result；The power consumption and area of finished product only are reduced with a Voltage Reference Buffer in structure.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of successive approximation analog-digital converter and its control
Method processed.
Background technique
Trend in IC design in recent years has more more low-power consumption, higher performance and less cost
Carry out more harsh requirement, and in the design of analog front circuit, an efficient analog-digital converter (analog-
To-digital converter, abbreviation ADC) system overall performance can be made to greatly improve, ADC is responsible for believing received simulation
Number be converted to digital signal, and be supplied to the digital signal processing unit of rear end to operate, thus its dynamic range, resolution ratio,
Accuracy, the linearity, sample rate, power consumption, input level characteristics etc., all become the important link of influence system overall performance,
Also become the important parameter that assessment converter itself shows.
The framework of existing ADC is many kinds of, such as pipe line analog-digital converter (pipeline analog-to-
Digital converter, abbreviation pipeline ADC) and successive approximation analog-digital converter (successive
Approximation register analog-to-digital converter, abbreviation SAR-ADC) etc. be all the prior art
Common framework in field.Wherein, under same specification demands, SAR-ADC can have lower compared to pipeline ADC
The advantage of power consumption and smaller chip area, also therefore, the technological development for SAR-ADC framework, also gradually by industry weight
Depending on.
It generally can include digital analog converter (digital-to- under the framework of existing SAR-ADC
Analog converter, abbreviation DAC), the parts such as comparator and SAR logic control circuit.Specifically, in traditional SAR-
In the Analog-digital Converter operating process of ADC, DAC generally can first using a reference voltage as benchmark to analog input signal into
Row sampling keeps (sample-and-hold), and SAR logic control circuit can be with binary search algorithm (binary search thereafter
Algorithm the digital-to-analogue conversion of DAC) is controlled, to enable DAC generate corresponding comparison signal, wherein the comparison signal
It is associated with the analog voltage of corresponding Different Logic state and the voltage difference of analog input signal.Then, comparator can be with described
Reference voltage is compared as benchmark with the comparison signal, to enable ratio of the SAR logic control circuit based on comparator
Relatively result and determine each logic state of digital output signal one by one.
Currently, SAR ADC is designed primarily to reversely merge switch (Inverted merged capacitor
Switching, IMCS) and dull switch (Monotonic switching, MS) both structures.Referring to FIG. 1, it is
The structural schematic diagram of 10 SAR ADC of IMCS structure, as shown in Figure 1, the SAR ADC of IMCS structure is sampled using bottom crown
Technology, so the charge injection that it switchs DAC output end to parasitic capacitance and input sample is insensitive；Referring to FIG. 2, it is
The structural schematic diagram of 10 SAR ADC of MS structure, as shown in Figure 2, MS structure be using top crown sampling technique, so it
The charge injection of parasitic capacitance and input sample switch to DAC output end is extremely sensitive.Secondly, IMCS structure needs to refer to electricity
Two voltage buffers of compression buffer (Vrefp buffer) and common mode reference voltage buffer (VCM buffer) and two groups
It switchs, includes sequentially connected sampling switch array, a reference voltage switch arrays, a common mode reference voltage in every group of switch
Switch arrays and switch arrays over the ground, the ground connection of switch arrays over the ground, the reference voltage switch arrays and the reference
Voltage buffer connection, the common mode reference voltage switch arrays are connect with the common mode reference voltage buffer；And MS structure
Only need a Voltage Reference Buffer and two groups of switches, include in every group of switch sequentially connected sampling switch array,
One reference voltage switch arrays and switch arrays over the ground, the ground connection of switch arrays over the ground, the reference voltage switch arrays
It is connect with the Voltage Reference Buffer, structure is complicated and power consumption is high by IMCS structure ratio MS.Therefore, SAR ADC is to obtaining height
Precision, IMCS structure is preferred, and to reduce power consumption and complexity, then to select MS structure.
In view of the above-mentioned problems, those skilled in the art always search for and design can meet high-precision and low-power consumption need simultaneously
The SAR ADC asked.
Summary of the invention
The purpose of the present invention is to provide a kind of successive approximation analog-digital converters, to solve existing successive approximation
The structure of analog-digital converter can not meet the problem of high-precision and low-power consumption simultaneously.
In order to solve the above technical problems, the present invention provides a kind of successive approximation analog-digital converter, it is described gradually to force
Nearly formula analog-digital converter includes:
Two capacitor arrays, two groups of switches, a Voltage Reference Buffer and a comparator, every group of switch include according to
The sampling switch array of secondary connection, reference voltage switch arrays and switch arrays over the ground, wherein the top crown of each capacitor array
It is connect with an input terminal of the comparator, the bottom crown of each capacitor array is connect with one group of sampling switch array, and institute
State comparator two input terminals selectively connect with the Voltage Reference Buffer, two groups over the ground switch arrays be grounded, two
Group reference voltage switch arrays are connect with the Voltage Reference Buffer.
Optionally, in the successive approximation analog-digital converter, the bottom crown of each capacitor array and one group
When sampling switch array connects, bottom crown and one in the sampling switch array of each capacitor in the capacitor array
Sampling switch connection, and the sampling switch that each capacitor is connected in the capacitor array is different.
Optionally, in the successive approximation analog-digital converter, the capacitor array is segmented binary system
Weight capacitor array.
It optionally, further include a SAR logic control circuit, institute in the successive approximation analog-digital converter
SAR logic control circuit is stated to connect with the output end of the comparator.
Optionally, in the successive approximation analog-digital converter, the top crown of one of capacitor array with
The positive input terminal of the comparator connects, and the top crown of another capacitor array is connect with the negative input end of the comparator.
The present invention also provides a kind of control method of successive approximation analog-digital converter, the successive approximation simulation
The control method of digital quantizer includes:
The top crown of two capacitor arrays is connected Voltage Reference Buffer, the lower pole of a capacitor array by sample phase
Plate accesses input signal, and the bottom crown of another capacitor array accesses another input signal, to adopt to two input signals
Sample；And
The top crown of two capacitor arrays and Voltage Reference Buffer are disconnected, and make capacitor array by the Approach by inchmeal stage
Bottom crown connect Voltage Reference Buffer so that the charge of two input terminals of the comparator is redistributed, according to the ratio
Output result compared with device completes Approach by inchmeal process.
Optionally, in the control method of the successive approximation analog-digital converter, if the comparator is defeated
Out for height, then the bottom crown of the capacitor in predetermined position still connects ginseng in the capacitor array connecting with the positive input terminal of the comparator
Voltage buffer is examined, the bottom crown of the capacitor of same position connects in the capacitor array connecting with the negative input end of the comparator
Ground；
If the output of the comparator be it is low, be pre-positioned in the capacitor array being connect with the negative input end of the comparator
The bottom crown for the capacitor set still connects Voltage Reference Buffer, phase in the capacitor array connecting with the positive input terminal of the comparator
With the bottom crown ground connection of the capacitor of position.
Optionally, in the control method of the successive approximation analog-digital converter, the successive approximation mould
Quasi- digital quantizer further includes a SAR logic control circuit, is connect with the output end of the comparator, and SAR logic control is utilized
Output result of the circuit based on comparator and determine each logic state of digital output signal one by one.
Optionally, in the control method of the successive approximation analog-digital converter, the capacitor array is point
Segmentation binary weights capacitor array.
Optionally, in the control method of the successive approximation analog-digital converter, under each capacitor array
When pole plate is connect with one group of switch, the bottom crown of each capacitor in the capacitor array and the sampling switch battle array of current switch group
Sampling switch connection in column, and the sampling switch that each capacitor is connected in the capacitor array is different.
In successive approximation analog-digital converter provided by the present invention and its control method, the successive approximation
Analog-digital converter include two capacitor arrays, two groups of switches, a Voltage Reference Buffer and a comparator, every group
Switch includes sampling switch array, reference voltage switch arrays and switch arrays over the ground, the top crown of each capacitor array with than
An input terminal compared with device connects, and the bottom crown of each capacitor array is connect with one group of sampling switch array, and the two of comparator
A input terminal is selectively connect with Voltage Reference Buffer, two groups over the ground switch arrays be grounded, two groups of reference voltage switch arrays
Column are connect with Voltage Reference Buffer.Successive approximation analog-digital converter of the invention uses bottom crown sample mode,
So that capacitor array degree parasitic capacitance and the charge injection connecting with the input terminal of comparator are insensitive, the essence of result is improved
Degree；The power consumption and area of finished product only are reduced with a Voltage Reference Buffer in structure.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of 10 SAR ADC of IMCS structure；
Fig. 2 is the structural schematic diagram of 10 SAR ADC of MS structure；
Fig. 3 is the structural schematic diagram of 10 successive approximation analog-digital converters of one embodiment of the invention；
Fig. 4 is the flow chart of the control method of the successive approximation analog-digital converter of one embodiment of the invention；
Fig. 5 is that the sequence of switches of 3 successive approximation analog-digital converters of one embodiment of the invention is related
Schematic diagram.
In Fig. 3:
Capacitor array 10a, 10b；Voltage Reference Buffer 11；Comparator 12；Sampling switch array 13a, 13b；With reference to electricity
Compress switch array 14a, 14b；Switch arrays 15a, 15b over the ground；SAR logic control circuit 16.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to successive approximation analog-digital converter proposed by the present invention and its control
Method processed is described in further detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It needs
Illustrate, attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly auxiliary is said
The purpose of the bright embodiment of the present invention.
It is unrestricted to enumerate as a specific embodiment of the invention, turned with 10 successive approximation simulation numerals
The specific structure of successive approximation analog-digital converter is described in detail for parallel operation (SAR-ADC).Fig. 3 is this implementation
The structural schematic diagram for 10 successive approximation analog-digital converters that example provides.As shown in figure 3, the successive approximation mould
Quasi- digital quantizer includes: two capacitor arrays, two groups of switches, a Voltage Reference Buffer 11 and a comparator 12.
Described two capacitor arrays are respectively capacitor array 10a and capacitor array 10b.The top crown of capacitor array 10a with
An input terminal (in the present embodiment the be positive input terminal) connection of the comparator 12, the top crown of capacitor array 10b with it is described
Another input terminal (being negative input end in the present embodiment) connection of comparator 12, and two input terminals choosing of the comparator 12
Selecting property is connect with the Voltage Reference Buffer 11.The bottom crown of described two capacitor array 10a, 10b respectively with one group of switch
Connection.
Every group of switch includes sequentially connected sampling switch array, reference voltage switch arrays and switch arrays over the ground.Its
In, one group of sampling switch array accesses input signal Vip, and another group of sampling switch array accesses input signal Vin；Two groups over the ground
Switch arrays are grounded；Two groups of reference voltage switch arrays are connect with same Voltage Reference Buffer 11 to access a reference voltage
Buffering signals Vrefp.
Detailed, one group of switch connecting with capacitor array 10a includes sequentially connected sampling switch array 13a, reference
Voltage switch array 14a and over the ground switch arrays 15a, the 15a of the switch arrays over the ground ground connection, the reference voltage switch arrays
14a is connect with the Voltage Reference Buffer 11；One group of switch connecting with capacitor array 10b includes that sequentially connected sampling is opened
Close array 13b, reference voltage switch arrays 14b and over the ground switch arrays 15b, the 15b of the switch arrays over the ground ground connection, the ginseng
Voltage switch array 14b is examined to connect with the Voltage Reference Buffer 11.
As described above, the successive approximation analog-digital converter of the present embodiment passes through electricity using bottom crown sample mode
Hold the bottom crown capacitor array that is sampled, therefore be connected with the input terminal of comparator 12 of capacitor in array to parasitic capacitance and
Charge injection is insensitive, at the same time, a reference electricity has only been used in the successive approximation analog-digital converter of the present embodiment
Compression buffer 11, to reduce power consumption and reduce area needed for finished product.In addition, include 3 kinds of switch arrays in every group of switch,
A kind of few switch arrays, structure are relatively easy in opposite every group of switch of IMCS structure.
With continued reference to FIG. 3, the bottom crown of each capacitor in two groups of capacitor arrays 10a, 10b respectively connects sampling switch
The bottom crown of a sampling switch in array, i.e., one capacitor connects a sampling switch, and the two is one-to-one relationship.
In the present embodiment, the capacitor array is segmented binary weights capacitor array, using segmented binary weights capacitor battle array
For column are compared to the capacitance structure for using pure binary weight capacitor array, the matching performance of capacitor array domain is more preferable, reason
Being segmented binary capacitor weight array, there are two each Self Matchings of capacitor array, and weight position span is smaller, are conducive to
It is matched on domain；And pure binary weight capacitor array minimum capacity is too big to maximum capacitor value span, therefore is unfavorable for
It is matched on domain.
Further, the successive approximation analog-digital converter further includes a SAR logic control circuit 16, with institute
The output end connection for stating comparator 12, determines that digital output signal is every so as to the comparison result based on comparator 12 one by one
One logic state.Wherein, the EOC of the output end of SAR logic control circuit 16 refers to each conversion of SARADC converter
Enable signal after the completion, D9~D0 are the 10 bit data output signals of SARADC.
In addition, the successive approximation analog-digital converter further includes a clock signal generator, in the work of clock clk
Under, sampled clock signal sampclk and sampclka are generated.
The present embodiment additionally provides a kind of control method of successive approximation analog-digital converter.Such as Fig. 3 and Fig. 4 institute
Show, the control method of the successive approximation analog-digital converter of the present embodiment includes:
Sample phase makes the top crown of described capacitor array 10a, 10b connect Voltage Reference Buffer 11, capacitor array
The bottom crown of 10a accesses input signal Vip, and the bottom crown of capacitor array 10b accesses input signal Vin, to believe the input
Number Vip, Vin are sampled；And
The top crown of capacitor array 10a, 10b and Voltage Reference Buffer 11 are disconnected, and make capacitor by the Approach by inchmeal stage
The bottom crown of array 10a, 10b connect Voltage Reference Buffer 11, so that the charge of two input terminals of the comparator 12 is again
Distribution completes Approach by inchmeal process according to the output result of the comparator 12.
Wherein, if the output of the comparator 12 is height, the capacitor battle array connecting with the positive input terminal of the comparator 12
The bottom crown of the capacitor in predetermined position still connects Voltage Reference Buffer 11 in column 10a, the negative input end with the comparator 12
The bottom crown ground connection of the capacitor of same position in the capacitor array 10b of connection；If the output of the comparator 12 be it is low, with institute
The bottom crown for stating the capacitor in predetermined position in the capacitor array of the negative input end 10b connection of comparator 12 is still connected reference voltage and is delayed
Device 11 is rushed, the bottom crown ground connection of the capacitor of same position in the capacitor array 10a connecting with the positive input terminal of the comparator 12.
Further, referring to FIG. 3, output result using SAR logic control circuit 16 based on comparator and determine one by one
Each logic state (i.e. 0 or 1) of fixed number word output signal indicates the output voltage of comparator for height in the present embodiment with 1
Current potential indicates the output voltage of comparator as low potential using 0.
The control method of successive approximation analog-digital converter in order to better understand the present invention, below with reference to Fig. 5 institute
The sequence of switches accompanying drawings of the 3 successive approximation analog-digital converters shown are described in detail.
As shown in figure 5, input signal Vip, Vin connects the bottom crown of capacitor array 10a, 10b, reference in sample phase
Voltage buffer (Vrefp buffer) 11 connect two capacitor arrays 10a, 10b top crown, to input signal Vip, Vin into
Row sampling；
In the Approach by inchmeal stage, a cycle, Voltage Reference Buffer 11 is from the upper pole of two capacitor arrays 10a, 10b
Plate disconnects, and the bottom crown of two capacitor arrays 10a, 10b connect (the i.e. capacitor all in capacitor array of Voltage Reference Buffer 11
Bottom crown be all connected with Voltage Reference Buffer 11), two input terminal charges of comparator 12 are redistributed.In the present embodiment,
If the voltage value of input signal Vip is greater than the voltage value of input signal Vin, the output voltage of comparator 12 is high potential, such as
The voltage value of fruit input signal Vip is less than the voltage value of input signal Vin, then the output voltage of comparator 12 is low potential；The
Two periods connect if the output voltage of upper a cycle comparator 12 is height with the positive input terminal of the comparator 12
Capacitor array 10a in capacitor be 2C the bottom crown of capacitor still connect Voltage Reference Buffer, with the comparator 12
The bottom crown ground connection for the capacitor that the capacitor of same position is 2C in the capacitor array 10b of negative input end connection；If upper period ratio
Output voltage compared with device 12 is low potential, the then capacitor in capacitor array 10b connecting with the negative input end of the comparator 12
Bottom crown for the capacitor of 2C still connects Voltage Reference Buffer 11, the capacitor battle array connecting with the positive input terminal of the comparator 12
The bottom crown ground connection for the capacitor that the capacitor for arranging same position in 10a is 2C；And so on, it is fully completed until comparing, i.e. SAR
ADC mono- complete change-over period completes.
Table 1 is the advantage and disadvantage pair of the SAR ADC of the SAR ADC of the present embodiment and SAR ADC and the MS structure of IMCS structure
Than specific as follows:
Table 1
By 1 comparative analysis of table it is found that the advantages of SARADC of the invention can be in conjunction with both structures, overcome IMCS structure and
MS structure there are the shortcomings that, while meeting high-precision and the needs of low-power consumption.
To sum up, described gradually to force in successive approximation analog-digital converter provided by the present invention and its control method
Nearly formula analog-digital converter includes two capacitor arrays, two groups of switches, a Voltage Reference Buffer and a comparator,
Every group of switch includes sampling switch array, reference voltage switch arrays and switch arrays over the ground, the top crown of each capacitor array
It is connect with an input terminal of comparator, the bottom crown of each capacitor array is connect with one group of sampling switch array, and comparator
Two input terminals selectively connect with Voltage Reference Buffer, two groups over the ground switch arrays be grounded, two groups of reference voltages are opened
Array is closed to connect with Voltage Reference Buffer.Successive approximation analog-digital converter of the invention uses bottom crown sampling side
Formula improves result so that capacitor array degree parasitic capacitance and the charge injection connecting with the input terminal of comparator are insensitive
Precision；The power consumption and area of finished product only are reduced with a Voltage Reference Buffer in structure.It can be seen that it is of the invention by
The needs of for high-precision and low-power consumption can be met simultaneously by walking approximant analog-digital converter.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of successive approximation analog-digital converter characterized by comprising two capacitor arrays, two groups of switches, one
Voltage Reference Buffer and a comparator, every group of switch include sequentially connected sampling switch array, reference voltage switch
Array and over the ground switch arrays, wherein the top crown of each capacitor array is connect with an input terminal of the comparator, each
The bottom crown of capacitor array is connect with one group of sampling switch array, and the two input terminals selectivity and the ginseng of the comparator
Examine voltage buffer connection, two groups over the ground switch arrays be grounded, two groups of reference voltage switch arrays with the reference voltage
Buffer connection.
2. successive approximation analog-digital converter as described in claim 1, which is characterized in that the lower pole of each capacitor array
When plate is connect with one group of sampling switch array, the bottom crown of each capacitor in the capacitor array and the sampling switch array
In the connection of a sampling switch, and each capacitor is connected in the capacitor array sampling switch is different.
3. successive approximation analog-digital converter as described in claim 1, which is characterized in that the capacitor array is segmentation
Formula binary weights capacitor array.
4. successive approximation analog-digital converter as described in claim 1, which is characterized in that further include a SAR logic control
Circuit processed, the SAR logic control circuit are connect with the output end of the comparator.
5. successive approximation analog-digital converter as described in claim 1, which is characterized in that one of capacitor array
Top crown is connect with the positive input terminal of the comparator, the negative input end of the top crown of another capacitor array and the comparator
Connection.
6. a kind of control method of successive approximation analog-digital converter as described in claim 1 characterized by comprising
The top crown of two capacitor arrays is connected Voltage Reference Buffer by sample phase, and the bottom crown of a capacitor array connects
Enter input signal, the bottom crown of another capacitor array accesses another input signal, to sample to two input signals；With
And
The top crown of two capacitor arrays and Voltage Reference Buffer are disconnected, and made under capacitor array by the Approach by inchmeal stage
Pole plate connects Voltage Reference Buffer, so that the charge of two input terminals of the comparator is redistributed, according to the comparator
Output result complete Approach by inchmeal process.
7. the control method of successive approximation analog-digital converter as claimed in claim 6, which is characterized in that if the ratio
Output compared with device is height, then the bottom crown of the capacitor in predetermined position in the capacitor array connecting with the positive input terminal of the comparator
Voltage Reference Buffer is still connected, in the capacitor array connecting with the negative input end of the comparator under the capacitor of same position
Pole plate ground connection；
If the output of the comparator is low, predetermined position in the capacitor array connecting with the negative input end of the comparator
The bottom crown of capacitor still connects Voltage Reference Buffer, identical bits in the capacitor array connecting with the positive input terminal of the comparator
The bottom crown for the capacitor set is grounded.
8. the control method of successive approximation analog-digital converter as claimed in claim 6, which is characterized in that it is described gradually
Approximant analog-digital converter further includes a SAR logic control circuit, connect with the output end of the comparator, utilizes SAR
Output result of the logic control circuit based on comparator and determine each logic state of digital output signal one by one.
9. the control method of successive approximation analog-digital converter as claimed in claim 6, which is characterized in that the capacitor
Array is segmented binary weights capacitor array.
10. the control method of successive approximation analog-digital converter as claimed in claim 6, which is characterized in that Mei Ge electricity
When the bottom crown of appearance array is connect with one group of switch, bottom crown and the current switch group of each capacitor in the capacitor array
Sampling switch connection in sampling switch array, and the sampling switch that each capacitor is connected in the capacitor array is not
Together.
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| CN107786206B (en) * | 2017-11-29 | 2024-02-02 | 四川知微传感技术有限公司 | Pipeline SAR-ADC system |
| US10447291B1 (en) | 2018-09-14 | 2019-10-15 | Linear Technology Holding, LLC | High dynamic range analog-to-digital converter |
| CN109450449B (en) * | 2018-11-23 | 2020-12-18 | 深圳锐越微技术有限公司 | Reference voltage control circuit and analog-to-digital converter |
| CN109768800B (en) * | 2018-11-27 | 2021-01-15 | 西安电子科技大学 | Ultralow-power-consumption successive approximation type analog-to-digital converter based on charge redistribution |
| CN111786677B (en) * | 2019-04-03 | 2024-02-06 | 扬智科技股份有限公司 | Continuous approximation type analog-to-digital converter |
| CN110138387B (en) * | 2019-06-05 | 2020-11-03 | 中国电子科技集团公司第二十四研究所 | SAR ADC based on single-channel time interleaved sampling and sampling method |
| CN112118009A (en) * | 2019-06-21 | 2020-12-22 | 瑞昱半导体股份有限公司 | Successive approximation analog-to-digital converter and operation method thereof |
| CN110768670B (en) * | 2019-09-26 | 2021-05-28 | 西安交通大学 | Digital piecewise linear calibration method for successive approximation type analog-to-digital converter |
| CN111431534B (en) * | 2020-05-13 | 2023-04-07 | 深圳芥子科技有限公司 | Analog-digital converter for quantizing multipath input |
| CN112968704B (en) * | 2021-02-03 | 2022-07-29 | 电子科技大学 | Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode |
| CN113839673B (en) * | 2021-09-14 | 2023-08-01 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
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