CN111786677B - Continuous approximation type analog-to-digital converter - Google Patents
Continuous approximation type analog-to-digital converter Download PDFInfo
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- CN111786677B CN111786677B CN201910265660.5A CN201910265660A CN111786677B CN 111786677 B CN111786677 B CN 111786677B CN 201910265660 A CN201910265660 A CN 201910265660A CN 111786677 B CN111786677 B CN 111786677B
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- 239000003990 capacitor Substances 0.000 claims abstract description 247
- 230000004044 response Effects 0.000 claims abstract description 12
- 239000000470 constituent Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 20
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
- H03M1/403—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type using switched capacitors
Abstract
A continuous approximation analog-to-digital converter includes a comparator, a capacitor array, a switch array, and a specification selection circuit. The comparator is provided with a first input end, a second input end and an output end, and is used for comparing the input of the first input end and the second input end and outputting a comparison result to the output end. The capacitor array is coupled to the comparator and comprises a plurality of component capacitors, and the switch array is coupled to the capacitor array. The specification selection circuit is coupled to the comparator and the capacitor array, and the specification selection circuit comprises a switch and a capacitor and receives a common voltage. The continuous approximation type analog-digital converter is operated in a first specification state in response to the switch of the specification selection circuit being turned on, and is operated in a second specification state in response to the switch of the specification selection circuit being turned off.
Description
Technical Field
The present invention relates to an analog-to-digital converter, and more particularly, to a continuous approximation analog-to-digital converter.
Background
In recent years, there is a trend in integrated circuit design for lower power consumption, higher performance, and lower cost, and in the design of an analog front-end circuit, an efficient analog-to-digital converter (ADC) can greatly improve the overall performance of the system, and the ADC is responsible for converting a received analog signal into a digital signal and providing the digital signal to a digital signal processing unit at the back end for operation, so that the dynamic range, resolution, accuracy, linearity, sampling speed, power consumption, and the like of the ADC become important links affecting the overall performance of the system, and become important parameters for evaluating the performance of the ADC itself.
The existing ADC has a wide variety of architecture, such as a pipeline ADC (pipeline analog to digital converter) and a continuous analog-to-digital ADC (successive approximation register analog to digital converter, SAR ADC), which are all commonly used in the prior art. Under the same specification requirements, SAR ADC has advantages of lower power consumption and smaller chip area compared with pipeline ADC, and therefore, development of SAR ADC architecture is also becoming important in the industry. That is, how to design a practical and accurate SAR ADC is a matter of interest to those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a continuous analog-to-digital converter, which can meet the requirements of the first and second circuit specifications according to simple control, so as to be operable in different circuit environments.
An embodiment of the invention provides a continuous approximation analog-to-digital converter comprising a comparator, a capacitor array, a switch array, and a specification selection circuit. The comparator is provided with a first input end, a second input end and an output end, and is used for comparing the input of the first input end and the second input end and outputting a comparison result to the output end. The capacitor array is coupled to the comparator and comprises a plurality of component capacitors, and the switch array is coupled to the capacitor array. The specification selection circuit is coupled to the comparator and the capacitor array, and the specification selection circuit comprises a switch and a capacitor and receives a common voltage. The continuous approximation type analog-digital converter is operated in a first specification state in response to the switch of the specification selection circuit being turned on, and is operated in a second specification state in response to the switch of the specification selection circuit being turned off.
In an embodiment of the invention, the constituent capacitors are formed by a plurality of first unit capacitors, and the first unit capacitors are integrally arranged on the substrate to form a first capacitor block. The capacitor of the specification selection circuit is formed by a plurality of second unit capacitors which are integrally arranged on the substrate to form a second capacitor block. The redundant capacitor block is arranged between the first capacitor block and the second capacitor block. The redundant capacitor block comprises a plurality of redundant capacitors which are integrally arranged on the substrate, so that the first capacitor block is not directly adjacent to the second capacitor block on the substrate.
Based on the above, in the embodiment of the invention, the continuous approximation analog-to-digital converter includes the specification selection circuit, and the switch in the specification selection circuit can be turned on or turned off in response to a level of a control voltage. The successive approximation analog-to-digital converter is selectively operable in a first specification state or a second specification state in response to a switch within the specification selection circuit being turned on or off. Thus, the continuous approximation type analog-digital converter can perform analog-digital conversion operation for different input voltage ranges. In addition, the redundant capacitor additionally arranged on the substrate can prevent the parasitic capacitance generated between the capacitance in the specification selection circuit and the capacitance in the digital-analog converter from affecting the accuracy of the continuous approximation type analog-digital converter.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a continuous analog-to-digital converter according to an embodiment of the invention.
Fig. 2 is a partial schematic diagram of a continuous analog-to-digital converter according to an embodiment of the invention.
Fig. 3 is a schematic layout diagram of a first capacitor array block, a redundant capacitor array block and a second capacitor array block according to an embodiment of the present invention.
Fig. 4A is a schematic diagram of a redundancy capacitor constituting a redundancy capacitor according to an embodiment of the present invention.
Fig. 4B is a schematic layout diagram of a first capacitor array block, a redundant capacitor array block and a second capacitor array block according to an embodiment of the invention.
Description of the reference numerals
10: continuous approximation type analog-to-digital converter
101: comparator with a comparator circuit
102_1, 102_2: specification selection circuit
103: SAR control circuit
104: positive phase capacitor array
105: negative phase capacitor array
106: positive phase switch array
107: negative phase switch array
CA: capacitor array
SA1: switch array
108: sample and hold circuit
Vref, vref1, vrefp, vrefn: reference voltage
Vcm: universal voltage
SW1, SW2: switch
IN1, IN2: input terminal
OUT: an output terminal
Vcmp: comparison result
ADR: digital conversion result
VIN: analog input signal
Vip: normal phase input signal
Vin: negative phase input signal
CA1, CA2: capacitance device
Ctr1: control voltage
C11 to C1M, C to C2M: component capacitor
111-11M, 121-12M: switch unit
Sp, sn: digital logic signal
P1, P2: substrate board
B1 and B3: first capacitor block
B2, B4: second capacitor block
Z1 and Z2: redundant capacitor block
41: bottom plate
40: top plate
DC. DC': redundant capacitor
GND: ground (floor)
CU1: first unit capacitor
CU2: second unit capacitor
Detailed Description
Reference will now be made in detail to the present exemplary embodiments, examples of which are illustrated in the accompanying drawings. In addition, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The terms "first," "second," and the like, herein below, are used for distinguishing between and not for ordering or defining differences between the elements indicated, and are not used for limiting the scope of the present invention.
Fig. 1 is a schematic diagram of a continuous analog-to-digital converter according to an embodiment of the invention. Referring to fig. 1, a continuous analog-to-digital converter (hereinafter referred to as SAR ADC) 10 of the present embodiment is adapted to convert an analog input signal VIN into a multi-bit resolution digital conversion result ADR, such as 4-bit, 12-bit or 16-bit, etc. Here, the SAR ADC 10 is a differential architecture capable of suppressing noise, and thus the analog input signal VIN may include a positive phase input signal Vip and a negative phase input signal VIN. In other words, the SAR ADC 10 belongs to an analog-to-digital converter having a symmetrical structure. The SAR ADC 10 includes a comparator 101, specification selection circuits 102_1, 102_2, SAR control circuit 103, capacitor array CA, switch array SA1, and sample and hold circuit 108. The capacitor array CA is coupled to the comparator 101 and includes a plurality of capacitors, and the switch array SA1 is coupled to the capacitor array CA. Further, the capacitor array CA and the switch array SA1 will constitute a digital-to-analog conversion (DAC) circuit within the SAR ADC 10.
In the present embodiment, since the SAR ADC 10 is a differential architecture, the capacitor array CA may include a positive phase capacitor array 104 and a negative phase capacitor array 105, and the switch array SA1 may include a positive phase switch array 106 and a negative phase switch array 107. The positive phase capacitor array 104 is coupled between the positive phase switch array 106 and the first input terminal IN1 of the comparator 101, and the negative phase capacitor array 105 is coupled between the negative phase switch array 107 and the second input terminal IN2 of the comparator 101. In detail, the positive phase capacitor array 104 and the negative phase capacitor array 105 each have M component capacitors, where M is a positive integer. And, one end of each of the constituent capacitors IN the positive capacitor array 104 is commonly coupled to the first input terminal IN1 of the comparator 101, and the other end of each of the constituent capacitors IN the positive capacitor array 104 is coupled to the positive switch array 106. One end of each of the constituent capacitors IN the negative phase capacitor array 105 is commonly coupled to the second input terminal IN2 of the comparator 101, and the other end of each of the constituent capacitors IN the negative phase capacitor array 105 is coupled to the negative phase switch array 107.
The sample and hold circuit 108 is used to sample and hold the analog input signal VIN. For example, the sample and hold circuit 108 may include two switches respectively connected to the first input terminal IN1 and the second input terminal IN2 of the comparator 101, and respectively sample the positive phase input signal Vip and the negative phase input signal Vin during the sampling period of the SAR ADC 10. The comparator 101 has a first input terminal IN1, a second input terminal IN2, and an output terminal OUT. The comparator 101 compares the inputs of the first input terminal IN1 and the second input terminal IN2, and outputs the comparison result Vcmp to the output terminal OUT.
The SAR control circuit 103 is coupled to the output OUT of the comparator 101. During the charge redistribution of the SAR ADC 10, the SAR control circuit 103 generates digital logic signals Sp and Sn in a continuous progressive (SAR) manner according to the comparison result Vcmp generated by the output terminal OUT of the comparator 101, so as to switch the switches of the switch array SA 1. The SAR control circuit 103 further receives and generates a digital conversion result ADR according to the comparison result Vcmp generated at the output terminal OUT of the comparator 101.
It should be noted that, IN the present embodiment, the specification selection circuit 102_1 is coupled to the first input terminal IN1 of the comparator 101 and the capacitor array CA. The specification selection circuit 102_2 is coupled to the second input terminal IN2 of the comparator 101 and the capacitor array CA. The specification selection circuit 102_1 includes a switch SW1 and a capacitor CA1, and receives a common voltage Vcm. The specification selection circuit 102_2 includes a switch SW2 and a capacitor CA2, and receives the common voltage Vcm. The switches SW1, SW2 will be turned on or off in response to the level of the control voltage Ctr1. Here, the switches SW1 and SW2 are implemented as NMOS devices, respectively, but the present invention is not limited thereto. In addition, the capacitance of the capacitors CA1 and CA2 and the capacitance of the component capacitors in the capacitor array CA have a specific relationship, and the specific relationship affects the input signal specification of the continuous analog-to-digital converter 10 and the voltage level setting of the reference voltage Vref and the common voltage Vcm. For example, in an operating environment where the reference voltage Vref is equal to the maximum value of the input voltage specified by the input signal specification, the capacitance of the capacitors CA1 and CA2 may be equal to the sum of the capacitance of the capacitors in the positive-phase capacitor array 104 and the sum of the capacitance of the capacitors in the negative-phase capacitor array 105, respectively. As shown in fig. 1, the switches SW1 and SW2 of the specification selection circuits 102_1 and 102_2 respectively include a control terminal, a first terminal and a second terminal. The control ends of the switches SW1 and SW2 are respectively coupled to the corresponding control voltages Ctr1. The first ends of the switches SW1 and SW2 are respectively coupled to the turn-on voltage Vcm, the second ends of the switches SW1 and SW2 are respectively coupled to one ends of the corresponding capacitors CA1 and CA2, and the other ends of the capacitors CA1 and CA2 of the specification selection circuits 102_1 and 102_2 are respectively coupled to the first input end IN1 and the second input end IN2 of the comparator 101.
It should be noted that the reference voltage Vref is generally a predetermined voltage value. When the switches SW1, SW2 are turned off, the presence of the specification selection circuits 102_1, 102_2 does not have an effect on the overall circuit. In this case, it is assumed that the reference voltage Vref is set to a preset reference value that is greater than or equal to the maximum value of the analog input voltage VIN that the SAR ADC 10 may receive. That is, when the reference voltage Vref is set to a preset reference value and the switches SW1 and SW2 are turned off, the SAR ADC 10 is adapted to receive a second input voltage (i.e., the analog input voltage VIN) within a second voltage range, so as to correctly perform the analog-to-digital conversion operation.
On the other hand, when the switches SW1, SW2 are turned on, the common voltage Vcm charges the capacitors CA1, CA 2. Therefore, IN this case, the required charge amounts of the first input terminal IN1 and the second input terminal IN2 are increased, and the input voltage range of the SAR ADC 10 capable of processing is reduced if the reference voltage Vref is still equal to the predetermined reference value. In other words, when the reference voltage Vref is set to the preset reference value and the switches SW1 and SW2 are turned on, the SAR ADC 10 is adapted to receive a first input voltage (i.e. the analog input voltage VIN) within the first voltage range.
Based on the above, the SAR ADC 10 is adapted to operate in the first specification state in response to the switches SW1, SW2 of the specification selection circuits 102_1, 102_2 being turned on. Further, the SAR ADC 10 is adapted to operate in a second specification state in response to the turning off of the switches SW1, SW2 of the specification selection circuits 102_1, 102_2. Table 1 provides examples according to one embodiment of the present invention. However, table 1 is merely exemplary and is not intended to limit the present invention. Referring to table 1, the SAR ADC 10 is operable in either the first specification state S2 or the second specification state T2 in response to the on or off of the switches SW1, SW2 of the specification selection circuits 102_1, 102_2 under the constraint that the reference voltages provided by the circuit environment are the same (0.6 volts). That is, the SAR ADC 10 is responsive to the switches SW1, SW2 of the specification selection circuits 102_1, 102_2 being turned on to meet the requirements of the first specification state S2. The SAR ADC 10 is responsive to the switch SW1, SW2 of the specification select circuit 102_1, 102_2 being turned off to meet the requirements of the second specification state T2.
TABLE 1
| Circuit specification | Input voltage range | The state of the switches SW1, SW2 | Reference voltage |
| S2 | 0.3 | Cut-off | 0.3 |
| S2 | 0.3 | Conduction | 0.6 |
| T2 | 0.6 | Cut-off | 0.6 |
| T2 | 0.6 | Conduction | 1.2 |
Fig. 2 is a partial schematic diagram of a continuous analog-to-digital converter according to an embodiment of the invention. Referring to fig. 2, the normal phase capacitor array 104 has a plurality of constituent capacitors C11-C1M (IN this embodiment, the normal phase capacitor array 104 has M constituent capacitors, M is a positive integer), one ends of the constituent capacitors C11-C1M are commonly coupled to the first input terminal IN1 of the comparator 101, and the other ends of the constituent capacitors C11-C1M are coupled to the normal phase switch array 106. The normal phase switch array 106 also has M switch units 111-11M, one ends of the switch units 111-11M are respectively coupled to the corresponding terminals of the component capacitors C11-C1M, and the other terminal is not coupled to the first input terminal IN1 of the comparator 101. For example, the component capacitor C13 is connected IN series between the switch unit 113 and the first input terminal IN1 of the comparator 101. In addition, the switch units 111-11M further receive reference voltages Vrefp, vrefn and a common voltage Vcm. The switch units 111-11M are controlled by the digital logic signal Sp so that the corresponding component capacitors C11-C1M receive one of the reference voltages Vrefp, vrefn and the common voltage Vcm. For example, the switch units 111-11M may each include three switches, such that the constituent capacitors C11-C1M receive one of the reference voltages Vrefp, vrefn and the common voltage Vcm.
A negative-phase capacitor array 105 is coupled to the second input IN2 of the comparator 101. The negative phase capacitor array 105 has a plurality of constituent capacitors C21-C2M (IN this embodiment, the negative phase capacitor array 105 has M capacitors), one ends of the constituent capacitors C21-C2M are commonly coupled to the second input terminal IN2 of the comparator 101, and the other ends of the constituent capacitors C21-C2M are coupled to the negative phase switch array 107. The negative-phase switch array 107 also has M switch units 121-12M, wherein one ends of the switch units 121-12M are respectively coupled to the other ends of the corresponding component capacitors C21-C2M, which are not coupled to the second input terminal IN2 of the comparator 101. For example, the capacitor C22 is connected IN series between the switch unit 122 and the second input terminal IN2 of the comparator 101. In addition, the switch units 121-12M further receive reference voltages Vrefp, vrefn and a common voltage Vcm. The switch units 121-12M are controlled by the digital logic signal Sn so that the corresponding component capacitors C21-C2M receive one of the reference voltages Vrefp, vrefn and the common voltage Vcm.
Note that in the normal phase capacitor array 104, the capacitance values of the M component capacitors exist in a proportional relationship. Specifically, the (i+1) th component capacitor in the normal phase capacitor array 104 has a capacitance value twice that of the (i) th component capacitor, where i is a positive integer from 1 to M. In terms of the ratio, the capacitance ratio of the M constituent capacitors in the positive capacitor array 104 is 1:2:4:8 …:2 M-1 . Similarly, there is the same state in the negative-phase capacitor array 105. In terms of the ratio, the capacitance ratio of the M constituent capacitors in the negative-phase capacitor array 105 is also 1:2:4:8 …:2 M-1 。
The control of the digital logic signals Sp and Sn to the switch units 111-11M and 121-12M in the charge redistribution period can refer to the operation mode of the SAR ADC with the conventional differential architecture, and will not be repeated herein. By changing the switching states of the switching units 111 to 11M, 121 to 12M according to the comparison result Vcmp of the comparator 101, the SAR control circuit 103 can generate the digital conversion result ADR. It should be noted that the SAR ADC 10 of the present embodiment further includes specification selection circuits 102_1 and 102_2. The specification selection circuits 102_1 and 102_2 are described in detail with reference to the embodiment of fig. 1. In general, by controlling the control voltage Ctr1, the SAR ADC 10 can be operated in a first specification state and a second specification state different from each other under the constraint that the reference voltages Vrefp and Vrefn are fixed, so as to be suitable for receiving input voltages in different voltage ranges. Thus, the application range of the SAR ADC is wider.
In the process of considering the capacitor layout, the layout symmetry and layout manner of the capacitor array will directly affect the accuracy of the SAR ADC 10. In the embodiment of the present invention, the capacitors CA1 and CA2 are also formed on the substrate due to the arrangement of the specification selection circuits 102_1 and 102_2. However, if the unit capacitors forming the capacitors CA1, CA2 are arranged adjacent to the unit capacitors forming the capacitor array CA (e.g., the positive-phase capacitor array 104 and the negative-phase capacitor array 105), parasitic capacitance is generated between the unit capacitors forming the capacitors CA1, CA2 and the unit capacitors forming the capacitor array CA, thereby affecting the accuracy of the SAR ADC 10. In particular, when the switches SW1, SW2 are turned off, the bottom plates of the unit capacitors forming the capacitances CA1, CA2 will take on a floating (floating) state, and thus, the unit capacitors forming the capacitances CA1, CA2 will generate parasitic capacitances with the neighboring capacitors due to the voltage difference between the both ends of the neighboring capacitors. For example, assuming that the unit capacitor forming the capacitor CA1 is arranged adjacent to the unit capacitor forming the capacitor C11, a parasitic capacitance is generated between the unit capacitor forming the capacitor C11 and the unit capacitor forming the capacitor CA1, so that a voltage difference Δv is generated between the two ends of the capacitor CA 1. Similarly, the two ends of the capacitor CA2 will also generate a voltage difference Δv due to parasitic capacitance. Based on the operation principle of the differential structure SAR ADC, the voltage difference Δv generated at the two ends of the capacitor CA1 and the voltage difference Δv generated at the two ends of the capacitor CA2 cannot be canceled. IN this way, the voltage difference between the first input terminal IN1 and the second input terminal IN2 of the comparator 101 will be enlarged by 2Δv due to the parasitic capacitance effect, thereby affecting the comparison result of the comparator 101. That is, the parasitic capacitance described above will affect the accuracy of SAR ADC 10. Accordingly, in the embodiment of the present invention, the redundant capacitor block is disposed between the unit capacitors constituting the capacitors CA1 and CA2 and the unit capacitors constituting the capacitor array CA.
Fig. 3 is a schematic layout diagram of a first capacitor array block, a redundant capacitor array block and a second capacitor array block according to an embodiment of the present invention. Referring to fig. 3, in the embodiment of the present invention, the constituent capacitors (e.g., the constituent capacitors C11 to C1M and the constituent capacitors C21 to C2M of fig. 2) are formed by a plurality of first unit capacitors. The first unit capacitors forming the constituent capacitors C11 to C1M may be integrally arranged on the substrate P1 to form the first capacitor block B1. The capacitances CA1, CA2 of the specification selection circuits 102_1, 102_2 are formed of a plurality of second unit capacitors. The second unit capacitors forming the capacitor CA1 may be integrally arranged on the substrate P1 to form a second capacitor block B2. The redundant capacitor block Z1 is disposed between the first capacitor block B1 and the second capacitor block B2, and the redundant capacitor block Z1 includes a plurality of redundant capacitors integrally arranged on the substrate P1, so that the first capacitor block B1 is not directly adjacent to the second capacitor block B2 on the substrate P1. In addition, the first unit capacitors forming the constituent capacitances C21 to C2M and the second unit capacitor forming the capacitance CA2 may be integrally arranged at another place on the substrate P1 in a similar manner to fig. 3. Similarly, the first unit capacitor forming the constituent capacitances C21 to C2M and the second unit capacitor forming the capacitance CA2 are not directly adjacent based on the barrier of the redundant capacitor. However, FIG. 3 is merely an exemplary embodiment. In other embodiments, the first capacitor blocks forming the constituent capacitors C11-C1M and the constituent capacitors C21-C2M and the second capacitor blocks forming the capacitors CA1, CA2 may be arranged in other ways, but a redundant capacitor block is present between the first capacitor block and the second capacitor block, which is not directly adjacent to the first capacitor block and the second capacitor block. The first unit capacitor, the second unit capacitor and the redundant capacitor may use Metal-Oxide-Metal (MOM) structure capacitors, but are not limited thereto. By such a layout, the existence of the redundant capacitor block Z1 can prevent the first capacitor block B1 from generating a parasitic capacitance which cannot be ignored with the second capacitor block B2.
In more detail, fig. 4A is a schematic diagram of a redundancy capacitor constituting a redundancy capacitor according to an embodiment of the present invention. Fig. 4B is a schematic layout diagram of a first capacitor array block, a redundant capacitor array block and a second capacitor array block according to an embodiment of the invention. Referring to fig. 4A and 4B, the top plate 40 of the redundancy capacitor DC is coupled to the reference voltage Vref1, and the bottom plate 41 of the redundancy capacitor DC is coupled to the ground GND. That is, there is a fixed voltage difference between the bottom plate 41 and the top plate 40 of each redundancy capacitor DC.
The constituent capacitors in the capacitor array CA are formed by a plurality of first unit capacitors CU1, and the first unit capacitors CU1 are integrally arranged on the substrate P2 to form a first capacitor block B3. The capacitors CA1 and CA2 of the specification selection circuits 102_1 and 102_2 are formed by a plurality of second unit capacitors CU2, and the second unit capacitors CU2 are integrally arranged on the substrate P2 to form a second capacitor block B4. The redundant capacitor block Z2 is disposed between the first capacitor block B3 and the second capacitor block B4, and the redundant capacitor block Z2 includes a plurality of redundant capacitors DC integrally arranged on the substrate P2, so that the first capacitor block B3 is not directly adjacent to the second capacitor block B4 on the substrate P2. In addition, a plurality of other redundancy capacitors DC' are disposed at the periphery of the first capacitor block B3, the second capacitor block B4 and the redundancy capacitor block Z2. Therefore, although the bottom plates of the second unit capacitors CU2 forming the capacitors CA1 and CA2 are floating, parasitic capacitance is generated between the second unit capacitor CU2 and the redundancy capacitor DC at the edge of the second capacitor block B4, and the interference effect caused by the parasitic capacitance is negligible. The reason is that the parasitic capacitance generated between the second unit capacitor CU2 and the redundancy capacitor DC does not undesirably enlarge the voltage difference between the first input terminal IN1 and the second input terminal IN2 of the comparator 101.
In summary, in the embodiments of the present invention, by setting the specification selection circuit, the SAR ADC of the embodiments of the present invention can be adapted to receive the analog input voltage corresponding to the first voltage range or the analog input voltage corresponding to the second voltage range based on the on or off of the switch in the specification selection circuit when receiving the fixed reference voltage. Therefore, the application range of the SAR ADC is wider, and the circuit area can be further saved. In addition, compared with the arrangement without the residual capacitor block, the layout with the redundant capacitor block can effectively reduce the interference generated by parasitic capacitance, so that the SAR ADC of the embodiment of the invention can have better signal-to-noise and distortion ratio (SNNR) characteristics.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.
Claims (6)
1. A successive approximation analog-to-digital converter comprising:
the comparator is provided with a first input end, a second input end and an output end, and is used for comparing the input of the first input end and the second input end and outputting a comparison result to the output end;
a capacitor array coupled to the comparator and including a plurality of constituent capacitors;
a switch array coupled to the capacitor array; and
a specification selection circuit coupled to the comparator and the capacitor array, comprising a switch and a capacitor for receiving a common voltage,
wherein the continuous analog-to-digital converter operates in a first specification state in response to the switch of the specification selection circuit being turned on and in a second specification state in response to the switch of the specification selection circuit being turned off.
2. The continuous analog-to-digital converter of claim 1, wherein the constituent capacitors are formed by a plurality of first unit capacitors integrally arranged on a substrate to form a first capacitor block, the capacitors of the specification selection circuit are formed by a plurality of second unit capacitors integrally arranged on the substrate to form a second capacitor block,
the first capacitor block is arranged on the substrate, and the second capacitor block is arranged on the substrate.
3. The continuous analog-to-digital converter of claim 2, wherein top plates of the redundant capacitors are coupled to a reference voltage and bottom plates of the redundant capacitors are coupled to ground.
4. The continuous analog-to-digital converter of claim 1, wherein the switch of the specification selection circuit comprises a control terminal, a first terminal and a second terminal, the control terminal of the switch is coupled to a control voltage, the first terminal of the switch is coupled to the common voltage, the second terminal of the switch is coupled to one terminal of the capacitor of the specification selection circuit, and the other terminal of the capacitor of the specification selection circuit is coupled to the comparator.
5. The continuous-approximation analog-to-digital converter of claim 1, wherein the capacitor array comprises a positive phase capacitor array and a negative phase capacitor array, the switch array comprising a positive phase switch array and a negative phase switch array, the positive phase capacitor array being coupled between the positive phase switch array and the first input of the comparator, the negative phase capacitor array being coupled between the negative phase switch array and the second input of the comparator.
6. The continuous-approximation analog-to-digital converter of claim 1, wherein the continuous-approximation analog-to-digital converter is adapted to receive a first input voltage within a first voltage range when operating in the first specification state, and to receive a second input voltage within a second voltage range when operating in the second specification state, wherein the first voltage range is different from the second voltage range.
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| Publication number | Priority date | Publication date | Assignee | Title |
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