CN104716961A - Successive-approximation type analog-digital converter - Google Patents
Successive-approximation type analog-digital converter Download PDFInfo
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Abstract
The invention discloses a successive-approximation type analog-digital converter. The successive-approximation type analog-digital converter comprises a digital analogy switching circuit, a sample and hold circuit, a comparison circuit and a successive-approximation type logic control circuit. The digital analogy switching circuit is used for converting a N digits digital logic signal into a comparison signal, wherein the N is a positive integer; the sample and hold circuit is used for sampling and holding an analogy input signal; the comparison circuit is used for making the analogy input signal held by the sample and hold circuit as a standard to compare with the comparison signal, and the comparison signal is generated in this way; the successive-approximation type logic control circuit is used for providing the N digits digital logic signal and determining the logic state of each digit of the digital logic signal according to a comparative result signal one by one, and a digital output signal relevant to the analogy input signal is generated in this way.
Description
Technical field
The present invention relates to a kind of analog-digital converter (analog-to-digital converter, ADC), and in particular to a kind of successive approximation analog-digital converter (successive approximationregister analog-to-digital converter, SAR-ADC).
Background technology
Trend in recent years in integrated circuit (IC) design, for more low-power consumption, higher performance, and less cost has more and more harsh requirement, and in the middle of the design of analog front circuit, an efficient analog-digital converter (analog-to-digital converter, be called for short ADC) entire system performance can be made to promote widely, ADC is responsible for the analog signal of reception to be converted to digital signal, and the digital signal processing unit being supplied to rear end operates, therefore its dynamic range, resolution, accuracy, the linearity, sample rate, power consumption, input stage characteristic etc., all become the important step of influential system general performance, also the important parameter of assessment transducer performance itself is become.
The framework of existing ADC is of a great variety, such as pipe line analog-digital converter (pipelineanalog-to-digital converter, be called for short pipeline ADC) and successive approximation analog-digital converter (successive approximation register analog-to-digital converter is called for short SAR-ADC) etc. be all framework conventional in prior art field.Wherein, under same specification demands, SAR-ADC can have the advantage of lower power consumption and less chip area compared to pipeline ADC, also therefore, for the technological development of SAR-ADC framework, also gradually by industry is paid attention to.
Under the framework of existing SAR-ADC, it generally can include the parts such as digital analog converter (digital-to-analog converter is called for short DAC), comparison circuit and SAR logic control circuit.Specifically, in the Analog-digital Converter operating process of traditional SAR-ADC, DAC generally first can carry out sampling using a reference voltage as benchmark to analog input signal and keep (sample-and-hold), thereafter SAR logic control circuit can carry out the digital-to-analogue conversion of control DAC with binary search algorithm (binarysearch algorithm), to make DAC produce corresponding comparison signal, wherein said comparison signal is associated with the corresponding analog voltage of Different Logic state and the voltage difference of analog input signal.Then, comparison circuit can come using described reference voltage as benchmark compare with described comparison signal, thus make SAR logic control circuit based on the comparison circuit comparative result and determine each logic state of digital output signal one by one.
From aforesaid operations process, under existing SAR-ADC framework, in order to realize Analog-digital Converter operation, benchmark that comparator compares is necessary to provide an extra reference voltage to be used as.In addition, in order to the accuracy that comparison circuit judges will be maintained, generally during SAR-ADC carries out before Analog-digital Converter, advanced line displacement the operation of (offset cancellation) can be eliminated.In this operation, equally also must provide a reference voltage to two inputs of comparison circuit as common mode reference voltage (common-mode voltage) with the variation between the different inputs eliminating comparison circuit.
Moreover based under existing SAR-ADC framework, general comparison circuit is all utilize the comparator be made up of single operational amplifier to realize.Therefore, when circuit operation is in high frequency, comparator also may cause SAR-ADC that comparatively serious noise jamming occurs because required operating current is comparatively large.
Summary of the invention
The invention provides a kind of successive approximation analog-digital converter, it need not use extra reference voltage also can realize the operation of Analog-digital Converter and skew elimination, and can reduce the noise jamming of circuit operation when high frequency.
Successive approximation analog-digital converter of the present invention comprises D/A conversion circuit, sample-and-hold circuit, comparison circuit and successive approximation logic control circuit.D/A conversion circuit is used for comparison signal N bit digital logical signal being converted to analog form, and wherein N is positive integer.Sample-and-hold circuit is used for sampling and keeping analog input signal.Comparison circuit couples D/A conversion circuit and sample-and-hold circuit, for the analog input signal that kept by sample-and-hold circuit as the benchmark compared with comparison signal, thus produces compare result signal.Successive approximation logic control circuit is used for providing N bit digital logical signal, and determines the logic state of each of digital logic signal one by one according to compare result signal, to produce the digital output signal being associated with analog input signal.
In an embodiment of the present invention, comparison circuit comprises the comparing unit and latch lock unit that M level is connected in series mutually.First order comparing unit receives analog input signal and comparison signal from sample-and-hold circuit and D/A conversion circuit respectively.Latch lock unit couples the output of M level comparing unit, for the comparative result of comparing unit multiple described in breech lock, and produces compare result signal according to this.Wherein, M is positive integer, and M is at least 1/4th of N.
In an embodiment of the present invention, comparison circuit also comprises M group feedback unit and M group capacitor cell.Between the input that described M group feedback unit is respectively coupled to every one-level comparing unit and output.Described M group capacitor cell couples the input of every one-level comparing unit respectively.
In an embodiment of the present invention, each comparing unit has differential output, and the positive output end of every one-level comparing unit and negative output terminal couple positive input terminal and the negative input end of next stage comparing unit respectively.Each feedback unit comprises the first feedback switch and the second feedback switch.Between the positive input terminal that first feedback switch is coupled to corresponding comparing unit and positive output end.Between the negative input end that second feedback switch is coupled to corresponding comparing unit and negative output terminal.Wherein, first and second feedback switch is controlled by successive approximation logic control circuit and conducting or cut-off.
In an embodiment of the present invention, each capacitor cell comprises the first input capacitance and the second input capacitance.First input capacitance couples the positive input terminal of corresponding comparing unit.Second input capacitance couples the negative input end of corresponding comparing unit.
In an embodiment of the present invention, successive approximation logic control circuit during sampling keeps in first and second feedback switch of multiple feedback unit described in conducting, and during Charge scaling, end first and second feedback switch of described multiple feedback unit.
In an embodiment of the present invention, sample-and-hold circuit comprises the first sampling switch, the second sampling switch and holding capacitor.The first end of the first sampling switch receives analog input signal, and the second end of the first sampling switch couple the positive input terminal of first order comparing unit and negative input end one of them.The first end of the second sampling switch receives analog input signal, and the second end of the second sampling switch couples the positive input terminal of first order comparing unit and negative input end wherein another.The first end of holding capacitor couples the second end of the second sampling switch, and the second end of holding capacitor couples earth terminal.
In an embodiment of the present invention, successive approximation logic control circuit sampling keep during in first and second sampling switch of conducting, to make analog input signal be held in holding capacitor, and during Charge scaling, end first and second sampling switch.
In an embodiment of the present invention, D/A conversion circuit comprises N number of electric capacity and N number of switch module.The first end of described multiple electric capacity couples the second end of the first sampling switch jointly.Described N number of switch module couples the second end of described multiple electric capacity respectively, optionally provides high logic voltage, low logic voltage and analog input signal one of them electric capacity to correspondence for being controlled by successive approximation logic control circuit.
In an embodiment of the present invention, described multiple switch module during sampling keeps in be controlled by successive approximation logic control circuit and provide analog input signal to corresponding electric capacity, and be sequentially controlled by during Charge scaling digital logic signal each logic state and provide high logic voltage or low logic voltage to corresponding electric capacity, to produce comparison signal.
In an embodiment of the present invention, first electric capacity is sequentially 2N-1 to 20 to the capacitance ratio of N number of electric capacity, and the highest order of N bit digital logical signal (most significant bit, MSB) first switch module is controlled to N number of switch module to sequentially corresponding in lowest order (least significant bit, LSB) is during Charge scaling.
Based on above-mentioned, the embodiment of the present invention proposes a kind of successive approximation analog-digital converter, it can only utilize analog input signal to be used as Analog-digital Converter and the common mode reference voltage needed for operating is eliminated in skew, therefore the successive approximation analog-digital converter of the embodiment of the present invention need not use extra reference voltage to realize the operation of skew elimination and Analog-digital Converter, thus simplifies design of integer electro-circuit.In addition, pass through the comparison circuit framework of proposed serial connection comparing unit, also effectively can reduce noise jamming when successive approximation analog-digital converter operates in high frequency, thus make the successive approximation analog-digital converter of the embodiment of the present invention can have better signal to noise ratio characteristic.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the successive approximation analog-digital converter of one embodiment of the invention;
Fig. 2 is the schematic diagram of the successive approximation analog-digital converter of another embodiment of the present invention;
Fig. 3 is the schematic diagram of the successive approximation analog-digital converter of further embodiment of this invention;
Fig. 4 is the signal sequence schematic diagram of the successive approximation analog-digital converter according to Fig. 3 embodiment.
[description of reference numerals]
100,200,300: successive approximation analog-digital converter
110,210,310: D/A conversion circuit
120,220,320: sample-and-hold circuit
130,230,330: comparison circuit
140,240,340: successive approximation logic control circuit
212_1 ~ 212_N, 312_1 ~ 312_12: switch module
222,224,322,324: sampling switch
232_1 ~ 232_M, 332_1 ~ 332_3: comparing unit
234,334: latch lock unit
236_1 ~ 236_M, 336_1 ~ 336_3: feedback unit
238_1 ~ 238_M, 338_1 ~ 338_3: capacitor cell
C1 ~ CN, C12: electric capacity
C11, C12, C21, C22, C31, C32: input capacitance
Ch: holding capacitor
CHG, CHGB, EOC, LAT: control signal
DOUT: digital output signal
Fclk: frequency signal
GND: earth terminal
INV: inverter
SW1 ~ SW4: switch
SWF11, SWF12, SWF21, SWF22, SWF31, SWF32: feedback switch
VC: comparison signal
VCMP: compare result signal
VH: logic high voltage
VL: logic low-voltage
VIN: analog input signal
Q [N], Q [12]: digital logic signal
Q [1] ~ q [N], q [12]: position
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
The embodiment of the present invention proposes a kind of successive approximation analog-digital converter, it can under not needing to use the prerequisite of extra reference voltage as common mode reference voltage (common-mode voltage), realize the operation that (offset cancellation) and Analog-digital Converter are eliminated in skew, to simplify design of integer electro-circuit.In addition, pass through proposed circuit framework and also effectively can reduce the noise jamming of circuit operation when high frequency, thus make the analog-digital converter of the embodiment of the present invention can have better signal to noise ratio (signal-to-noise ratio, SNR) characteristic.In order to make content of the present invention more easily be understood, below especially exemplified by the example that embodiment can be implemented really according to this as the present invention.In addition, all may part, in graphic and execution mode, use the element/component/step of same reference numerals, represent identical or like.
Fig. 1 is the schematic diagram of the successive approximation analog-digital converter of one embodiment of the invention.Please refer to Fig. 1, the successive approximation analog-digital converter (being called for short SAR-ADC below) 100 of the present embodiment is suitable for a digital output signal DOUT analog input signal VIN being converted to a N bit resolution, and wherein N is positive integer (is such as 4,12 or 16 etc.).SAR-ADC100 comprises D/A conversion circuit (being called for short DAC-circuit below) 110, sample-and-hold circuit 120, comparison circuit 130 and successive approximation logic control circuit (being called for short SAR logic control circuit below) 140.
In the present embodiment, DAC-circuit 110 is for being converted to the comparison signal VC of analog form by the N received from SAR logic control circuit 140 bit digital logical signal Q [N].Sample-and-hold circuit 120 is for sampling and keeping analog input signal VIN.Comparison circuit 130 couples DAC-circuit 110 and sample-and-hold circuit 120, for the analog input signal VIN that kept by sample-and-hold circuit 120 as the benchmark compared with comparison signal VC, thus produces compare result signal VCMP.The compare result signal VCMP that SAR logic control circuit 140 can export according to comparison circuit 130 determines the logic state of each of digital logic signal Q [N] one by one, to produce the digital output signal DOUT being associated with analog input signal VIN.
Specifically, the operation of the Analog-digital Converter of SAR-ADC100 can be divided into two period/stage, be respectively sampling and keep (sample-and-hold) period and Charge scaling (charge-redistribution) period.During sampling keeps, DAC-circuit 110 and sample-and-hold circuit 120 can be controlled by SAR logic control circuit 140 and carry out sampling and keep the action of analog input signal VIN, and analog input signal VIN can be provided to two inputs of comparison circuit 130 in the mode of common mode, thus making comparison circuit 130 can carry out offseting the operation eliminated, the common-mode gain with seasonal comparison circuit 130 can be initialized to 0.
After terminating during sampling keeps, during SAR-ADC100 successively can enter Charge scaling.During Charge scaling, SAR logic control circuit 130 can adopt binary search algorithm to determine the logic state of each (this part can further illustrate in subsequent embodiment) of digital logic signal Q [N] one by one, makes DAC-circuit 110 produce voltage quasi position and progressively levels off to the comparison signal VC of analog input signal VIN.In digital logic signal Q [N] each all through SAR logic control circuit 140 according to compare result signal VCMP after adjusting, SAR logic control circuit 140 terminates during namely judging Charge scaling, and produces digital output signal DOUT based on the logic state of final digital logic signal Q [N].
Concrete framework and the operation of the SAR-ADC of the further description embodiment of the present invention is come below with Fig. 2 embodiment.Wherein, Fig. 2 is the schematic diagram of the SAR-ADC of another embodiment of the present invention.
Please refer to Fig. 2, the SAR-ADC200 of the present embodiment comprises DAC-circuit 210, sample-and-hold circuit 220, comparison circuit 230 and SAR logic control circuit 240.Wherein, DAC-circuit 210 comprises N number of electric capacity C1 ~ CN and N number of switch module 212_1 ~ 212_N.Sampling keeping unit 220 comprises sampling switch 222,224 and holding capacitor Ch.Comparison circuit 230 comprises comparing unit 232_1 ~ 232_M, latch lock unit 234, M group feedback unit 236_1 ~ 236_M and the M group capacitor cell 238_1 ~ 238_M that M level is connected in series mutually, and wherein M is positive integer.
In DAC-circuit 210, the first end of electric capacity C1 ~ CN couples the sampling switch 222 of sample-and-hold circuit 220 jointly.Wherein, the capacitance ratio of electric capacity C1 to electric capacity CN sequentially can be designed to 2N-1 to 20.For example, if the capacitance of electric capacity C1 is designed to C, then electric capacity C2, C3 ... the capacitance of CN can sequentially be designed to C/2, C/4 ..., C/2N-1, by that analogy.Second end of switch module 212_1 ~ 212_N difference coupling capacitance C1 ~ CN, and optionally provide high logic voltage VH, low logic voltage VL and analog input signal VIN one of them electric capacity C1 ~ CN to correspondence for being controlled by SAR logic control circuit 240.Wherein, high logic voltage VH and low logic voltage VL is the analog input interval (that is, the level of analog input signal VIN can between VH and VL) of SAR-ADC200.
In the present embodiment, digital logic signal Q [N] for controlling DAC-circuit 210 can be made up of position q [1] ~ q [N], at this, position q [1] is sequentially respectively highest order (the most significant bit of digital logic signal Q [N] to q [N], MSB) to lowest order (least significant bit, LSB).Wherein, each q [1] ~ q [N] can be considered as in during Charge scaling respectively for controlling the control signal of corresponding switch module 212_1 ~ 212_N.In other words, the highest order q [1] to lowest order q [N] of N bit digital logical signal Q [N] understands the switching of sequentially corresponding control switch module 212_1 ~ 212_N in during Charge scaling.For example, in during Charge scaling, switch module 212_1 ~ 212_N sequentially can react on high logic level (such as, logic level " 1 ") position q [1] ~ q [N] and select provide high logic voltage VH to the electric capacity C1 ~ CN of correspondence, and react on position q [the 1] ~ q [N] of low logic level (such as, logic level " 0 ") and select to provide low logic voltage VL to the electric capacity C1 ~ CN of correspondence.
Further for the SAR-ADC200 of 4 (namely, N=4), in during Charge scaling, if the digital logic signal Q [N] that SAR logic control circuit 240 provides is " 1000 ", then represent first/highest order q [1] counterlogic level " 1 ", second q [2] counterlogic level " 0 ", the 3rd q [3] counterlogic level " 0 " and the 4th/lowest order q [4] counterlogic level " 0 ".Based under above-mentioned logic state, switch module 212_1 can react on the position q [1] of logic level " 1 " and provide high logic voltage VH to the electric capacity C1 of correspondence, and switch module 212_2,212_3 and 212_4 then can react on position q [2], the q [3] of logic level " 0 " and q [4] and provide low logic voltage VL to electric capacity C2, C3 and C4 of correspondence.Therefore, under this configuration, it is in parallel that DAC-circuit 210 can be equivalent to electric capacity C2, C3 and C4, and the voltage quasi position of the comparison signal VC that DAC-circuit 210 produces can the result after the pressure reduction to high logic voltage VH and low logic voltage VL carries out dividing potential drop according to electric capacity C1 and described shunt capacitance determine.
At this using concrete numerical value as example, if the capacitance ratio that high logic voltage VH is 3V, low logic voltage VL is 0V and electric capacity C1 ~ C4 is sequentially 1:1/2:1/4:1/8, when DAC-circuit 210 receives digital logic signal Q [N] that logic state is " 1000 ", electric capacity C2, C3 and C4 three can be equivalent to a shunt capacitance, and the capacitance ratio of described shunt capacitance and electric capacity C1 about slightly 1:1 (being actually 1:7/8 (1/2+1/4+1/8)).Under this configuration, electric capacity C1 has identical resistance value with described shunt capacitance is rough, make the high logic voltage VH of 3V after the dividing potential drop of electric capacity C1 and described shunt capacitance, produce the comparison signal VC that voltage quasi position is about 1.5V (i.e. 1/2VH).Operation/the function mode of the DAC-circuit 210 of 8,12 or all the other figure places all can be analogized by above-mentioned example, therefore does not repeat them here.
It is worth mentioning that at this, designer can consider based on its design and in DAC-circuit 210, increase by one group of capacitance redundancy (dummy) electric capacity identical with electric capacity CN and corresponding switch module (not illustrating), with make DAC-circuit 210 the comparison signal VC that changes out can and high logic voltage VH between there is the voltage relativeness of integral multiple, but the present invention is not as limit.
In sample-and-hold circuit 220, the first end of sampling switch 222 receives analog input signal VIN, and the second end of sampling switch 222 couple the first end of the electric capacity C1 ~ CN of DAC-circuit 210 and the positive input terminal of first order comparing unit 232_1 and negative input end one of them.The first end of sampling switch 224 receives analog input signal VIN equally, and the second end of sampling switch 224 couples the positive input terminal of first order comparing unit 232_1 and negative input end wherein another.The first end of holding capacitor Ch couples the second end of sampling switch 224, and second end of holding capacitor Ch couples earth terminal GND (0V).Wherein, sampling switch 222 and 224 synchronously can be controlled by the control signal CHG and conducting or cut-off that SAR logic control circuit 240 provides.
In comparison circuit 230, comparing unit 232_1 ~ 232_M can be such as the comparing unit of tool differential output, wherein the positive output end of every one-level comparing unit 232_1 ~ 232_M and negative output terminal can be respectively coupled to positive input terminal and the negative input end of next stage comparing unit 232_1 ~ 232_M, such as: the positive output end of comparing unit 232_1 and negative output terminal can be respectively coupled to positive input terminal and the negative input end of comparing unit 232_2.Latch lock unit 234 couples the output of afterbody (M level) comparing unit 232_M, it can be used for the comparative result of breech lock comparing unit 232_1 ~ 232_M, and produces the compare result signal VCMP of the voltage relativeness of instruction comparison signal VC and analog input signal VIN according to this.Between the input that feedback unit 236_1 ~ 236_M is respectively coupled to every one-level comparing unit 232_1 ~ 232_M and output.Capacitor cell 238_1 ~ 238_M is then the input being coupled in every one-level comparing unit 232_1 ~ 232_M respectively.
With regard to the Analog-digital Converter operation of SAR-ADC200 entirety, first, in during sampling keeps, SAR logic control circuit 240 can provide the control signal CHG of activation to come the sampling switch 222 and 224 in conducting sample-and-hold circuit 220 and the feedback unit 236_1 ~ 236_M corresponding to comparing unit 232_1 ~ 232_M at different levels, and reacts on the control signal CHG of activation with seasonal each switch module 212_1 ~ 212_N and select to provide analog input signal VIN to the electric capacity C1 ~ CN of correspondence.
Under this configuration, analog input signal VIN can be provided to two inputs of first order comparing unit 232_1 in the mode of common mode, and the sampling switch 224 of conducting charges to holding capacitor Ch together with seasonal analog input signal VIN, be held in holding capacitor Ch to make analog input signal VIN.In addition, feedback unit 236_1 ~ the 236_M of conducting can set up the feedback path of short circuit between the input of comparing unit 232_1 ~ 232_M at different levels and output, make analog input signal VIN can be provided to the input/output of every one-level comparing unit 232_1 ~ 232_M via capacitor cell 238_1 ~ 238_M and feedback unit 236_1 ~ 236_M, thus eliminate the offset voltage of comparing unit 232_1 ~ 232_M at different levels, and the common-mode gain of comparing unit 232_1 ~ 232_M at different levels is initialized to 0 simultaneously.
During Charge scaling, control signal CHG can be switched to forbidden energy by SAR logic control circuit 240, sampling switch 222 and 224 and feedback unit 236_1 ~ 236_M are ended, and position q [1] ~ q [N] corresponding in making each switch module 212_1 ~ 212_N change into being controlled by digital logic signal Q [N] and determine to provide logic high voltage VH or logic low-voltage VL to the electric capacity C1 ~ CN of correspondence.
Under this configuration, SAR logic control circuit 240 can first provide one group of digital logic signal Q [N] with default logic state to control DAC-circuit 210.For N=4, under binary search algorithm, the digital logic signal Q [N] of the acquiescence that SAR logic control circuit 240 provides is general is such as " 1000 " or " 0111 " (that is, corresponding to the logic state of 1/2nd logic high voltage VH, but the present invention is not limited only to this).Then, comparing unit 232_1 ~ 232_M can signal VC and sample-and-hold circuit 220 keep based on the comparison analog input signal VIN compare step by step, thus makes latch lock unit 234 produce corresponding compare result signal VCMP according to the comparative result of afterbody comparing unit 232_M.
Now, according to this compare result signal VCMP (corresponding to the comparison signal VC of acquiescence and the comparative result of analog input signal VIN), SAR logic control circuit 240 can determine that the logic state of highest order/the first q [1] is logic level " 1 " or " 0 ", and adjust the logic state of next bit q [2].Then, DAC-circuit 210 successively can produce corresponding comparison signal VC according to the digital logic signal Q [N] after adjustment and come to compare with analog input signal VIN, make SAR logic control circuit 240 determine the logic state of next bit q [2] again according to the compare result signal VCMP of the comparative result of corresponding this comparison signal VC and analog input signal VIN, and adjust the logic state of next bit q [3] again.By aforesaid operation, SAR logic control circuit 240 can during Charge scaling in sequentially determine the logic state of each q [1] ~ q [N].
More particularly, in the operation of logic state determining each q [1] ~ q [N] one by one, DAC-circuit 210 can be adjusted by the logic state of highest order q [1] to lowest order q [N] along with digital logic signal Q [N] and produce and progressively level off to the comparison signal VC of voltage quasi position of analog input signal VIN.In other words, (determined the logic state of lowest order q [N]) at the end of during Charge scaling, the digital logic signal Q [N] that 240 decodings of SAR logic control circuit go out is the digital output signal DOUT corresponding to analog input signal VIN.
From the concrete operations flow process of above-mentioned SAR-ADC200, by the configuration of the sample-and-hold circuit 220 of the embodiment of the present invention, SAR-ADC200 can during sampling keeps in the utilization analog input signal VIN that is simultaneously provided to the positive/negative input of comparing unit 232_1 ~ 232_M at different levels be used as the common mode reference voltage of the offset voltage for eliminating comparing unit 232_1 ~ 232_M at different levels.In addition, can be maintained in holding capacitor Ch constantly in analog input signal VIN is during Charge scaling, therefore comparison circuit 230 can directly using the analog input signal VIN be held in holding capacitor Ch as the benchmark compared with comparison signal VC, and same without the need to comparing based on extra reference voltage.
In other words, compared to traditional SAR-ADC, the SAR-ADC200 of the embodiment of the present invention under the prerequisite that need not use extra reference voltage, can realize the operation carrying out offseting elimination and Analog-digital Converter to comparison circuit 230.
On the other hand, in the present embodiment, the magnitude setting of comparing unit 232_1 ~ 232_M is figure place N based on SAR-ADC200 and determines.More particularly, M can at least equal 1/4th of N.For example, if SAR-ADC200 is designed to 4 bit resolutions (that is, N=4), then need to arrange the comparing unit 236_1 (that is, M >=1) of at least one-level in comparison circuit 230; If SAR-ADC200 is designed to 8 bit resolutions (that is, N=8), then need to arrange comparing unit 236_1 ~ 236_2 (that is, M >=1) that at least two-stage is connected in series mutually in comparison circuit 230, all the other all can be by that analogy.
Configured by the comparing unit 232_1 ~ 232_M of described multi-stage serial connection, because the gain of overall comparison circuit 230 can be disperseed by comparing unit 232_1 ~ 232_M at different levels, therefore comparing unit 232_1 ~ 232_M at different levels only can need be operated on its operating point with less current drives well.Base this, compared to the comparison circuit that single comparator is formed, even if also serious noise jamming can not be caused because operating current is too high when the comparing unit 232_1 ~ 232_M of the present embodiment operates in high frequency.
Be described further with the physical circuit framework of the SAR-ADC300 of 12 as shown in Figure 3 below.Wherein, Fig. 3 is the schematic diagram of the SAR-ADC of further embodiment of this invention.
Please refer to Fig. 3, in the present embodiment, the SAR-ADC300 (that is, N=12) of 12 comprises DAC-circuit 310, sample-and-hold circuit 320, comparison circuit 330 and SAR logic control circuit 340.Wherein, DAC-circuit 310 comprises the capacitor array that 12 electric capacity C1 ~ C12 form and the switch module 312_1 ~ 312_12 distinguishing corresponding described electric capacity C1 ~ C12.Comparison circuit 330 comprises feedback unit 336_1 ~ 336_3 and the capacitor cell 338_1 ~ 338_3 of three grades of comparing unit 332_1 ~ 332_3 (that is, M=3) be mutually connected in series, latch lock unit 334 and the corresponding comparing unit 332_1 ~ 332_3 at different levels of difference.In addition, the concrete framework of sample-and-hold circuit 320 is similar to previous embodiment, comprises sampling switch 322 and 324 and holding capacitor Ch.
Specifically, in the DAC-circuit 310 of the present embodiment, each switch module 312_1 ~ 312_12 can utilize the circuit framework be made up of multiple switch and inverter to realize.At this for switch module 312_1, switch module 312_1 comprises interrupteur SW 1 ~ SW4 and inverter INV.Second end of the common coupling capacitance C1 of first end of interrupteur SW 1 and SW2, the second termination of interrupteur SW 2 receives analog input signal VIN, and the control end of interrupteur SW 1 and SW2 reception control signal CHGB and CHG respectively, wherein control signal CHGB and CHG is anti-phase each other.Interrupteur SW 3 couples the second end of interrupteur SW 1 jointly with the first end of SW4, interrupteur SW 3 receives low logic voltage VL and high logic voltage VH respectively with second end of SW4, wherein the control end of interrupteur SW 4 is controlled by the logic state of the position q [1] of digital logic signal Q [12] and conducting or cut-off, and the control end of interrupteur SW 3 is controlled by the logic state of a q [1] and conducting or cut-off via inverter INV.In other words, alternate conduction in a complementary fashion can be distinguished between interrupteur SW 1 and SW2 and between interrupteur SW 3 and SW4, to realize optionally providing analog input signal VIN, high logic voltage VH and low logic voltage VL one of them function.The concrete framework of rest switch module 312_2 ~ 312_12 is similar to switch module 312_1, therefore does not repeat them here.
In the comparison circuit 330 of the present embodiment, feedback unit 336_1 comprises feedback switch SWF11 and SWF12, and feedback unit 336_2 comprises feedback switch SWF21 and SWF22, and feedback unit 336_3 comprises feedback switch SWF31 and SWF32.Wherein, between the positive input terminal that feedback switch SWF11, SWF21 and SWF31 are respectively coupled to corresponding comparing unit 332_1,332_2 and 332_3 and positive output end, and between feedback switch SWF12, SWF22 and SWF32 negative input end of being respectively coupled to corresponding comparing unit 332_1,332_2 and 332_3 and negative output terminal.
In addition, capacitor cell 338_1 comprises input capacitance C11 and C12, and capacitor cell 338_2 comprises input capacitance C21 and C22, and capacitor cell 338_3 comprises input capacitance C31 and C32.The first end of positive input terminal via electric capacity C11 coupling capacitance C1 ~ C12 of first order comparing unit 332_1 and the second end of sampling switch 322, and the negative input end of first order comparing unit 332_1 couples the second end of sampling switch 324 and the first end of holding capacitor Ch via electric capacity C12.The positive input terminal of second level comparing unit 332_2 and negative input end couple positive output end and the negative output terminal of first order comparing unit 332_1 respectively via input capacitance C21 and C22.The positive input terminal of third level comparing unit 332_3 and negative input end couple positive output end and the negative output terminal of second level comparing unit 332_2 respectively via input capacitance C31 and C32, and the positive output end of third level comparing unit 332_3 and negative output terminal are all coupled to latch lock unit 334.
Arrange in pairs or groups below Fig. 4 signal sequence to illustrate SAR-ADC300 entirety Analog-digital Converter operation.
Referring to Fig. 3 and Fig. 4, first with regard to SAR logic control circuit 340 each signal of receiving/exporting be described.In the present embodiment, frequency signal fclk is the reference frequency of SAR logic control circuit 340, wherein SAR logic control circuit 340 can go out a corresponding digital output signal DOUT in every 16 frequency periods (hereinafter referred to as a change-over period) decoding of frequency signal fclk, during wherein front 3 frequency periods are the sampling maintenance of SAR-ADC300, during then 13 frequency periods are then the Charge scaling of SAR-ADC300.Be with hexadecimal representation at this digital output signal DOUT, but the present invention is not limited only to this.Control signal LAT is the signal operated for controlling latch lock unit 334.Control signal EOC is then EOC (end ofconversion) signal being used to indicate Analog-digital Converter start/end, wherein digital output signal DOUT instantly when control signal EOC activation, can send by SAR logic control circuit 340.In addition, remaining control signal CHG and digital logic signal Q [12] all as previously mentioned.
Specifically, when SAR-ADC300 enters during sampling keeps based on the control signal EOC of activation, SAR logic control circuit 340 can provide the control signal CHG of activation to come conducting sampling switch 322 and 324 and feedback switch SWF11 ~ SWF32, and makes each switch module 312_1 ~ 312_12 react on the control signal CHG of activation and select to provide analog input signal VIN to corresponding electric capacity C1 ~ C12.
Under this configuration, the positive input terminal that analog input signal VIN can be simultaneously provided to comparing unit 332_1 ~ 332_3 at different levels via input capacitance C11 ~ C32 and feedback switch SWF11 ~ SWF32 and negative input end, to carry out comparing unit 332_1 ~ 332_3 at different levels offseting the operation eliminated, and the common-mode gain of comparing unit 332_1 ~ 332_3 at different levels is made to be initialized to 0.In addition, during this period, analog input signal VIN can charge to holding capacitor Ch, to be held in holding capacitor Ch by analog input signal VIN simultaneously.Wherein, the analog input signal that holding capacitor Ch keeps represents with VINh at this.
Then, after during entering Charge scaling, control signal CHG can be switched to forbidden energy by SAR logic control circuit 340, sampling switch 322 and 324 and feedback switch SWF11 ~ SWF32 are ended, and position q [1] ~ q [12] corresponding in making each switch module 312_1 ~ 312_12 change into being controlled by digital logic signal Q [N] and determine to provide logic high voltage VH or logic low-voltage VL to the electric capacity C1 ~ C12 of correspondence.In the present embodiment, the logic state that SAR logic control circuit 340 gives tacit consent to the digital logic signal Q [N] provided is for " 011111111111 ", and the voltage quasi position of logic high voltage VH, logic low-voltage VL and analog input signal VIN is respectively for 3V, 0V and 0.1V.
During Charge scaling, SAR logic control circuit 340 can control signal LAT 12 impulse durations based on the comparison consequential signal VCMP sequentially adjust first q [1] of digital logic signal Q [12] to the 12 q [12].More particularly, in first impulse duration of control signal LAT, DAC-circuit 310 can the logic-based state digital logic signal Q [12] that is " 011111111111 " and produce the comparison signal VC that voltage quasi position is about 1.5V, now comparison circuit 330 can judge that the voltage quasi position of comparison signal VC (1.5V) is greater than analog input signal VIN (0.1V), thus sends the compare result signal VCMP of activation.Therefore, first q [1] namely can be maintained logic level " 0 " according to the compare result signal VCMP of activation by SAR logic control circuit 340, and successively the logic state of second q [2] is adjusted to " 0 ".
Then, in second impulse duration of control signal LAT, DAC-circuit 310 can the logic-based state digital logic signal Q [12] that is " 001111111111 " and produce the comparison signal VC that voltage quasi position is about 0.75V, and comparison circuit 330 still can judge that the voltage quasi position of comparison signal VC (0.75V) is greater than analog input signal VIN (0.1V), thus again send the compare result signal VCMP of activation, SAR logic control circuit 340 is made second q [2] to be maintained equally logic level " 0 " according to the compare result signal VCMP of activation, and successively the logic state of the 3rd q [3] is adjusted to " 0 ".Thereafter, the logic level of every q [3] ~ q [12] is all sequentially determine according to aforesaid way, therefore does not repeat them here.
As shown in Figure 4, in 12 impulse durations of control signal LAT, comparison circuit 340 can sequentially produce the compare result signal VCMP that logic state is " 111110000011 ", and the logic state of digital logic signal Q [12] finally can be adjusted to " 000001111100 " by SAR logic control circuit 340.Base this, SAR logic control circuit 340 namely can control signal EOC again activation time, based on digital logic signal Q [12] logic state " 000001111100 " and send digital value for the digital output signal DOUT (hexadecimal) of " 07C ".That is the analog input signal VIN of 0.1V after a change-over period, can be converted to the digital output signal DOUT of digital value for " 07C " by SAR logic control circuit 340, thus completes Analog-digital Converter operation once.
It is worth mentioning that in addition, the control signal CHG of the present embodiment can be designed to switch to activation in advance (namely before entering the change-over period, the transition time point of control signal CHG and EOC is separated by one section of timing period), during to enter at SAR-ADC300 during sampling keeps, corresponding switch can by conducting immediately, thus carry out ahead of time offseting the operation eliminated, but the present invention is not as limit.
In sum, the embodiment of the present invention proposes a kind of SAR-ADC, it can only utilize analog input signal to be used as Analog-digital Converter and the common mode reference voltage needed for operating is eliminated in skew, therefore the SAR-ADC of the embodiment of the present invention need not use extra reference voltage to realize the operation eliminating offset voltage and Analog-digital Converter, thus simplifies design of integer electro-circuit.In addition, pass through the comparison circuit framework of proposed serial connection comparing unit, also effectively can reduce noise jamming when SAR-ADC operates in high frequency, thus make the SAR-ADC of the embodiment of the present invention can have better signal to noise ratio characteristic.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a successive approximation analog-digital converter, comprising:
One D/A conversion circuit, for a N bit digital logical signal being converted to the comparison signal of an analog form, wherein N is positive integer;
One sample-and-hold circuit, for sampling and keeping an analog input signal;
One comparison circuit, couples this D/A conversion circuit and this sample-and-hold circuit, for the analog input signal that kept by this sample-and-hold circuit as the benchmark compared with this comparison signal, thus produces a compare result signal; And
One successive approximation logic control circuit, for providing this N bit digital logical signal, and determines the logic state of each of this digital logic signal, one by one to produce the digital output signal being associated with this analog input signal according to this compare result signal.
2. successive approximation analog-digital converter as claimed in claim 1, it is characterized in that, this comparison circuit comprises:
The comparing unit that M level is connected in series mutually, wherein first order comparing unit receives this analog input signal and this comparison signal from this sample-and-hold circuit and this D/A conversion circuit respectively; And
One latch lock unit, couples the output of M level comparing unit, for the comparative result of comparing unit described in breech lock, and produces this compare result signal according to this,
Wherein, M is positive integer, and M is at least 1/4th of N.
3. successive approximation analog-digital converter as claimed in claim 2, it is characterized in that, this comparison circuit also comprises:
M group feedback unit, between the input being respectively coupled to every one-level comparing unit and output; And
M group capacitor cell, couples the input of every one-level comparing unit respectively.
4. successive approximation analog-digital converter as claimed in claim 3, it is characterized in that, respectively this comparing unit has differential output, and the positive output end of every one-level comparing unit and negative output terminal couple positive input terminal and the negative input end of next stage comparing unit respectively, and respectively this feedback unit comprises:
One first feedback switch, between the positive input terminal being coupled to corresponding comparing unit and positive output end; And
One second feedback switch, between the negative input end being coupled to corresponding comparing unit and negative output terminal,
Wherein, this first and second feedback switch is controlled by this successive approximation logic control circuit and conducting or cut-off.
5. successive approximation analog-digital converter as claimed in claim 4, it is characterized in that, respectively this capacitor cell comprises:
One first input capacitance, couples the positive input terminal of corresponding comparing unit; And
One second input capacitance, couples the negative input end of corresponding comparing unit.
6. successive approximation analog-digital converter as claimed in claim 4, it is characterized in that, this successive approximation logic control circuit during a sampling keeps in first and second feedback switch of feedback unit described in conducting, and during a Charge scaling, end first and second feedback switch of described feedback unit.
7. successive approximation analog-digital converter as claimed in claim 2, it is characterized in that, this sample-and-hold circuit comprises:
One first sampling switch, its first end receives this analog input signal, and its second end couple the positive input terminal of first order comparing unit and negative input end one of them;
One second sampling switch, its first end receives this analog input signal, and its second end couples the positive input terminal of first order comparing unit and negative input end wherein another; And
One holding capacitor, its first end couples the second end of this second sampling switch, and its second end couples an earth terminal.
8. successive approximation analog-digital converter as claimed in claim 7, it is characterized in that, this successive approximation logic control circuit one sampling keep during in this first and second sampling switch of conducting, to make this analog input signal be held in this holding capacitor, and during a Charge scaling, end this first and second sampling switch.
9. successive approximation analog-digital converter as claimed in claim 7, it is characterized in that, this D/A conversion circuit comprises:
N number of electric capacity, the first end of wherein said electric capacity couples the second end of this first sampling switch jointly; And
N number of switch module, couples the second end of described electric capacity respectively, optionally provides a high logic voltage, a low logic voltage and this analog input signal one of them electric capacity to correspondence for being controlled by this successive approximation logic control circuit.
10. successive approximation analog-digital converter as claimed in claim 9, it is characterized in that, described switch module during a sampling keeps in be controlled by this successive approximation logic control circuit and provide this analog input signal to corresponding electric capacity, and be sequentially controlled by during a Charge scaling this digital logic signal each logic state and provide this high logic voltage maybe this low logic voltage to corresponding electric capacity, to produce this comparison signal.
11. successive approximation analog-digital converters as claimed in claim 10, it is characterized in that, first electric capacity is sequentially 2N-1 to 20 to the capacitance ratio of N number of electric capacity, and the highest order of this N bit digital logical signal to minimum be positioned at this Charge scaling during sequentially correspondingly control first switch module to N number of switch module.
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