CN111294050A - High linearity cyclic asymptotic analog-to-digital converter - Google Patents
High linearity cyclic asymptotic analog-to-digital converter Download PDFInfo
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Abstract
A high linearity cyclic asymptotic analog-to-digital converter for generating n-bit conversion output includes a first capacitor digital-to-analog converter and a second capacitor digital-to-analog converter. One of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter having a larger output signal is defined as a higher voltage capacitor digital-to-analog converter, and the other one is defined as a non-switched capacitor digital-to-analog converter. In the m-th conversion stage, the m-1 th capacitor of the non-switched capacitor digital-to-analog converter is switched according to the comparison result of the output signals of the higher-voltage capacitor digital-to-analog converter and the non-switched capacitor digital-to-analog converter.
Description
Technical Field
The present invention relates to an analog-to-digital converter (ADC), and more particularly, to a cyclic-asymptotic analog-to-digital converter (SAR ADC).
Background
A successive approximation register (SAR ADC) is one type of analog-to-digital converter (ADC) for equivalently converting an analog signal into a digital signal. The successive approximation adc performs the conversion by comparing and searching through all possible quantization levels to obtain a digital output. Compared with a conventional analog-to-digital converter, the circular asymptotic analog-to-digital converter uses less circuit area and corresponding cost. Although the asymptotic adc consumes less power, the power consumption of the asymptotic adc is still too high for some electronic devices with limited power supplies. In addition, the conventional iterative asymptotic analog-to-digital converter has the disadvantages of non-linearity and capacitance mismatch.
Therefore, it is desirable to provide a novel successive approximation analog-to-digital converter with enhanced linearity, power consumption and capacitance matching.
Disclosure of Invention
In view of the foregoing, an objective of the embodiments of the present invention is to provide a cyclic asymptotic analog-to-digital converter with high linearity, low power consumption and enhanced capacitance matching.
The purpose of the invention is realized by adopting the following technical scheme.
The embodiment of the invention provides a cyclic asymptotic analog-to-digital converter for generating n-bit conversion output, which comprises a first capacitor digital-to-analog converter and a second capacitor digital-to-analog converter. In the sampling stage, all the capacitors of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter are switched to the common voltage. In the first conversion stage, the first most significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter. One of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter having a larger output signal is defined as a higher voltage capacitor digital-to-analog converter, and the other one is defined as a non-switched capacitor digital-to-analog converter. All capacitors of the higher voltage capacitance digital-to-analog converter are switched to ground, wherein the common voltage is between the power supply and the ground. In the mth conversion stage (1< m < n), the mth most significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter. And switching the (m-1) th capacitor of the non-switched capacitor digital-to-analog converter according to the comparison result of the output signals of the higher-voltage capacitor digital-to-analog converter and the non-switched capacitor digital-to-analog converter. In the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.
The object of the invention can be further achieved by the following technical measures.
Preferably, the high linearity cyclic asymptotic ADC comprises n-1 capacitors having capacitance values of 2n-3C, 2n-4C … 22C, 21C and 21C in sequence from 1 to n-1, wherein C is a default value.
Preferably, the aforementioned high linearity cyclic asymptotic ADC, wherein the second capacitive DAC comprises n-1 capacitors having capacitance values of 2n-3C, 2n-4C … 22C, 21C, and 21C in sequence from 1 to n-1, wherein C is a default value.
Preferably, the aforementioned high linearity cyclic asymptotic adc is configured to determine the first most significant bit of the conversion output to be "1" if the output signal of the first capacitor dac is greater than the output signal of the second capacitor dac, and to determine the first most significant bit to be "0" otherwise.
Preferably, the aforementioned high linearity cyclic asymptotic adc is configured to determine the mth most significant bit of the conversion output to be "1" if the output signal of the first capacitor dac is greater than the output signal of the second capacitor dac, and to determine the mth most significant bit to be "0" otherwise.
Preferably, the high linearity cyclic asymptotic adc is configured to switch the m-1 capacitor of the non-switched capacitor dac to ground if the output signal of the non-switched capacitor dac is greater than the output signal of the higher voltage capacitor dac, and to switch to power otherwise.
Preferably, the aforementioned high linearity cyclic asymptotic adc is configured such that if the output signal of the first capacitor dac is greater than the output signal of the second capacitor dac, the least significant bit of the conversion output is determined to be "1", otherwise, the least significant bit is determined to be "0".
Preferably, the high linearity iterative adc further comprises a detection and skipping algorithm based on the generated n-bit conversion output.
Preferably, in the high linearity successive approximation adc, in the sampling stage, the first capacitor dac samples a positive input signal, and the second capacitor dac samples a negative input signal.
Preferably, the high linearity cyclic asymptotic adc further comprises a comparator for receiving the output signal of the first capacitor dac and the output signal of the second capacitor dac.
The embodiment of the invention further provides a high-linearity successive approximation type analog-to-digital converter for generating n-bit conversion output, comprising a first capacitance digital-to-analog converter and a second capacitance digital-to-analog converter, wherein in a sampling phase, all capacitors of the first capacitance digital-to-analog converter and the second capacitance digital-to-analog converter are switched to a common voltage, in a first conversion phase, a first most significant bit of the conversion output is determined according to a comparison result of output signals of the first capacitance digital-to-analog converter and the second capacitance digital-to-analog converter, and one of the first capacitance digital-to-analog converter and the second capacitance digital-to-analog converter having a smaller output signal is defined as a lower voltage capacitance digital-to-analog converter, and the other one is defined as a non-switched capacitance digital-to-analog converter, switching all capacitors of the lower voltage DAC to the power source, wherein a common voltage is between the power source and ground, determining an mth most significant bit of the converted output according to a comparison result of output signals of the first and second capacitive DACs in an mth conversion stage (1< m < n), switching an m-1 capacitor of the non-switched capacitive DAC according to a comparison result of output signals of the lower voltage capacitive DAC and the non-switched capacitive DAC, and determining a least significant bit of the converted output according to a comparison result of output signals of the first and second capacitive DACs in an nth conversion stage.
Preferably, the aforementioned high-linearity asymptotic adc is configured to switch the m-1 capacitor of the non-switched capacitor dac to ground if the output signal of the non-switched capacitor dac is greater than the output signal of the lower-voltage capacitor dac, and to switch to the power supply otherwise.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 shows a block diagram of a high linearity and low power consumption cyclic asymptotic analog-to-digital converter (sar adc) according to an embodiment of the present invention.
Fig. 2A shows a circuit of the first capacitor digital-to-analog converter of fig. 1.
FIG. 2B shows a circuit of the second capacitive digital-to-analog converter of FIG. 1.
FIG. 3 is a flowchart illustrating a method of performing the iterative asymptotic ADC of FIG. 1 according to an embodiment of the present invention.
Fig. 4A to 9B illustrate the switching of the first and second capacitive digital-to-analog converters when the successive approximation-by-loop analog-to-digital converter is performed at different stages.
[ description of main element symbols ]
100 cycle progressive analog-to-digital converter
11A first capacitive digital-to-analog converter
11B second capacitance D/A converter
12: comparator
13, a cycle progressive controller
31 sampling stage
32 (conversion phase 1) switching all capacitors of a higher voltage capacitance digital-to-analog converter
33 (conversion phase m) switching the m-1 capacitor of the non-switched capacitance digital-to-analog converter
34 transition stage n
Vip first input signal
Vin is a second input signal
Vop first output signal
Von second output signal
Dout conversion output
Vdd, power supply
Vcm common voltage
Gnd, ground
C1-C4 capacitor
Cd capacitor
SWip first input switch
SWin second input switch
SW 1-SW 4 switch
Detailed Description
Fig. 1 shows a block diagram of a high linearity and low power consumption cyclic asymptotic analog-to-digital converter (SAR ADC)100 according to an embodiment of the present invention.
In the present embodiment, the successive approximation type analog-to-digital converter (hereinafter referred to as an analog-to-digital converter) 100 may include a first capacitor digital-to-analog converter 11A and a second capacitor digital-to-analog converter 11B, respectively receiving a first input signal Vip (e.g., a positive input signal) and a second input signal Vin (e.g., a negative input signal), for respectively generating a first output signal Vop (e.g., a positive output signal) and a second output signal Von (e.g., a negative output signal).
Second fig. 2A shows a circuit of the first capacitive digital-to-analog converter 11A of the first diagram. The ADC 100 of this embodiment may be n-bit, and the first capacitive DAC 11A may comprise an array of n-1 capacitors, including the first capacitor, the second capacitor … (n-1) th capacitor. In addition, the additional capacitor Cd is a stray (parasitic) capacitor, which is connected to ground and is not switchable. Among the n-1 capacitors, the capacitance value of the capacitor with the larger number (order number) is smaller than or equal to the capacitance value of the capacitor with the smaller number. For example, the capacitors numbered 1 to n-1 have capacitance values of 2n-3C, 2n-4C … 22C, 21C, and 21C, respectively, where C is a default value, and the last two capacitors have the same capacitance value. As illustrated in fig. 2A, the adc 100 is 5-bit, and the first capacitive dac 11A includes 4 capacitors C1-C4 having capacitance values of 4C, 2C, 1C, and 1C, respectively. A first plate (plate), e.g. an upper plate, of the n-1 capacitors may be connected to the first input signal Vip via a first input switch SWip. The second plates (e.g., lower plates) of all the capacitors can be switched to a common voltage (Vcm), which is located in the middle between Vdd and Gnd, a power supply Vdd, or ground Gnd, respectively, via corresponding switches (e.g., SW 1-SW 4).
Similarly, fig. 2B shows the circuit of the second capacitive digital-to-analog converter 11B of fig. 1. The ADC 100 of this embodiment may be an n-bit, and the second capacitive DAC 11B may comprise an array of n-1 capacitors, including the first capacitor and the (n-1) th capacitor of the second capacitor …. In addition, the additional capacitor Cd is a stray capacitor, which is connected to ground and is not switchable. Among the n-1 capacitors, the capacitance value of the capacitor with the larger number is smaller than or equal to the capacitance value of the capacitor with the smaller number. For example, the capacitors numbered 1 to n-1 have capacitance values of 2n-3C, 2n-4C … 22C, 21C, and 21C, respectively, where C is a default value, and the last two capacitors have the same capacitance value. As illustrated in fig. 2A, the adc 100 is 5-bit, and the second capacitive dac 11B includes 4 capacitors C1-C4 having capacitance values of 4C, 2C, 1C, and 1C, respectively. The first plates (e.g., upper plates) of the n-1 capacitors may be connected to a second input signal Vin via a second input switch SWin. The second plates (e.g., lower plates) of all the capacitors can be switched to a common voltage Vcm, which is located in the middle between Vdd and Gnd, a power supply Vdd, or ground Gnd, respectively, via corresponding switches (e.g., SW 1-SW 4).
Referring to fig. 1, the adc 100 of the present embodiment may include a comparator 12 (e.g., an operational amplifier) for receiving a first output signal Vop and a second output signal Von at a first input node (e.g., a positive (+) input node) and a second input node (e.g., a negative (-) input node) of the comparator 12, respectively. The adc 100 of the present embodiment may include a circular asymptotic controller 13, which generates a conversion output Dout according to the comparison output of the comparator 12. The progressive controller 13 further controls the switches (e.g., SW 1-SW 4) of the first capacitor dac 11A and the switches (e.g., SW 1-SW 4) of the second capacitor dac 11B according to the comparison output of the comparator 12.
Fig. 3 is a flowchart illustrating a method of performing the iterative asymptotic adc 100 of fig. 1 according to an embodiment of the present invention. Fig. 4A to 9B illustrate the switching of the first capacitor dac 11A and the second capacitor dac 11B when the successive approximation adc 100 is executed at different phases (phase). In the 5-bit adc 100 illustrated in fig. 4A to 9B, the capacitors C1 to C4 of the first capacitive dac 11A have capacitance values of 4C, 2C, 1C, and 1C, respectively, and the capacitors C1 to C4 of the second capacitive dac 11B have capacitance values of 4C, 2C, 1C, and 1C, respectively.
In the sampling phase of step 31, as shown in fig. 4A, the second plates of all the capacitors of the first capacitive digital-to-analog converter 11A are switched to the common voltage Vcm through the corresponding switches, and the second plates of all the capacitors of the second capacitive digital-to-analog converter 11B are switched to the common voltage Vcm through the corresponding switches. The first input switch SWip is closed to thereby switch the first plates of all the capacitors of the first capacitive digital-to-analog converter 11A to the first input signal Vip, and the second input switch SWin is closed to thereby switch the first plates of all the capacitors of the second capacitive digital-to-analog converter 11B to the second input signal Vin. Fig. 4B illustrates waveforms of the first output signal Vop and the second output signal Von. After the sampling stage (step 31) is completed, n conversion stages are sequentially performed to generate n bits of the converted output Dout, respectively.
In step 32 (transition phase 1), as shown in fig. 5A, the first input switch SWip and the second input switch SWin are turned on. The bits at the Most Significant Bit (MSB) (i.e., left-most bit) position of the converted output Dout are determined based on the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the first most significant bit position is determined to be "1", otherwise it is determined to be "0".
Then, it is determined which one of the first capacitive digital-to-analog converter 11A and the second capacitive digital-to-analog converter 11B is a higher-voltage (high-voltage) capacitive digital-to-analog converter according to the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the first capacitive dac 11A is determined to be a higher voltage capacitive dac, otherwise the second capacitive dac 11B is determined to be a higher voltage capacitive dac. The second plates of all capacitors of the higher voltage capacitance digital-to-analog converter (in this example the second capacitance digital-to-analog converter 11B) are switched (from the common voltage Vcm) to ground Gnd via respective switches, as illustrated in fig. 5A. Fig. 5B illustrates waveforms of the first output signal Vop and the second output signal Von. In the present embodiment, another capacitance digital-to-analog converter with respect to the higher voltage capacitance digital-to-analog converter is defined as an un-switching capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A).
In another alternative embodiment, the second plates of all capacitors of the lower voltage (lower-voltage) capacitive digital-to-analog converter (in this example the first capacitive digital-to-analog converter 11A) are switched (from the common voltage Vcm) to the power supply Vdd via respective switches at step 32.
In the conversion stage 2, as shown in FIG. 6A, the bit at the second Most Significant Bit (MSB) (i.e., the second left bit) position of the conversion output Dout is determined according to the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the second most significant bit position is determined to be "1", otherwise it is determined to be "0". Next, the second plate of the first capacitor of the non-switched capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch according to the comparison output of the comparator 12. Wherein if the output signal of the non-switched capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, the ground Gnd is switched, otherwise, the power Vdd is switched, as shown in fig. 6A. Fig. 6B illustrates waveforms of the first output signal Vop and the second output signal Von.
Similarly, in transition stage 3, as shown in FIG. 7A, the bit at the third Most Significant Bit (MSB) (i.e., the third left bit) position of the transition output Dout is determined based on the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the third most significant bit position is determined to be "1", otherwise it is determined to be "0". Next, the second plate of the second capacitor of the non-switched capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch according to the comparison output of the comparator 12. Wherein if the output signal of the non-switched capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, the switch is made to ground Gnd, as shown in fig. 7A, otherwise, the switch is made to power Vdd. Fig. 7B illustrates waveforms of the first output signal Vop and the second output signal Von.
Similarly, in the conversion stage 4, as shown in FIG. 8A, the bit at the fourth Most Significant Bit (MSB) (i.e., the fourth left bit) position of the conversion output Dout is determined according to the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the fourth most significant bit position is determined to be "1", otherwise it is determined to be "0". Next, the second plate of the third capacitor of the non-switched capacitance digital-to-analog converter (in this example, the first capacitance digital-to-analog converter 11A) is switched via the corresponding switch according to the comparison output of the comparator 12. Wherein if the output signal of the non-switched capacitor digital-to-analog converter is greater than the output signal of the higher voltage capacitor digital-to-analog converter, the switch is made to ground Gnd, as shown in fig. 8A, otherwise, the switch is made to power Vdd. The waveform of the first output signal Vop and the second output signal Von is illustrated as 8B.
Generally, during the transition phase m (1< m < n), the bit at the m-Most Significant Bit (MSB) position of the transition output Dout is determined based on the comparison output of the comparator 12. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the m-th most significant bit position is determined to be "1", otherwise it is determined to be "0". Then, the second plate of the m-1 th capacitor of the non-switched capacitance digital-to-analog converter is switched via the corresponding switch according to the comparison output of the comparator 12. Wherein, if the output signal of the non-switched capacitor digital-to-analog converter is larger than the output signal of the higher voltage capacitor digital-to-analog converter, the ground Gnd is switched, otherwise, the power Vdd is switched.
In step 34 (transition stage 5, transition stage n, or final transition stage), the bits at Least Significant Bit (LSB) (i.e., the rightmost bit) positions of the transition output Dout are determined according to the comparison output of the comparator 12, as shown in fig. 9A. For example, if the first output signal Vop is greater than the second output signal Von, the bit of the least significant bit position is determined to be "1", otherwise it is determined to be "0". In this step, there is no need to switch the capacitor as in the previous step. Fig. 9B illustrates waveforms of the first output signal Vop and the second output signal Von.
The above embodiments may be applied to other algorithms, such as detect-and-skip (DAS) algorithm. In one example, the foregoing embodiment is used to convert the first several n bits, so as to obtain the error caused by the inaccuracy of the capacitive digital-to-analog converter, which is stored in a lookup table (lookup table) or implemented as a logic circuit. Based on the resulting error, a detect-and-skip (DAS) algorithm is performed to convert the next bits of the n bits. Details of the detect-and-skip (DAS) algorithm can be found in "0.85 fJ/conversion step 10b 200kS/s sub-area sequential asymptotic analog-to-digital converter with 40nm CMOS (a 0.85fJ/conversion-step 10b 200kS/s Subrancing SAR ADC in40nm CMOS)" proposed by the Dynasty (translation of Hung-Yen Tai), published in the institute of Electrical and electronics Engineers International Solid State Circuit Conference (IEEE) 2014, which is regarded as part of the present specification.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A high linearity, circular asymptotic analog-to-digital converter for generating an n-bit converted output, comprising:
a first capacitive digital-to-analog converter; and
a second capacitive digital-to-analog converter;
wherein in the sampling stage, all capacitors of the first and second capacitive digital-to-analog converters are switched to a common voltage;
in a first conversion stage, determining a first most significant bit of the conversion output according to a comparison result of output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter;
defining one of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter with a larger output signal as a higher voltage capacitor digital-to-analog converter, and the other one as a non-switched capacitor digital-to-analog converter;
switching all capacitors of the higher voltage capacitance digital-to-analog converter to ground, wherein a common voltage is between a power supply and ground;
determining an mth most significant bit of the converted output according to a comparison result of output signals of the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter in an mth conversion stage (1< m < n);
switching an m-1 capacitor of the non-switched capacitor digital-to-analog converter according to a comparison result of output signals of the higher voltage capacitor digital-to-analog converter and the non-switched capacitor digital-to-analog converter; and
in the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.
2. The high linearity adc of claim 1, wherein the first capacitive dac comprises n-1 capacitors having capacitance values of 2n-3C, 2n-4C … 22C, 21C in sequence from 1 to n-1, where C is a default value.
3. The high linearity adc of claim 1, wherein the second capacitive dac comprises n-1 capacitors having capacitance values of 2n-3C, 2n-4C … 22C, 21C in sequence from 1 to n-1, wherein C is a default value.
4. The high linearity cyclic asymptotic ADC of claim 1, wherein if the output signal of the first capacitive DAC is larger than the output signal of the second capacitive DAC, the first most significant bit of the converted output is determined to be "1", otherwise the first most significant bit is determined to be "0".
5. The high linearity cyclic asymptotic ADC of claim 1, wherein the mth most significant bit of the converted output is determined to be "1" if the output signal of the first capacitive DAC is larger than the output signal of the second capacitive DAC, and is otherwise determined to be "0".
6. The high linearity cyclic asymptotic ADC of claim 1, wherein the m-1 capacitor of the unswitched capacitance DAC is switched to ground if the output signal of the unswitched capacitance DAC is larger than the output signal of the higher voltage capacitance DAC, and is switched to power otherwise.
7. The high linearity cyclic asymptotic ADC of claim 1, wherein if the output signal of the first capacitive DAC is larger than the output signal of the second capacitive DAC, the least significant bit of the converted output is determined to be "1", otherwise the least significant bit is determined to be "0".
8. The high linearity cyclic asymptotic ADC of claim 1, further comprising:
a detect-and-skip algorithm is performed based on the n-bit conversion output generated.
9. The high linearity cyclic asymptotic ADC of claim 1, wherein during the sampling phase, the first capacitive DAC samples a positive input signal and the second capacitive DAC samples a negative input signal.
10. The high linearity successive approximation analog-to-digital converter of claim 1, further comprising a comparator receiving an output signal of the first capacitive digital-to-analog converter and an output signal of the second capacitive digital-to-analog converter.
11. A high linearity, circular asymptotic analog-to-digital converter for generating an n-bit converted output, comprising:
a first capacitive digital-to-analog converter; and
a second capacitive digital-to-analog converter;
wherein in the sampling stage, all capacitors of the first and second capacitive digital-to-analog converters are switched to a common voltage;
in a first conversion stage, determining a first most significant bit of the conversion output according to a comparison result of output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter;
defining one of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter having a smaller output signal as a lower voltage capacitor digital-to-analog converter, and the other one as a non-switched capacitor digital-to-analog converter;
switching all capacitors of the lower voltage capacitance digital-to-analog converter to a power supply, wherein a common voltage is between the power supply and ground;
determining an mth most significant bit of the converted output according to a comparison result of output signals of the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter in an mth conversion stage (1< m < n);
switching an m-1 capacitor of the non-switched capacitor digital-to-analog converter according to a comparison result of output signals of the lower voltage capacitor digital-to-analog converter and the non-switched capacitor digital-to-analog converter; and
in the nth conversion stage, the least significant bit of the conversion output is determined according to the comparison result of the output signals of the first capacitor digital-to-analog converter and the second capacitor digital-to-analog converter.
12. The high linearity cyclic asymptotic ADC of claim 11, wherein the m-1 capacitor of the non-switched capacitor DAC is switched to ground if the output signal of the non-switched capacitor DAC is greater than the output signal of the lower voltage capacitor DAC, and is otherwise switched to power.
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| CN111294050B (en) | 2023-03-24 |
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