CN105007079A - Fully differential increment sampling method of successive approximation type analog-digital converter - Google Patents

Abstract

The invention discloses a fully differential increment sampling method of a successive approximation type analog-digital converter. According to amplitude characteristic analysis of a neural signal, it is determined that during a non-active period of the signal, most amplitude values of the signal fall into a window of 16LSB, and therefore, a judging window is arranged to shield high-order redundancy conversion of the SAR ADC during the non-active period of the signal. When the signal is active, the amplitude change of the signal exceeds 16LSB and the ADC performs conversion from the high-order bits, so that the problem that the input signal amplitude needs to be limited for an input-tracking SAR ADC structure is solved. The increment sampling SAR ADC provided by the invention is a fully differential structure. The fully differential increment sampling method could effectively restrain common mode interference and even-order harmonic, improve accuracy of ADC conversion and solve the problems that the common mode disturbance of a signal-end structure is large and the noise of the even-order harmonic is obvious. Simultaneously, compared with a single-ended increment sampling structure, the fully differential structure has a doubled signal conversion range, thereby effectively broadening the range of input signals.

Description

The fully differential increment method of sampling of gradual approaching A/D converter

[technical field]

The present invention relates to analog to digital converter technical field, particularly a kind of fully differential increment method of sampling of gradual approaching A/D converter.

[background technology]

Low consumption circuit is the emphasis of the circuit design such as nerve signal transducer and radio sensing network always.Due to SAR ADC (successive approximation A/D converter, successive approximation analog to digital converter) there is simple structure and less analog module, extremely low power consumption can be realized, be therefore particularly suitable for the circuit design of low-power consumption.Electric charge is the distributed SAR ADC capacitor array DAC that utilizes the exponent of 2 to arrange again, different quantization levels is realized by the switching of electric capacity between height reference level of different weight, and make this level finally level off to sampled signal, obtain quantized result.For the SARADC of N-bit, need N electric capacity to switch in theory and just can obtain transformation result.

Signal to be detected in electroneurographic signal and sensing network is generally pulse signal, and most of the time signal intensity is comparatively slow, and changes in amplitude is little, and only when pulse arrives, amplitude just has larger change.When signal amplitude change is slow, when sample rate is constant, the sampled value change of adjacent double sampling is less, and the high-order result of ADC conversion is identical, as Fig. 1.The switching power consumption of DAC electric capacity occupies larger specific gravity in SAR ADC total power consumption, and the average power consumption expression formula recovering each step electric capacity switching of structure (Vcm-based) SARADC based on common mode electrical level is:

E _i＝(2 ^n-i-2-2 ^n-2i-2)CV _ref ²(1)

Wherein n is conversion accuracy, and C is unit electric capacity, V _reffor the reference level that electric capacity switches.E _irepresent the average power consumption that the i-th step electric capacity switches, as i=1, E ₁represent the average power consumption that the first step (i.e. MSB) electric capacity switches, can see that the switching power consumption of high-order electric capacity exponentially compared with the switching power consumption of bit capacitor increases.

High ordertransfer redundancy shown in Fig. 1 will bring larger energy dissipation.For the SAR ADC of pulse signal detection application, solve high ordertransfer redundancy issue significant for low power dissipation design.

For this problem, a kind of SAR ADC structure of inputting, tracing is suggested.Its each sampled value is not the absolute size value of input voltage, but this sampling and previous conversion quantize the difference of voltage.When adjacent double sampling change is less, this difference is less, carries out quantizing can predict high-order transformation result for " 0 ", therefore can shield high-order conversion to this difference, be added to the transformation result of low level previous quantized result, can obtain the quantized value of this sampling.Such as document " Input-trackingDAC for low-powerhigh-linearity SAR ADC " (B.G.Lee and S.G.Lee, Electronics Letters, vol.47, no.16, pp.911-913, Aug.2011) in by the frequency of restriction input signal, adjacent double sampling difference can be realized and be less than Vref/4, thus shield the conversion of MSB and MSB-1 position, compare traditional SAR ADC, the average switch power consumption of electric capacity saves 70%.But this method limits frequency input signal, namely limit the changing value of adjacent double sampling voltage, when variable quantity of sampling is greater than Vref/4, will there is mistake in conversion.Therefore this ADC cannot process sampling and the conversion of significantly jump signal.In order to solve the large problem of jump signal changes in amplitude, voltage decision logic can be added, when the difference of sampling is less than a window, only carrying out low level conversion, when difference is greater than window, change from a high position.Document " A Low Power 10bit 500kS/sDelta-Modulated SAR ADC (DMSAR ADC) for Implantable Medical Devices " (Y.F.Lyu, C.Y.Wu, L.C.Liu, IEEE International Symposium on Circuits and System (ISCAS), pp.2046-2049,2013) one group of previous quantification voltage of DAC capacitance stores is utilized, another group DAC gathers current input value, achieves the SAR ADC of single-ended increment sampling.By the set of specific capacitor in DAC, can judge to sample difference whether in the window of setting, and complete subsequent conversion.Measurement result shows, and when input signal is 10Hz and 7kHz, this ADC can realize the power consumption reduction of 66% under 500kS/s sample rate.But the ADC in article belongs to single-ended sampling, be unfavorable for suppressing common mode disturbances, the conversion range of single-ended structure is also narrower simultaneously.Therefore this ADC is not suitable in the larger signal acquiring system of common mode disturbances.

Document " A 10bit SAR ADC With Data-DependentEnergy Reduction Using LSB-FirstSuccessiveApproximation " (F.M.Yaul and A.P.Chandrakasan, IEEE Journal of Solid-State Circuits, vol.49, no.12, pp.2825-2834, December 2014) a kind of backward conversion SAR ADC estimated based on voltage is proposed, solve the problem of high ordertransfer redundancy.After sampling terminates, estimate voltage by previous quantized result as to one of this sampled value, and progressively upwards search for from LSB, judge sampled voltage scope.After sampled voltage scope is determined, DAC progressively changes downwards again, obtains this quantized result.This structure, when adjacent double sampling voltage is constant, only can realize once changing by 2 steps.But this conversion logic only has very high conversion efficiency when input signal changes slowly, it increases along with signal amplitude, and conversion efficiency declines very fast.

[summary of the invention]

The object of the present invention is to provide a kind of fully differential increment method of sampling of gradual approaching A/D converter, to solve the deficiency of high ordertransfer redundancy issue that SARADC runs into and existing solution.

To achieve these goals, the present invention adopts following technical scheme:

The fully differential increment method of sampling of gradual approaching A/D converter, comprises the following steps:

1) when sampling control signal SAMPLE signal is " 1 ", enter sample phase, now sampling switch closes, and input signal change followed by capacitor array top crown; Capacitor array bottom crown receives V respectively according to previous quantized result D [9:1] from a high position to low level _dDor GND; Due to C ₀and C ₁size be identical, when D [0] is 1, the C in P type capacitor array ₀receive V _cM, the C in N-type capacitor array ₀receive GND; When D [0] is 0, the C in P type capacitor array ₀receive GND, the C in N-type capacitor array ₀receive V _cM; At the end of sampling, capacitor array top crown quantity of electric charge expression formula is:

$Q_p=V_{IP}\·C_T-\left(\underset{i=1}{\overset{9}{\Σ}}\right(D\[i\]\·2^{i-1}{C}_0)\·V_{DD}+D\[0\]\·C_0\·\frac{V_{DD}}{2})---\left(3\right)$

$Q_n=V_{IN}\·C_T-\left(\underset{i=1}{\overset{9}{\Σ}}\right(\stackrel{\‾}{D\[i\]}\·2^{i-1}{C}_0)\·V_{DD}+\stackrel{\‾}{D\[0\]}\·C_0\·\frac{V_{DD}}{2})---\left(4\right)$

Wherein V _iPand V _iNfor sample voltage value of checking the mark, C _tfor the electric capacity summation of single-ended capacitor array;

2) after sampling terminates, enter hold mode, sampling switch disconnects, and capacitance switch control capacitance array bottom crown all receives V _cM, now the quantity of electric charge expression formula of capacitor array top crown is:

Q _p＝(V _p-V _CM)·C _T(5)

Q _n＝(V _n-V _CM)·C _T(6)

Wherein V _pand V _nbe respectively the magnitude of voltage of differential capacitance top crown.

Make (3) (5) equal respectively with (4) (6) formula, obtain capacitor array top crown voltage expression at the end of sampling:

$\begin{array}{c}{V}_p=V_{IP}-(\underset{i=1}{\overset{9}{\Σ}}D\[i\]\·\frac{2^{i-1}{C}_0}{C_T}\·V_{DD}+D\[0\]\·\frac{C_0}{C_T}\·\frac{V_{DD}}{2})+V_{CM}\\ =V_{IP}-V_{IP}^{\′}+V_{CM}\end{array}---\left(7\right)$

$\begin{array}{c}{V}_n=V_{IN}-(\underset{i=1}{\overset{9}{\Σ}}\stackrel{\‾}{D\[i\]}\·\frac{2^{i-1}{C}_0}{C_T}\·V_{DD}+\stackrel{\‾}{D\[0\]}\·\frac{C_0}{C_T}\·\frac{V_{DD}}{2})+V_{CM}\\ =V_{IN}-V_{IN}^{\′}+V_{CM}\end{array}---\left(8\right)$

Subtracted each other by (7) (8) formula and obtain the difference difference signal obtained of sampling and be:

V _p-V _n＝(V _IP-V _IN)-(V′ _IP-V′ _IN) (9)

Wherein, V _iP-V _iNfor this difference sample voltage value, V ' _iP-V ' _iNfor previous difference sample quantization end value;

3) phase place is kept to terminate symbol and the size of rear judgement difference increment of sample magnitude of voltage:

If incremental voltage is that just P is held C by capacitance switch ₅gND received by the lower step of electric capacity, and N holds C ₅v received by the lower step of electric capacity _dD, now capacitor array top crown voltage difference is:

$V_p-V_n=(V_{IP}-V_{IN})-(V_{IP}^{\′}-V_{IN}^{\′})-\frac{1}{32}{V}_{DD}---\left(10\right)$

The described fully differential increment method of sampling adopts sampling of entirely checking the mark, and the full amplitude of sampled signal is 2V _dD, quantified precision is 10bit, and therefore a quantification step (LSB) is V _dD/ 512; If the comparative result of comparator is " 1 ", represent that positive incremental voltage value is greater than 1/32V _dD, i.e. 16LSB, beyond the coding range of low 4, next step is from highest order C ₉electric capacity starts conversion: by C ₅the lower step of electric capacity takes back V _cM, the C of P end ₉gND received by the lower step of electric capacity, the C of N end ₉v received by the lower step of electric capacity _dD, comparator judges whether positive incremental voltage value is greater than 1/2V _dDif be greater than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive GND and the C of N end ₈bottom crown is from V _cMreceive V _dD, judge whether incremental voltage value is greater than 3/4V _dDif instead be less than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive V _dDand the C of N end ₈bottom crown is from V _cMreceive GND, judge whether incremental voltage value is greater than 1/4V _dD, subsequent conversion principle is the same until all figure places convert; If comparative result is " 0 ", represent that positive incremental voltage is less than 1/32V _dD, directly carry out next step C ₄the conversion of electric capacity: the C that P is held ₄v received by the lower step of electric capacity _dD, the C of N end ₄gND received by the lower step of electric capacity, judges whether positive incremental voltage is greater than 1/64V _dDif be greater than 1/64V _dDthe then C of P end ₃bottom crown is from V _cMreceive GND and the C of N end ₃bottom crown is from V _cMreceive V _dD, judge whether incremental voltage is greater than 3/128V _dDif instead be less than 1/64V _dDthe then C of P end ₃v received by bottom crown _dDand the C of N end ₃gND received by bottom crown, judges whether incremental voltage is greater than 1/128V _dD, subsequent conversion principle is the same until all figure places convert;

If incremental voltage is negative value, P is held C ₅v received by the lower step of electric capacity _dD, N holds C ₅gND received by the lower step of electric capacity; If comparative result is " 0 ", represent that negative incremental voltage value is greater than 1/32V _dD, next step needs from C ₉electric capacity starts conversion, if comparative result is " 1 ", represents that negative incremental voltage value is less than 1/32V _dD, shield the conversion of high 4, next step is changed from C4 electric capacity, until EOC;

4) step 3) in the transform coding value of positive incremental voltage be added in the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value; Step 3) in the transform coding value of negative incremental voltage deducted from the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value;

5) treat that all switch process complete, this EOC, gradual approaching A/D converter enters into holding state, waits for the arrival of next SAMPLE signal high level, carries out sample conversion next time.

The present invention further improves and is: the P type capacitor array of capacitor array is identical with N-type capacitor array, includes 10 electric capacity C0-C9; Every partition capacitance array capacitor size arranges according to the exponent of 2, namely

C _i＝2 ^i-1C ₀(i＞0) (2)

Wherein C _irepresent the size of i-th electric capacity, C ₀represent specific capacitance; The electric capacity C at the most end of capacitor array ₀as weight electric capacity, do not participate in conversion;

The top crown of all electric capacity of P type capacitor array connects the positive input terminal of comparator; The top crown of all electric capacity of N-type capacitor array connects the negative input end of comparator; External input signal VIP connects the positive input terminal of comparator by the first sampling switch; External input signal VIN connects the negative input end of comparator by the second sampling switch.

The present invention further improves and is: in P type capacitor array and N-type capacitor array, the lower step of each electric capacity is by capacitance switch S _piand S _nicontrol it and be connected to reference level V _dD, common-mode signal V _cMor GND, wherein V _cM=0.5V _dD.

The present invention further improves and is: in step 1) sample phase and step 4) translate phase, capacitance switch generates two groups of reverse control signal S _p9-0and S _n9-0, control P type capacitor array and N-type capacitor array respectively; Control signal S _piwith control signal S _nion the contrary.

The present invention further improves and is: after comparator has compared, and exports and compares settling signal VALID, and VALID signal, as the generation signal of asynchronous sequential, triggers asynchronous sequential generation module and produces asynchronous clock, is used for driving sar controller.

The present invention further improves and is: the asynchronous clock that sar controller is generated by asynchronous sequential drives, for realizing Approach by inchmeal control logic.

Relative to prior art, the present invention has following beneficial effect:

The present invention is directed to the feature of electroneurographic signal isopulse signal, optimize, make SAR ADC consume lower energy when input signal change is less, and when input signal amplitude changes greatly, extra power consumption can not be increased too much.Gradual approaching A/D converter of the present invention achieves lower power consumption number under the mean state of a long period, is suitable in the middle of Neural Signal Collecting system and wireless sensing network system.

The present invention, according to the amplitude characteristic analysis of nerve signal, determines during signal inactive, and its amplitude major part can drop in the window of 16LSB, therefore judges that window can the high-order redundant of shielded signal inactive period SAR ADC by arranging this.When signal enlivens, the change of its amplitude is changed from a high position more than 16LSB, ADC, overcomes the problem that inputting, tracing SARADC structure needs to limit input signal amplitude.

The present invention carries out the sampling of fully differential increment, effectively can suppress common mode disturbances, suppresses even-order harmonic, improves the precision of ADC conversion, overcomes that single-ended structure common mode perturbations is large, the obvious problem of even-order harmonic noise., sample compared to single-ended increment, the signal conversion range of fully differential increment sampling have also been enlarged one times, has effectively widened the scope of input signal meanwhile.

The fully differential increment method of sampling of the present invention is when signal amplitude increment is less than 16LSB window, and after only carrying out, 5 step electric capacity switchings can complete and once change.Therefore gradual approaching A/D converter of the present invention have also been made good tradeoff design for amplitude variable quantity and electric capacity switch step, it is made not only to have less power consumption in amplitude transformation amount hour, and when amplitude variable quantity increases, still there is relatively low power consumption.

[accompanying drawing explanation]

Fig. 1 is SAR ADC when input signal change is less, the schematic diagram of high ordertransfer redundancy.

Fig. 2 is fully differential increment of the present invention sampling SAR adc circuit structure chart.

Fig. 3 is the capacitor array switch logic figure realizing fully differential increment sampling SAR ADC.

Fig. 4 is the amplitude-versus-frequency curve of SAR ADC of the present invention 2048 FFT.

Fig. 5 is the capacitance switch power consumption of traditional SAR ADC and increment sampling SAR ADC and the variation relation figure of frequency input signal.

[embodiment]

The invention provides a kind of fully differential increment method of sampling of gradual approaching A/D converter, high-order redundant is shielded by the size of the increment size judging sampling, optimize the DAC capacitance switch power consumption of SAR ADC when input signal amplitude of variation is less, achieve low power dissipation design.

SAR ADC integrated circuit designed by the present invention as shown in Figure 2.Main circuit will comprise sampling switch, DAC capacitor array, capacitance switch, comparator, sar controller, asynchronous sequential generation module, 10 adders, 10 MUX 8 and registers 9.SAR ADC work comprises three phases, is respectively sample phase, maintenance stage and translate phase.

DAC capacitor array comprises P type capacitor array and N-type capacitor array, and each capacitor array includes 10 electric capacity C0-C9; The top crown of all electric capacity of P type capacitor array connects the positive input terminal of comparator; The top crown of all electric capacity of N-type capacitor array connects the negative input end of comparator; External input signal VIP connects the positive input terminal of comparator by the first sampling switch; External input signal VIN connects the negative input end of comparator by the second sampling switch.

As shown in Figure 2, sampling switch realizes ADC in the sampling of sample phase to external input signal VIP and VIN.When sampling control signal (SAMPLE) is " 1 ", enter sample phase, sampling switch closes, and the P type capacitor array of DAC capacitor array and the top crown of N-type capacitor array are connected to external input signal VIP and VIN, and the positive input terminal voltage Vp of comparator follows V _iPchange, the negative input end voltage Vn of comparator follows V _iNchange.When SAMPLE signal becomes " 0 ", sampling switch disconnects, and sampling end Vp and Vn respectively store sample switch closes VIP and the VIN value of eve, and this value is also the value that ADC will carry out quantization encoding.

As shown in Figure 2, DAC capacitor array is the important module realizing Approach by inchmeal conversion logic, is also the primary structure realizing increment sampling.In fully differential structure, DAC capacitor array is made up of P type and N-type capacitor array, and these two parts are identical, the capacitor array of two parts up and down as shown in Figure 2.Every partition capacitance array capacitor size arranges according to the exponent of 2, namely

C _i＝2 ^i-1C ₀(i＞0) (2)

Wherein C _irepresent the size of i-th electric capacity, C ₀represent specific capacitance.The electric capacity C at the most end of capacitor array ₀as weight electric capacity, do not participate in conversion.In P type capacitor array and N-type capacitor array, the lower step of each electric capacity is by capacitance switch S _piand S _nicontrol it and be connected to reference level V _dD, common-mode signal V _cM(V _cM=0.5V _dD) or GND.In sample phase, electric capacity top crown is connected to input signal V _iPand V _iN, what electric capacity stored is the difference of this sampled voltage and previous quantification voltage; At translate phase, the top crown of electric capacity carries out the Approach by inchmeal process that electric charge distributes to realize dichotomy again.

As shown in Figure 2, the annexation of step under capacitance switch control DAC electric capacity.In sample phase, capacitance switch signal is controlled by previous quantized result D [9:0]; At translate phase, capacitance switch signal is controlled by the comparative result B [9:0] of comparator.At sample phase and translate phase, capacitance switch generates two groups of reverse control signal S _p9-0and S _n9-0, control P type capacitor array and N-type capacitor array respectively.Work as S _piduring for " 1 ", S _nifor " 0 "; Work as S _piduring for " 0 ", S _nifor " 1 ".When switching signal is " 1 ", under electric capacity, V received by step _dD, when switching signal is " 0 ", under electric capacity, GND received by step.

As shown in Figure 2, comparator realizes electric capacity top crown voltage V _pand V _nsize comparing function.Work as V _pbe greater than V _ntime, comparator output signal COMP is " 1 ", works as V _pbe less than V _ntime, COMP is " 0 ".VALID is for comparing settling signal, and when comparator is in reset and comparison phase, VALID is " 0 ", and when comparator has compared, VALID is set to " 1 ".VALID signal, as the generation signal of asynchronous sequential, triggers asynchronous sequential generation module and produces asynchronous clock.

As shown in Figure 2, sar controller mainly realizes Approach by inchmeal control logic.At translate phase, asynchronous clock that sar controller is generated by asynchronous sequential drives, and according to the comparative result COMP control capacitance switch of comparator, switches, realize the conversion of the i-th step to step under i-th electric capacity.Afterwards, V is worked as _pand V _nwhen voltage is stablized again, sar controller is triggered again, the lower step controlling the i-th-1 electric capacity according to comparative result COMP switches, complete the i-th-1 conversion, so carry out repeated work, convert until all, sar controller makes ADC enter holding state, waits for the arrival of switching signal SAMPLE next time.As shown in Figure 2, asynchronous sequential generation module is used for producing the internal clocking driving sar controller work.SAMPLE signal is sampled signal, and its frequency equals ADC sample frequency, at the end of sampling, by asynchronous sequential generation module for sar controller provides follow-up internal clocking, therefore avoid the introducing of external high frequency clock, reduce clock power consumption, reduce interference.

As shown in Figure 2,10 adders have been used for the summation of previous quantization encoding and this increment sample quantization value.SAR ADC designed by the present invention samples to incremental voltage at every turn and changes, and the transformation result obtained is B [9:0], and this increment is added with previous quantization encoding value D [9:0], can obtain the absolute coding value of this sampled voltage.In adder, be also integrated with and overflow decision logic circuit.When D [9:0] reaches maximum, if because error causes B [9:0] to be a positive recruitment, then overflow logic keep D [9:0] for maximum constant.Otherwise, when D [9:0] reaches minimum value, if because error causes B [9:0] to be a negative decrease, then overflow logic keep D [9:0] for minimum value constant.

As shown in Figure 2,10 MUX are used for selecting the source of control capacitance switching signal.Sample phase capacitance switch is controlled by previous quantization encoding value, and translate phase capacitance switch is controlled by current comparator Output rusults.

As shown in Figure 2, register module is used for storing previous transform coding value.Register data upgrades after this increment sample conversion completes, and remains to next increment sample conversion and complete.

Fig. 3 shows the electric capacity switch logic figure of the fully differential increment method of sampling of gradual approaching A/D converter of the present invention, specifically comprises the following steps:

1) when SAMPLE signal is " 1 ", as shown in Figure 3, SAR ADC enters sample phase, and now sampling switch closes, and input signal change followed by electric capacity top crown.Electric capacity bottom crown receives V respectively according to previous quantized result D [9:1] from a high position to low level _dDor GND.Because tail electric capacity C0 is equal with C1 capacitance size, therefore when D [0] is 1, the C in P type DAC ₀receive V _cM, the C in N-type DAC ₀receive GND; When D [0] is 0, the C in P type DAC ₀receive GND, the C in N-type DAC ₀receive V _cM.At the end of sampling, electric capacity top crown quantity of electric charge expression formula is:

$Q_p=V_{IP}\·C_T-\left(\underset{i=1}{\overset{9}{\Σ}}\right(D\[i\]\·2^{i-1}{C}_0)\·V_{DD}+D\[0\]\·C_0\·\frac{V_{DD}}{2})---\left(3\right)$

$Q_n=V_{IN}\·C_T-\left(\underset{i=1}{\overset{9}{\Σ}}\right(\stackrel{\‾}{D\[i\]}\·2^{i-1}{C}_0)\·V_{DD}+\stackrel{\‾}{D\[0\]}\·C_0\·\frac{V_{DD}}{2})---\left(4\right)$

Wherein C _tfor single-ended capacitor array and.

2) after sampling terminates, enter hold mode, as shown in Figure 3, sampling switch disconnects, and capacitance switch control capacitance bottom crown all receives V _cM, now the quantity of electric charge expression formula of electric capacity top crown is:

Q _p＝(V _p-V _CM)·C _T(5)

Q _n＝(V _n-V _CM)·C _T(6)

Because sampling switch disconnects front and back, the electric capacity top crown quantity of electric charge remains unchanged, and therefore makes (3) (5) equal respectively with (4) (6) formula, can obtain electric capacity top crown voltage expression at the end of sampling:

$\begin{array}{c}{V}_p=V_{IP}-(\underset{i=1}{\overset{9}{\Σ}}D\[i\]\·\frac{2^{i-1}{C}_0}{C_T}\·V_{DD}+D\[0\]\·\frac{C_0}{C_T}\·\frac{V_{DD}}{2})+V_{CM}\\ =V_{IP}-V_{IP}^{\′}+V_{CM}\end{array}---\left(7\right)$

$\begin{array}{c}{V}_n=V_{IN}-(\underset{i=1}{\overset{9}{\Σ}}\stackrel{\‾}{D\[i\]}\·\frac{2^{i-1}{C}_0}{C_T}\·V_{DD}+\stackrel{\‾}{D\[0\]}\·\frac{C_0}{C_T}\·\frac{V_{DD}}{2})+V_{CM}\\ =V_{IN}-V_{IN}^{\′}+V_{CM}\end{array}---\left(8\right)$

Subtracted each other by (7) (8) formula and can obtain the difference difference signal obtained of sampling and be:

V _p-V _n＝(V _IP-V _IN)-(V′ _IP-V′ _IN) (9)

Wherein, V _iP-V _iNfor this difference sample voltage value, V ' _iP-V ' _iNfor previous difference sample quantization end value, the voltage difference that the electric capacity top crown therefore representated by formula (9) stores is difference increment of sample magnitude of voltage.

3) phase place is kept to terminate the rear symbol and the size that need to judge increment (result of formula (9)).

As shown in Figure 3, if incremental voltage is just (V _p>V _n), then illustrate that this differential voltage value of sampling is larger than the differential voltage value of previous sampling, the present invention utilizes C ₅the switching of electric capacity judges incremental voltage value whether within LSB/32.P is held C by capacitance switch ₅receive GND, N holds C5 to receive V _dD, now electric capacity top crown voltage difference is:

$V_p-V_n=(V_{IP}-V_{IN})-(V_{IP}^{\′}-V_{IN}^{\′})-\frac{1}{32}{V}_{DD}---\left(10\right)$

If the comparative result of comparator is " 1 ", represent that positive incremental voltage value is greater than 1/32V _dD, beyond the coding range of low 4, therefore next step changes from highest order (C9), by C ₅electric capacity takes back V _cM, the C of P end ₉gND received by the lower step of electric capacity, the C of N end ₉v received by the lower step of electric capacity _dD, comparator judges whether positive incremental voltage value is greater than 1/2V _dDif be greater than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive GND and the C of N end ₈bottom crown is from V _cMreceive V _dD, judge whether incremental voltage value is greater than 3/4V _dDif instead be less than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive V _dDand the C of N end ₈bottom crown is from V _cMreceive GND, judge whether incremental voltage value is greater than 1/4V _dD, subsequent conversion principle is the same until all figure places convert.If comparative result is " 0 ", represent that positive incremental voltage is less than 1/32V _dD, can predict that the encoded radio of high 4 D [9:6] is for " 0 ", therefore can by high 4 conversion shieldings, directly carry out the conversion of next step C4, the C4 by P end receives V _dD, the C of N end ₄receive GND, judge whether positive incremental voltage is greater than 1/64V _dDif be greater than 1/64V _dDthe then C of P end ₃bottom crown is from V _cMreceive GND and the C of N end ₃bottom crown is from V _cMreceive V _dD, judge whether incremental voltage is greater than 3/128V _dDif instead be less than 1/64V _dDthe then C of P end ₃v received by bottom crown _dDand the C of N end ₃gND received by bottom crown, judges whether incremental voltage is greater than 1/128V _dD, subsequent conversion principle is the same until all figure places convert.

If incremental voltage is negative value (V _p<V _n), then illustrate that this differential voltage value of sampling is less than the differential voltage value of previous sampling, conversion logic afterwards and (V _p>V _n) logic contrary.Judging the stage, P is being held C ₅receive V _dD, N holds C ₅receive GND.If comparative result is " 0 ", represent that negative incremental voltage value is greater than 1/32V _dD, next step needs from C ₉start conversion.If comparative result is " 1 ", represent that negative incremental voltage value is less than 1/32V _dD, can shield the conversion of high 4, next step is from C ₄change, until EOC.

4) step 3) in the transform coding value of positive incremental voltage need to be added in the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value.Step 3) in the transform coding value of negative incremental voltage need to be deducted from the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value, subtract logic has been integrated in 10 adders.

5) treat that all switch process complete, this EOC, SAR ADC enters into holding state, waits for the arrival of next SAMPLE signal high level, carries out sample conversion next time.

Fully differential increment sampling gradual approaching A/D converter designed by the present invention, adopts 0.18 μm of standard CMOS process to carry out circuit design, and has carried out simulating, verifying.Whole circuit working is under 0.6V supply voltage, and sample frequency is up to 300kS/s, and input signal amplitude is 1.14V _pp, when frequency input signal is 1kHz, the power consumption of SAR ADC is 2.49 μ W, and the ADC spectrogram that emulation obtains as shown in Figure 4.By the calculating to Fig. 4, the signal harmonic noise ratio (SNDR) of the SAR ADC designed by the present invention is 58.4dB, and effective accuracy is 9.4, and quality factor reach 12.28fJ/conv.-step.Fig. 5 is SAR ADC capacitance switch power consumption graph of a relation with frequency input signal change under 300kS/s sample rate.The reduction along with frequency input signal can be seen, neighbouring sample signal intensity amplitude reduces, and increment of sample voltage is more in 16LSB window, and SAR ADC shields the switching of high-order electric capacity, reduce converted power consumption, therefore capacitance switch power consumption reduces along with frequency input signal and reduces.When frequency input signal is less than 1.5kHz, under 300kS/s sample rate condition, the incremental voltage of any twice neighbouring sample is all within 16LSB, and therefore average capacitance switching power loss reaches minimum.As can be seen from Figure 5, compare conventional conversion structure, the average capacitance switching power loss of fully differential increment sampling structure can save 94% at most.When frequency input signal is greater than 10kHz, because adjacent double sampling incremental voltage value is not all in the scope of 16LSB, so SAR ADC will from C ₉for starting conversion, owing to consuming C ₅the power consumption that electric capacity switches judges the size of incremental voltage, therefore the master switch power consumption of DAC can be greater than traditional SAR ADC, but electroneurographic signal pulse frequency seldom reaches more than 10kHz, under this application conditions, this situation is little, and method of the present invention still can obtain lower power consumption within longer change-over time.

Claims (6)

1. the fully differential increment method of sampling of gradual approaching A/D converter, is characterized in that, comprise the following steps:

1) when sampling control signal SAMPLE signal is " 1 ", enter sample phase, now sampling switch closes, and input signal change followed by capacitor array top crown; Capacitor array bottom crown receives V respectively according to previous quantized result D [9:1] from a high position to low level _dDor GND; When D [0] is 1, the C in P type capacitor array ₀receive V _cM, the C in N-type capacitor array ₀receive GND; When D [0] is 0, the C in P type capacitor array ₀receive GND, the C in N-type capacitor array ₀receive V _cM; At the end of sampling, capacitor array top crown quantity of electric charge expression formula is:

$Q_p=V_{IP}\&CenterDot;C_T-\left(\underset{i=1}{\overset{9}{\&Sigma;}}\right(D\&lsqb;i\&rsqb;\&CenterDot;2^{i-1}{C}_0)\&CenterDot;V_{DD}+D\&lsqb;0\&rsqb;\&CenterDot;C_0\&CenterDot;\frac{V_{DD}}{2})---\left(3\right)$

$Q_n=V_{IN}\&CenterDot;C_T-\left(\underset{i=1}{\overset{9}{\&Sigma;}}\right(\stackrel{\&OverBar;}{D\&lsqb;i\&rsqb;}\&CenterDot;2^{i-1}{C}_0)\&CenterDot;V_{DD}+\stackrel{\&OverBar;}{D\&lsqb;0\&rsqb;}\&CenterDot;C_0\&CenterDot;\frac{V_{DD}}{2})---\left(4\right)$

Wherein C _tfor single-ended capacitor array and;

2) after sampling terminates, enter hold mode, sampling switch disconnects, and capacitance switch control capacitance array bottom crown all receives V _cM, now the quantity of electric charge expression formula of capacitor array top crown is:

Q _p＝(V _p-V _CM)·C _T（5）

Q _n＝(V _n-V _CM)·C _T（6）

Make (3) (5) equal respectively with (4) (6) formula, obtain capacitor array top crown voltage expression at the end of sampling:

$\begin{array}{c}{V}_p=V_{IP}-(\underset{i=1}{\overset{9}{\&Sigma;}}D\&lsqb;i\&rsqb;\&CenterDot;\frac{2^{i-1}{C}_0}{C_T}\&CenterDot;V_{DD}+D\&lsqb;0\&rsqb;\&CenterDot;\frac{C_0}{C_T}\&CenterDot;\frac{V_{DD}}{2})+V_{CM}\\ =V_{IP}-V_{IP}^{\&prime;}+V_{CM}\end{array}---\left(7\right)$

$\begin{array}{c}{V}_n=V_{IN}-(\underset{i=1}{\overset{9}{\&Sigma;}}\stackrel{\&OverBar;}{D\&lsqb;i\&rsqb;}\&CenterDot;\frac{2^{i-1}{C}_0}{C_T}\&CenterDot;V_{DD}+\stackrel{\&OverBar;}{D\&lsqb;0\&rsqb;}\&CenterDot;\frac{C_0}{C_T}\&CenterDot;\frac{V_{DD}}{2})+V_{CM}\\ =V_{IN}-V_{IN}^{\&prime;}+V_{CM}\end{array}---\left(8\right)$

Subtracted each other by (7) (8) formula and obtain the difference difference signal obtained of sampling and be:

V _p-V _n＝(V _IP-V _IN)-(V′ _IP-V′ _IN) （9）

Wherein, V _iP-V _iNfor this difference sample voltage value, V ' _iP-V ' _iNfor previous difference sample quantization end value;

3) phase place is kept to terminate symbol and the size of rear judgement difference increment of sample magnitude of voltage:

If incremental voltage is that just P is held C by capacitance switch ₅gND received by the lower step of electric capacity, and N holds C ₅v received by the lower step of electric capacity _dD, now capacitor array top crown voltage difference is:

$V_p-V_n=(V_{IP}-V_{IN})-(V_{IP}^{\&prime;}-V_{IN}^{\&prime;})-\frac{1}{32}{V}_{DD}---\left(10\right)$

The described fully differential increment method of sampling adopts sampling of entirely checking the mark, and the full amplitude of sampled signal is 2V _dD, quantified precision is 10bit, and therefore a quantification step (LSB) is V _dD/ 512; If the comparative result of comparator is " 1 ", represent that positive incremental voltage value is greater than 1/32V _dD, i.e. 16LSB, beyond the coding range of low 4, next step is from highest order C ₉electric capacity starts conversion: by C ₅the lower step of electric capacity takes back V _cM, the C of P end ₉gND received by the lower step of electric capacity, the C of N end ₉v received by the lower step of electric capacity _dD, comparator judges whether positive incremental voltage value is greater than 1/2V _dDif be greater than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive GND and the C of N end ₈bottom crown is from V _cMreceive V _dD, judge whether incremental voltage value is greater than 3/4V _dDif instead be less than 1/2V _dDthe then C of P end ₈bottom crown is from V _cMreceive V _dDand the C of N end ₈bottom crown is from V _cMreceive GND, judge whether incremental voltage value is greater than 1/4V _dD, subsequent conversion principle is the same until all figure places convert; If comparative result is " 0 ", represent that positive incremental voltage is less than 1/32V _dD, directly carry out next step C ₄the conversion of electric capacity: the C that P is held ₄v received by the lower step of electric capacity _dD, the C of N end ₄gND received by the lower step of electric capacity, judges whether positive incremental voltage is greater than 1/64V _dDif be greater than 1/64V _dDthe then C of P end ₃bottom crown is from V _cMreceive GND and the C of N end ₃bottom crown is from V _cMreceive V _dD, judge whether incremental voltage is greater than 3/128V _dDif instead be less than 1/64V _dDthe then C of P end ₃v received by bottom crown _dDand the C of N end ₃gND received by bottom crown, judges whether incremental voltage is greater than 1/128V _dD, subsequent conversion principle is the same until all figure places convert;

If incremental voltage is negative value, P is held C ₅v received by the lower step of electric capacity _dD, N holds C ₅gND received by the lower step of electric capacity; If comparative result is " 0 ", represent that negative incremental voltage value is greater than 1/32V _dD, next step needs from C ₉electric capacity starts conversion, if comparative result is " 1 ", represents that negative incremental voltage value is less than 1/32V _dD, shield the conversion of high 4, next step is changed from C4 electric capacity, until EOC;

4) step 3) in the transform coding value of positive incremental voltage be added in the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value; Step 3) in the transform coding value of negative incremental voltage deducted from the quantization encoding value of previous conversion by 10 adders, obtain this difference component V _iP-V _iNquantization encoding value;

5) treat that all switch process complete, this EOC, gradual approaching A/D converter enters into holding state, waits for the arrival of next SAMPLE signal high level, carries out sample conversion next time.

2. the fully differential increment method of sampling of gradual approaching A/D converter according to claim 1, is characterized in that, the P type capacitor array of capacitor array is identical with N-type capacitor array, includes 10 electric capacity C0-C9; Every partition capacitance array capacitor size arranges according to the exponent of 2, namely

C _i＝2 ^i-1C ₀(i＞0) （2）

Wherein C _irepresent the size of i-th electric capacity, C ₀represent specific capacitance; The electric capacity C at the most end of capacitor array ₀as weight electric capacity, do not participate in conversion;

The top crown of all electric capacity of P type capacitor array connects the positive input terminal of comparator; The top crown of all electric capacity of N-type capacitor array connects the negative input end of comparator; External input signal VIP connects the positive input terminal of comparator by the first sampling switch; External input signal VIN connects the negative input end of comparator by the second sampling switch.

3. the fully differential increment method of sampling of gradual approaching A/D converter according to claim 2, is characterized in that, in P type capacitor array and N-type capacitor array, the lower step of each electric capacity is by capacitance switch S _piand S _nicontrol it and be connected to reference level V _dD, common-mode signal V _cMor GND, wherein V _cM=0.5V _dD.

4. the fully differential increment method of sampling of gradual approaching A/D converter according to claim 1, is characterized in that, at the sample phase of step 1) and the translate phase of step 4), capacitance switch generates two groups of reverse control signal S _p9-0and S _n9-0, control P type capacitor array and N-type capacitor array respectively; Control signal S _piwith control signal S _nion the contrary.

5. the fully differential increment method of sampling of gradual approaching A/D converter according to claim 1, it is characterized in that, after comparator has compared, settling signal VALID is compared in output, VALID signal is as the generation signal of asynchronous sequential, trigger asynchronous sequential generation module and produce asynchronous clock, be used for driving sar controller.

6. the fully differential increment method of sampling of gradual approaching A/D converter according to claim 5, is characterized in that, the asynchronous clock that sar controller is generated by asynchronous sequential drives, for realizing Approach by inchmeal control logic.