CN104143983A - Continuous approximation type analog-digital converter and method thereof - Google Patents
Continuous approximation type analog-digital converter and method thereof Download PDFInfo
- Publication number
- CN104143983A CN104143983A CN201310173319.XA CN201310173319A CN104143983A CN 104143983 A CN104143983 A CN 104143983A CN 201310173319 A CN201310173319 A CN 201310173319A CN 104143983 A CN104143983 A CN 104143983A
- Authority
- CN
- China
- Prior art keywords
- carry
- out bit
- comparative result
- current potential
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a continuous approximation type analog-digital converter and a method thereof. Particularly, in each bit decision period of last several bit decision periods, a comparator is used for continuously conducting multiple comparison on a first potential and a second potential on an analog-digital converting circuit to obtain a plurality of comparison results, and then a continuous approximation type control circuit is used for generating corresponding carry-out bits according to the comparison results.
Description
Technical field
The present invention relates to a kind of analog digital switch technology, particularly a kind of Continuous Approximation formula analog-digital converter (SAR ADC) and method thereof.
Background technology
Analog-digital converter (analog-to-digital converter; ADC) there is multiple framework, for example: flash type (flash) ADC, pipeline type (pipelined) ADC, Continuous Approximation formula (successive-approximation-register; SAR) ADC etc.The each have their own advantage of these frameworks, can select according to different application demands conventionally.Wherein, Continuous Approximation formula ADC is compared with other frameworks consumption lower-wattages, compared with small size and lower cost.
Traditionally, SAR ADC adopts binary search algorithm (binary search algorithm) to obtain the digital output code matching with input signal.In transfer process, according to the comparative result of comparator each time, D/A conversion circuit in SAR ADC conventionally all need the to add deduct voltage of a binary system ratio, after last bit period (bit cycle) finishes, the gap of input signal and reference voltage will be less than a least significant bit (least significant bit; LSB).Yet, when input signal hour, it is easily subject to noise jamming (this interference comprises the interference of comparator, chip system itself, power supply etc.), and then causes judging by accident.
Summary of the invention
In one embodiment, a kind of Continuous Approximation formula analog-digital conversion method comprises: by an analog signal being sampled to produce one first current potential, utilizing a comparator sequentially to produce a plurality of carry-out bits and export a digital signal based on these a little carry-out bits according to a plurality of the second current potentials that recur on this first current potential and this D/A conversion circuit.In this, these a little second current potentials correspond respectively to these carry-out bits.Wherein, the generation step of last carry-out bit comprises utilizes a comparator repeatedly to compare continuously the first current potential and last the second current potential occurring, to obtain a plurality of the first comparative results and to produce last carry-out bit according to these a little first comparative results.
In another embodiment, a kind of Continuous Approximation formula analog-digital conversion method comprises: by an analog signal being sampled to produce one first current potential, utilizing a comparator sequentially to produce a plurality of carry-out bits and export a digital signal based on these a little carry-out bits according to a plurality of the second current potentials that recur on this first current potential and this D/A conversion circuit.Wherein, the generation step of last j carry-out bit in these a little carry-out bits comprises: utilize a comparator repeatedly to compare continuously the first current potential and last the second current potential occurring, to obtain respectively a plurality of the first comparative results and to produce a last j carry-out bit according to these first comparative results.In this, j is greater than 1 integer.
In another embodiment, a kind of Continuous Approximation formula analog-digital converter comprises: a sampling and D/A conversion circuit, a comparator and a Continuous Approximation formula control circuit.One Continuous Approximation formula control circuit comprises: one first decision module, at least one the second decision module and an output logic.The first decision module corresponding to a plurality of decisions during in last position determine during, and one of them during corresponding to all the other decisions of each second decision module.
Sampling and D/A conversion circuit are by sampling to produce one first current potential to an analog signal.During determining in last position, comparator carries out repeatedly comparing to obtain respectively a plurality of the first comparative results to one second current potential on the first current potential and sampling and D/A conversion circuit continuously, and the first decision module produces one group of last carry-out bit according to these a little first comparative results.During each in during all the other decisions determines, comparator carries out once relatively to obtain the second corresponding comparative result the first current potential and the second current potential, and the second corresponding decision module produces a carry-out bit according to the second comparative result of correspondence, and control sampling and D/A conversion circuit according to the second comparative result of correspondence, to be adjusted at the second current potential on sampling and D/A conversion circuit.Output logic is exported a digital signal according at least one carry-out bit and one group of last carry-out bit.
To sum up, according to Continuous Approximation formula analog-digital converter of the present invention (SAR ADC) and method thereof, increase the number of comparisons of comparator during for last several decisions, effectively to reduce noise under the situation not increasing complicated signal supervisory instrument (such as the noise jamming that comparator, chip system itself, power supply etc. the are produced) impact on the signal noise ratio of SAR ADC.Moreover, for comparative result repeatedly, can utilize majority rule, on average carry or specific coded system again, low noise energy further falls.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of Continuous Approximation formula analog-digital converter (SAR ADC) according to an embodiment of the invention.
Fig. 2 and Fig. 3 are the outline flowchart of Continuous Approximation formula (SAR) analog-digital conversion method according to an embodiment of the invention.
Fig. 4 is the schematic diagram of an embodiment of the first decision module in Fig. 1.
Fig. 5 is the part flow chart of SAR analog-digital conversion method according to another embodiment of the present invention.
Fig. 6 is the schematic diagram of SAR ADC according to another embodiment of the present invention.
Fig. 7 is the schematic diagram of an embodiment of the first decision module in Fig. 6.
Fig. 8 and Fig. 9 are according to the part flow chart of the SAR analog-digital conversion method of further embodiment of this invention.
Figure 10 is the partial schematic diagram of another embodiment of the Continuous Approximation formula control circuit in Fig. 1.
Figure 11 is the partial schematic diagram of SAR ADC according to another embodiment of the present invention.
Figure 12 is system clock, the clock signal in Figure 11 and the sequential chart of controlling an embodiment of clock.
[symbol description]
10 Continuous Approximation formula analog-digital converters (SAR ADC)
110 sampling and D/A conversion circuits
130 comparators
150 Continuous Approximation formula control circuits
151 input logics
153-1～153-N decision module
154 generation units
154-1～154-3 generation unit
155 identifying units
157 output logics
1571 logic elements
1573 output units
B1～B(N+j-1) carry-out bit
B[1:N] digital signal
B(N-1) _ a digital code
B(N-1) _ b digital code
B(N-1) _ c digital code
BN_a digital code
BN_b digital code
BN_c digital code
CKc controls clock
CKs system clock
CK1～CK(N+4) clock signal
OUT_p comparative result
OUT_n comparative result
Sc digital controlled signal
Valid useful signal
Vin analog signal
VDD supplies voltage
V1 the first current potential
V2 the second current potential
S21 samples and preserves sampled analog signals
S23 produces the second current potential according to the digital controlled signal receiving
S25 once compares to obtain a comparative result the carrying out of the first current potential on sampling and D/A conversion circuit and the second current potential on sampling and D/A conversion circuit
S27 produces a carry-out bit according to this comparative result
S29 exports to sampling and D/A conversion circuit according to this comparative result by digital controlled signal
S33 produces the second current potential according to the digital controlled signal receiving
S35 once compares to obtain a comparative result the carrying out of the first current potential on sampling and D/A conversion circuit and the second current potential on sampling and D/A conversion circuit
S37 produces a digital code according to this comparative result
S38 produces a carry-out bit according to the digital code of corresponding these a little comparative results
S39 exports to sampling and D/A conversion circuit according to these a little comparative results by digital controlled signal
S43 produces the second current potential according to the digital controlled signal receiving
S45 once compares to obtain a comparative result the carrying out of the first current potential on sampling and D/A conversion circuit and the second current potential on sampling and D/A conversion circuit
S47 produces a digital code according to this comparative result
S48 produces last carry-out bit according to the digital code of corresponding these a little comparative results
S48 ' produces a plurality of carry-out bits according to the digital code of corresponding these a little comparative results
The carry-out bit of S51 based on all exported a digital signal
Embodiment
Fig. 1 is the schematic diagram of Continuous Approximation formula analog-digital converter (SAR ADC) according to an embodiment of the invention.Fig. 2 and Fig. 3 are the outline flowchart of Continuous Approximation formula (SAR) analog-digital conversion method according to an embodiment of the invention.
With reference to Fig. 1, SAR ADC10 comprises a sampling and D/A conversion circuit 110, a comparator 130 and a Continuous Approximation formula control circuit 150.
Sampling and D/A conversion circuit 110 is coupled to two inputs of comparator 130, the output of comparator 130 is coupled to the control end that Continuous Approximation formula control circuit 150 and Continuous Approximation formula control circuit 150 are coupled to sampling and D/A conversion circuit 110.
With reference to Fig. 2, the running of SAR ADC10 starts from sample phase (sampling phase).During sample phase, Continuous Approximation formula control circuit 150 is controlled sampling and D/A conversion circuit 110 with digital controlled signal Sc, to cause sampling and 110 couples of sampled analog signals Vin of D/A conversion circuit to sample and preserve (step S21).In other words, sampling and D/A conversion circuit 110 produce one first current potential V1 by sampled analog signals Vin.
Then, SAR ADC10 enters a cycle stage (bit-cycling phase), i.e. translate phase, to determine the conversion output of numeral output.During the position cycle stage comprises sequentially N the position decision connecting.Wherein, N is greater than 1 integer.During each position determines, sampling and D/A conversion circuit 110 can be changed a position and produce one second current potential V2.In this, sampling and D/A conversion circuit 110 are only changed a position during same position determines, and by most significant digit (most significant bit; MSB) start to be converted to least significant bit (LSB) (least significant bit; LSB).
In certain embodiments, Continuous Approximation formula control circuit 150 comprises N decision module 153-1～153N and an output logic 157.
Decision module 153-1～153(N-1) be coupled in respectively between the output and sampling and D/A conversion circuit 110 control ends of comparator 130.And, decision module 153-1～153(N-1) output be connected to output logic 157.Decision module 153-1～153(N-1) each in is coupled to next decision module.
During N decision module 153-1～153N corresponds respectively to N position decision, and during everybody determines, corresponding decision module determines a carry-out bit according to output OUT_p, the OUT_n of comparator 130.
For convenience of description, below decision module 153-N is referred to as to the first decision module 153-N, and all the other decision module 153-1～153-(N-1) be referred to as second decision module 153-1～153-(N-1).
During the 1st decision, Continuous Approximation formula control circuit 150 is exported to sampling and D/A conversion circuit 110 by digital controlled signal Sc.In certain embodiments, Continuous Approximation formula control circuit 150 is according to second decision module 153-1～153(N-1) output (that is, carry-out bit B1～B(N-1)) produce digital controlled signal Sc.
Sampling and D/A conversion circuit 110 produce the second current potential V2(step S23 according to the digital controlled signal Sc receiving again).In this, digital controlled signal Sc the highest (first) position is " 1 ", and all the other positions are " 0 ".
Then, the first current potential V1 and the second current potential V2 on sampling and D/A conversion circuit 110 on 130 pairs of samplings of comparator and D/A conversion circuit 110 carries out once relatively to obtain comparative result OUT_p, OUT_n(step S25 the 1st time).In this, comparative result OUT_p, OUT_n are a differential wave.
The second decision module 153-1 produces a carry-out bit B1(step S27 according to this comparative result OUT_p, OUT_n).For instance, suppose that the first current potential V1 is input signal Vin, and the second current potential V2 is the simulation output (VDAC) after digital controlled signal Sc conversion.Now, when comparative result OUT_p, the OUT_n of comparator 130 are less than input signal Vin for simulation output VDAC, the second decision module 153-1 is set as " 1 " by the value of carry-out bit B1, that is, output signal B[1:N] the 1st be 1.Otherwise when comparative result OUT_p, the OUT_n of comparator 130 are more than or equal to input signal Vin for simulation output VDAC, the second decision module 153-1 is set as " 0 " by carry-out bit B1, that is, output signal B[1:N] the 1st be 0.
And Continuous Approximation formula control circuit 150 is controlled sampling and D/A conversion circuit 110(step S29 according to this comparative result OUT_p, OUT_n), to be adjusted at the second current potential V2 on sampling and D/A conversion circuit 110.In other words, the carry-out bit B1 that Continuous Approximation formula control circuit 150 produces according to the second decision module 153-1 adjusts and new digital controlled signal Sc is exported to sampling and D/A conversion circuit 110, to cause sampling and D/A conversion circuit 110 to produce the second current potential V2(step S23 according to new digital controlled signal Sc).Take the 1st comparative result OUT_p, OUT_n is less than input signal Vin as example as simulation output VDAC, now, the highest (first) position of digital controlled signal Sc is maintained " 1 ", inferior high (second) position is changed and is made as " 1 " by " 0 ", and all the other positions are also maintained " 0 ".Sampling and the D/A conversion circuit 110 digital controlled signal Sc that basis is new produce the second current potential V2.Similarly, if take the 1st comparative result OUT_p, OUT_n, be not less than input signal Vin as example as simulation output VDAC, the highest (first) position of digital controlled signal Sc changes and is made as " 0 ", inferior high (second) position and is changed and be made as " 1 " by " 0 ", and all the other positions are also maintained " 0 ".
Comparator 130 once compares the first current potential V1 on sampling and D/A conversion circuit 110 and the carrying out of the second current potential V2 on sampling and D/A conversion circuit 110 again, to obtain comparative result OUT_p, OUT_n(step S25 the 2nd time).
The second decision module 153-1 produces carry-out bit B2 of (settings) correspondence, i.e. output signal B[1:N again according to this comparative result OUT_p, OUT_n] the 2nd (step S27).
And Continuous Approximation formula control circuit 150 is controlled sampling and D/A conversion circuit 110(step S29 again according to this comparative result OUT_p, OUT_n), to be again adjusted at the second current potential V2 on sampling and D/A conversion circuit 110.
That is to say, by repeatedly sequentially carrying out (step S23), (step S25), (step S27) and (step S29), until during completing the decision of second-to-last position.Now, second decision module 153-1～153(N-1) produce respectively (setting) carry-out bit B1～B(N-1), i.e. output signal B[1:N] the 1st to N-1 position.
During determining in N position (, during last position determines), comparator 130 repeats the first current potential V1 and the second current potential V2 to compare to obtain a plurality of comparative result OUT_p, OUT_n, that is, continuously the first current potential V1 and the second current potential V2 are repeatedly compared.For convenience of description, the comparative result OUT_p, the OUT_n that during determining in N position, produce are referred to as the first comparative result OUT_p, OUT_n, and the comparative result OUT_p, the OUT_n that during all the other decisions, produce are referred to as the second comparative result OUT_p, OUT_n.In other words, during determining in last position, comparator 130 carries out continuously m time and relatively obtains m the first comparative result OUT_p, OUT_n.In this, m is greater than 1 integer.During determining in last position, after comparator 130 relatively completes, Continuous Approximation formula control circuit 150 can not remove to adjust the second current potential V2 on it according to each comparative result OUT_p, OUT_n control sampling and D/A conversion circuit 110, that is to say, during determining in last position, Continuous Approximation formula control circuit 150 can not change exported digital controlled signal Sc, to cause, repeatedly compares the second current potential V2 being used and remains unchanged.
In other words, in the cycle stage of same position, the first decision module is processed a plurality of comparative results continuously, and the second decision module is only processed a comparative result.
In certain embodiments, the first decision module 153-N comprises m generation unit 154 and an identifying unit 155.M generation unit 154 is coupled in respectively between the output of comparator 130 and the input of identifying unit 155.
M generation unit corresponds respectively to m the first comparative result OUT_p, OUT_n, and produces corresponding digital code according to the first comparative result OUT_p, the OUT_n of correspondence.
Fig. 4 is the schematic diagram of an embodiment of the first decision module 153-N in Fig. 1.
So that relatively 3 times (that is, m=3) be example, collocation is with reference to Fig. 3 and Fig. 4, and the first decision module 153-N comprises 3 generation unit 154-1,154-2,154-3 and an identifying unit 155 continuously.Generation unit 154-1,154-2,154-3 are coupled in respectively between the output of comparator 130 and the input of identifying unit 155.The output of identifying unit 155 is connected to control end and the output logic 157 of sampling and D/A conversion circuit 110.
During determining in N position, sampling and D/A conversion circuit 110 produce the second current potential V2(step S43 according to new digital controlled signal Sc).Then, comparator 130 carries out the 1st comparison (the N time of whole position cycle stage relatively), compares the first current potential V1 and the second current potential V2 to obtain the 1st the first comparative result OUT_p, OUT_n(step S45).Generation unit 154-1 produces a digital code B3_a(step S47 according to this first comparative result OUT_p, OUT_n).
Then, comparator 130 carries out the 2nd comparison (the N+1 time of whole position cycle stage relatively) again, compares the first current potential V1 and the second current potential V2 to obtain the 2nd the first comparative result OUT_p, OUT_n(step S45 again).Generation unit 154-2 produces a digital code B3_b(step S47 according to this first comparative result OUT_p, OUT_n again).
Then, comparator 130 carries out the 3rd comparison (the N+2 time of whole position cycle stage relatively) again, compares the first current potential V1 and the second current potential V2 to obtain the 3rd the first comparative result OUT_p, OUT_n(step S45 again).Generation unit 154-3 produces a digital code B3_c(step S47 according to this first comparative result OUT_p, OUT_n again).
After completing the number of comparisons of setting, identifying unit 155 produces (setting) last carry-out bit BN(step S48 according to digital code B3_a, B3_b, the B3_c of corresponding these 3 the first comparative result OUT_p, OUT_n).
Then, output logic 157 usings all carry-out bit B1～BN that set as a digital signal B[1:N], and by this digital signal B[1:N] circuit (step S51) of next stage exported to.
Fig. 5 is the part flow chart of SAR analog-digital conversion method according to another embodiment of the present invention.Fig. 6 is the schematic diagram of SAR ADC according to another embodiment of the present invention.
In certain embodiments, with reference to Fig. 5 and Fig. 6, the first decision module 153-N can produce a plurality of carry-out bit BN～B(N+j-1 according to the digital code of m the first comparative result OUT_p, OUT_n) (step S48 ').Wherein, j is greater than 1 integer.
Now, output logic 157 usings all carry-out bit B1～B(N+j-1) as a digital signal B[1:N+j-1], and by this digital signal B[1:N+j-1] export to next stage (step S51).
Fig. 7 is the schematic diagram of an embodiment of the first decision module 153-N in Fig. 6.
Take continuously relatively 2 times and producing 2 carry-out bits is example, and collocation is with reference to Fig. 7, and the first decision module 153-N comprises 2 generation unit 154-1,154-2 and an identifying unit 155.Generation unit 154-1,154-2 are coupled in respectively between the output of comparator 130 and the input of identifying unit 155.The output of identifying unit 155 is connected to control end and the output logic 157 of sampling and D/A conversion circuit 110.
During N position determines, comparator 130 carries out continuously 2 comparisons (N of whole position cycle stage and N+1 comparison) and sequentially obtains 2 the first comparative result OUT_p, OUT_n.Generation unit 154-1 produces a digital code B3_a according to the 1st the first comparative result OUT_p, OUT_n, and generation unit 154-2 produces a digital code B3_b(step S47 according to the 2nd the first comparative result OUT_p, OUT_n).Then, identifying unit 155 can utilize a conversion table (as following table one) to obtain latter two carry-out bit BN, B(N+1 according to digital code BN_a, BN_b) (step S48 ').
Table one
| BN_a | BN_b | BN | B（N+1） |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
In certain embodiments, in the end, during several decisions, each comparator 130 all repeatedly compares continuously, uses signal noise ratio (the signal-to-noise ratio of further lifting SAR ADC10; SNR).
In other words, k+2 position reciprocal determine during to corresponding decision module 153-(N-k+1 during N position decision) each in～153-N includes a plurality of generation units 154 and an identifying unit 155.For convenience of description, below decision module 153-N is referred to as to the first decision module 153-N, by decision module 153-(N-k+1)～153-(N-1) be referred to as the 3rd decision module 153-(N-k+1)～153-(N-1), and by all the other decision module 153-1～153-(N-1) be referred to as second decision module 153-1～153-(N-1).And, below the comparative result OUT_p, the OUT_n that during determining in N position, produce are referred to as to the first comparative result OUT_p, OUT_n, the comparative result OUT_p, the OUT_n that during determining to N-1 position during k+2 position decision reciprocal, produce are referred to as to the 3rd comparative result OUT_p, OUT_n, and the comparative result OUT_p, the OUT_n that during all the other decisions, produce are referred to as to the second comparative result OUT_p, OUT_n.
Fig. 8 and Fig. 9 are according to the part flow chart of the SAR analog-digital conversion method of further embodiment of this invention.In graphic, k is integer, and k+2 is less than the sum of carry-out bit.Figure 10 is the partial schematic diagram of another embodiment of the Continuous Approximation formula control circuit 150 in Fig. 1.
With reference to Fig. 8, Fig. 9 and Figure 10, suppose SAR ADC10 be designed to last 2 positions and determine during (that is, graphic in k=0) comparator 130 carry out respectively 3 comparisons (that is, graphic in m=0).
During second-to-last position determines when (that is, during N-1 position determines), sample and D/A conversion circuit 110 produces the second current potential V2(step S33 according to new digital controlled signal Sc).Then, comparator 130 carries out the 1st comparison during N-1 position determines, compares the first current potential V1 and the second current potential V2 to obtain one the 3rd comparative result OUT_p, OUT_n(step S35).The 3rd decision module 153-(N-1) the generation unit 154-1 in produces a digital code B(N-1 according to this 3rd comparative result OUT_p, OUT_n) _ a(step S37).
Then, comparator 130 carries out the 2nd comparison during N-1 position determines again, compares the first current potential V1 and the second current potential V2 to obtain one the 3rd comparative result OUT_p, OUT_n(step S35 again).The 3rd decision module 153-(N-1) the generation unit 154-2 in produces a digital code B(N-1 according to this 3rd comparative result OUT_p, OUT_n) _ b(step S37).
Then, comparator 130 carries out the 3rd comparison during N-1 position determines again, compares the first current potential V1 and the second current potential V2 to obtain one the 3rd comparative result OUT_p, OUT_n(step S35 again).The 3rd decision module 153-(N-1) the generation unit 154-3 in produces a digital code B(N-1 according to this 3rd comparative result OUT_p, OUT_n) _ c(step S37).
Before completing the number of comparisons setting during this decision, Continuous Approximation formula control circuit 150 can not change exported digital controlled signal Sc, to cause, repeatedly compares the second current potential V2 being used and remains unchanged.
After completing the number of comparisons of setting, the 3rd decision module 153-(N-1) the 3rd comparative result OUT_p, the digital code B(N-1 of OUT_n that the identifying unit 155 in produces according to corresponding this 3 comparisons) _ a, B(N-1) _ b, B(N-1) _ c produces (setting) N-1 carry-out bit B(N-1) (step S38).
Continuous Approximation formula control circuit 150 is controlled sampling and D/A conversion circuit 110(step S39 again according to this little the 3rd comparative result OUT_p, OUT_n), to be again adjusted at the second current potential V2(step 43 on sampling and D/A conversion circuit 110).In other words, Continuous Approximation formula control circuit 150 is based on the 3rd decision module 153-(N-1) in N-1 carry-out bit B(N-1 setting of identifying unit 155) adjust and digital controlled signal Sc exported to sampling and D/A conversion circuit 110.
During determining in N position, collocation is with reference to Fig. 3 or Fig. 5, sampling and D/A conversion circuit 110 are adjusted the second current potential V2(step 43 according to new digital controlled signal Sc) afterwards, 130 couples of the first current potential V1 of comparator and the second current potential V2 carry out 3 comparisons continuously, to obtain three the first comparative result OUT_p, OUT_n(step 45).And generation unit 154-1, the 154-2 in the first decision module 153-N, 154-3 produce digital code BN_a, BN_b, BN_c(step 47 according to this little the first comparative result OUT_p, OUT_n respectively).Then, the identifying unit 155 in the 3rd decision module 153-N produces (setting) N carry-out bit BN(step S48 according to digital code BN_a, BN_b, the BN_c of the first comparative result OUT_p, the OUT_n that produce corresponding to this 3 comparisons again) or produce N and N+1 carry-out bit BN, B(N+1) (step S48 ').
In other words, in the cycle stage of same position, the first decision module and the 3rd decision module are all processed a plurality of comparative results, and the second decision module is only processed a comparative result.Moreover a plurality of generation units in same decision module correspond respectively to a plurality of comparative results that produce during same position determines.And, during the decision of last position, during determining for the position that is set as repeatedly comparing, before completing the number of comparisons setting during this decision, Continuous Approximation formula control circuit 150 can not change exported digital controlled signal Sc, to cause, repeatedly compares the second current potential V2 being used and remains unchanged.
In certain embodiments, during last several decisions, when each comparator 130 all carries out repeatedly relatively continuously, comparator 130 is carried out all identical, equal differences or part is identical and part difference of number of times relatively during each decision.For instance, suppose the k=0 in Fig. 8, SAR ADC10 can be as the design of above-mentioned example, (yet SAR ADC10 also can be designed to comparator 130 carries out continuously 2 comparisons during N-1 position determines, the 3rd decision module has 2 generation units), and carry out continuously 3 comparisons (that is, the first decision module has 3 generation units) during N position determines.
In step S38 or step S48, the mode that identifying unit 155 can majority rule or obtain corresponding carry-out bit in the average mode of carry again.
Take N position determine during and m=3 be example, identifying unit 155 carries out the majority rule of corresponding digital code BN_a, BN_b, BN_c to obtain last carry-out bit BN, as following table two.
Table two
| BN_a | BN_b | BN_c | BN |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
In other words, when utilizing the mode of majority rule, m is necessary for odd number, that is, the number of comparisons of comparator 130 during this decision is odd number.
Take again N position determine during and m=3 be example, identifying unit 155 carry out corresponding digital code BN_a, BN_b, BN_c on average again carry (decimal fractions rounds up) to obtain last carry-out bit BN, as following table three.
Table three
| BN_a | BN_b | BN_c | On average | BN |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0.33 | 0 |
| 0 | 1 | 0 | 0.33 | 0 |
| 0 | 1 | 1 | 0.67 | 1 |
| 1 | 0 | 0 | 0.33 | 0 |
| 1 | 0 | 1 | 0.67 | 1 |
| 1 | 1 | 0 | 0.67 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Figure 11 is the partial schematic diagram of SAR ADC according to another embodiment of the present invention.
Take N=3 as example, with reference to Figure 11, in this embodiment, the 1st and 2 positions determine during comparator 130 carry out respectively 1 comparison, and during determining in the 3rd position, comparator 130 carries out 3 comparisons.
Continuous Approximation formula control circuit 150 comprises input logic 151, the second decision module 153-1,153-2, the first decision module and output logic.The first decision module comprises three generation unit 154-1,154-2,154-3 and an identifying unit 155.Output logic comprises a logic module 1571 and an output unit 1573.Two inputs of input logic 151 couple positive output end and the negative output terminal of comparator 130.
The second decision module 153-1,153-2 can be realized by the flip-flop DFF connecting with generation unit 154-1,154-2,154-3.In this, each in the second decision module 153-1,153-2 and generation unit 154-1,154-2,154-3 includes two flip-flop DFF(for convenience of description, is below referred to as the first flip-flop DFF and the second flip-flop DFF).
The setting end of the first flip-flop DFF in the second decision module 153-1,153-2 and generation unit 154-1,154-2,154-3 or replacement termination are received system clock CKs, and set or reset according to system clock CKs.
The output of each first flip-flop DFF is coupled to corresponding to the control end of the second flip-flop DFF of identical bits or same numbers code and corresponding to the input of the first flip-flop DFF of next bit or next digital code.The input of the first flip-flop DFF of the second decision module 153-1 is coupled to feeder ear (supply voltage VDD).
In other words, the output of the first flip-flop DFF of the second decision module 153-1 is coupled to the control end of the second flip-flop DFF of the second decision module 153-1 and the input of the first flip-flop DFF of the second decision module 153-2.The output of the first flip-flop DFF of the second decision module 153-2 is coupled to the control end of the second flip-flop DFF of the second decision module 153-2 and the input of the first flip-flop DFF of generation unit 154-1.The output of the first flip-flop DFF of generation unit 154-1 is coupled to the control end of the second flip-flop DFF of generation unit 154-1 and the input of the first flip-flop DFF of generation unit 154-2.The output of the first flip-flop DFF of generation unit 154-3 is coupled to the control end of the second flip-flop DFF and the first input end of logic module 1571 of generation unit 154-3.
The input of each second flip-flop DFF is coupled to the positive output end of comparator 130.The output of the second flip-flop DFF of generation unit 154-1,154-2,154-3 is connected to the input of identifying unit 155.The output of the second flip-flop DFF of the second decision module 153-1,153-2 and the output of identifying unit 155 are coupled to the output of output unit 1573, and are electrically connected to sampling and D/A conversion circuit 110.
The output of input logic 151 is coupled to the control end of each first flip-flop DFF and the second input of logic module 1571.The 3rd input receiving system clock CKs of logic element 1571.The output of logic module 1571 is connected to the control end of output unit 1573.
Input logic 151 receives anode and the negative terminal output (comparative result OUT_p, OUT_n) of comparator 130, and the logical operation that compares result OUT_p, OUT_n is to export useful signal Valid to the control end of each first flip-flop DFF and the input of logic module 1571.In certain embodiments, input logic 151 can be a NAND gate (NAND gate).
The first flip-flop DFF of the second decision module 153-1 produces a clock signal CK1 according to useful signal Valid and supply voltage VDD.The second flip-flop DFF of the second decision module 153-1 sets the 1st carry-out bit B1 according to anode comparative result OUT_p and clock signal C K1 again.And the first flip-flop DFF of the second decision module 153-1 also offers this clock signal CK1 the first flip-flop DFF of the second decision module 153-2, the input data of usining as the first flip-flop DFF of the second decision module 153-2.
The first flip-flop DFF of the second decision module 153-2 produces a clock signal CK2 according to useful signal Valid and clock signal CK1.The second flip-flop DFF of the second decision module 153-1 sets the 2nd carry-out bit B2 according to anode comparative result OUT_p and clock signal C K2 again.And the first flip-flop DFF of the second decision module 153-2 also offers this clock signal CK2 the first flip-flop DFF of generation unit 154-1, the input data of usining as the first flip-flop DFF of generation unit 154-1.
Generation unit 154-1 carrys out clocking CK3 according to useful signal Valid and clock signal CK2.The second flip-flop DFF of generation unit 154-1 exports a digital code B3_a according to anode comparative result OUT_p and clock signal C K3 again.And the first flip-flop DFF of generation unit 154-1 also offers logic module 1571 by this clock signal CK5.
Generation unit 154-2 carrys out clocking CK4 according to useful signal Valid and clock signal CK2.The second flip-flop DFF of generation unit 154-2 exports a digital code B3_b according to anode comparative result OUT_p and clock signal C K4 again.And the first flip-flop DFF of generation unit 154-2 also offers this clock signal CK4 the first flip-flop DFF of generation unit 154-3, the input data of usining as the first flip-flop DFF of generation unit 154-3.
Generation unit 154-3 carrys out clocking CK5 according to useful signal Valid and clock signal CK4.The second flip-flop DFF of generation unit 154-3 exports a digital code B3_c according to anode comparative result OUT_p and clock signal C K5 again.And the first flip-flop DFF of generation unit 154-1 also offers logic module 1571 by this clock signal CK5.
155 of identifying units are set the 3rd carry-out bit B3 according to digital code B3_a, B3_b, B3_c.In this, identifying unit 155 can majority rule or on average again the mode such as carry decide the 3rd carry-out bit B3.
Logic element 1571 produces a control clock CKc according to system clock CKs, useful signal Valid and clock signal CK5, to cause output unit 1573 read the 1st carry-out bit B1, the 2nd carry-out bit B2 and the 3rd carry-out bit B3 and be output as an output signal B[1:3 according to controlling clock CKc].In certain embodiments, logic element 1571 can or door (OR gate) realize.
In this embodiment, the sequential relationship of system clock CKs, clock signal C K1～CK5 and control clock CKc as shown in figure 12.
Wherein, sampling and D/A conversion circuit 110 consist essentially of a plurality of switches and a plurality of electric capacity.The first end of these a little electric capacity is connected to an input of comparator 130, and the second end optionally receives a reference voltage by switch.Continuous Approximation formula control circuit 150 is coupled to the control end of these switches, and the running by controlling these a little switches is to determine the current potential (as, the second current potential V2) of the first end of these a little electric capacity.In certain embodiments, sampling and D/A conversion circuit 110 can comprise sampling preservation circuit and digital analog converter, or are a capacitance digital analog converter.Due to sampling and the enforcement aspect of D/A conversion circuit and in detail running system be well known to those skilled in the art, therefore repeat no more in this.
To sum up, according to Continuous Approximation formula analog-digital converter of the present invention (SAR ADC) and method thereof, increase the number of comparisons of comparator during for last several decisions, effectively to reduce noise (such as the noise jamming that comparator, chip system itself, power supply etc. the are produced) impact on the signal noise ratio of SAR ADC in the situation that do not increase complicated signal supervisory instrument.Moreover, for comparative result repeatedly, can utilize majority rule, on average carry or specific coded system again, low noise energy further falls.
Although the present invention discloses as above with above-described embodiment; so these embodiment are not in order to limit the present invention; for any those of ordinary skill in this area; without departing from the spirit and scope of the present invention; can make change and revise, therefore scope of patent protection of the present invention must be defined and is as the criterion with this specification claims.
Claims (18)
1. a Continuous Approximation formula analog-digital conversion method, comprising:
By an analog signal being sampled to produce one first current potential;
Utilize a comparator sequentially to produce a plurality of carry-out bits according to a plurality of the second current potentials that recur on described the first current potential and D/A conversion circuit, wherein, described the second current potential corresponds respectively to described carry-out bit; And
Based on described carry-out bit, export a digital signal;
Wherein, the generation step of last carry-out bit in described carry-out bit comprises:
Utilize described comparator continuously the second current potential of the last generation in described the first current potential and described the second current potential repeatedly to be compared, to obtain a plurality of the first comparative results; And
According to described the first comparative result, produce described last carry-out bit.
2. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, the step that produces described last carry-out bit according to described the first comparative result comprises:
According to described first comparative result of described comparator, produce respectively a plurality of digital codes; And
Described digital code carried out to majority rule to obtain described last carry-out bit.
3. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, the step that produces corresponding described last carry-out bit according to described the first comparative result comprises:
According to described first comparative result of described comparator, produce respectively a plurality of digital codes; And
Described digital code is averaged to carry to obtain described last carry-out bit again.
4. Continuous Approximation formula analog-digital conversion method according to claim 1, wherein, the inverse in described carry-out bit the 2nd to the generation step of carry-out bit described in each in k carry-out bit reciprocal comprises:
Utilize described comparator continuously described the first current potential repeatedly to be compared with corresponding described the second current potential, to obtain a plurality of the 3rd comparative results;
According to described the 3rd comparative result, control described D/A conversion circuit, to adjust described the second current potential on described D/A conversion circuit; And
According to described the 3rd comparative result, produce corresponding described carry-out bit;
Wherein, k is integer, and k+2 is less than the sum of described carry-out bit.
5. Continuous Approximation formula analog-digital conversion method according to claim 4, wherein, the step that produces corresponding described carry-out bit according to described the 3rd comparative result comprises:
According to described the 3rd comparative result, produce respectively a plurality of digital codes; And
Described digital code is carried out to majority rule to obtain corresponding described carry-out bit.
6. Continuous Approximation formula analog-digital conversion method according to claim 4, wherein, the step that produces corresponding described carry-out bit according to described the 3rd comparative result comprises:
According to described the 3rd comparative result, produce respectively a plurality of digital codes; And
Described digital code is averaged to carry to obtain corresponding described carry-out bit again.
7. according to the Continuous Approximation formula analog-digital conversion method described in any one in claim 1 to 6, wherein, the generation step of carry-out bit comprises described in each in all the other carry-out bits in described carry-out bit:
Utilize described comparator once to compare with corresponding described the second current potential described the first current potential, to obtain one second comparative result;
According to described second comparative result of described comparator, control described D/A conversion circuit, to adjust described the second current potential on described D/A conversion circuit; And
According to described the second comparative result, produce corresponding described carry-out bit.
8. a Continuous Approximation formula analog-digital conversion method, comprising:
By an analog signal being sampled to produce one first current potential;
Utilize a comparator sequentially to produce a plurality of carry-out bits according to a plurality of the second current potentials that recur on described the first current potential and D/A conversion circuit; And
Based on described carry-out bit, export a digital signal;
Wherein, the generation step of last j carry-out bit in described carry-out bit comprises:
Utilize a comparator continuously the second current potential of the last generation in described the first current potential and described the second current potential repeatedly to be compared, to obtain respectively a plurality of the first comparative results; And
According to described first comparative result of described comparator, produce described last j carry-out bit, wherein, j is greater than 1 integer.
9. Continuous Approximation formula analog-digital conversion method according to claim 8, wherein, the described step that produces a described last j carry-out bit according to described the first comparative result comprises:
According to described the first comparative result, produce respectively at least three digital codes; And
Utilize a conversion table to decide described last j carry-out bit according to described digital code.
10. Continuous Approximation formula analog-digital conversion method according to claim 8 or claim 9, wherein, the second current potential that the second current potential to the in described the second current potential the 1st time occurring occurs for j-1 time is sequentially corresponding to the 1st carry-out bit to a j-1 carry-out bit in described carry-out bit, and described the 1st carry-out bit extremely the generation step of each carry-out bit in described j-1 carry-out bit comprise:
Utilize described comparator once to compare with corresponding described the second current potential described the first current potential, to obtain one second comparative result;
According to described the second comparative result, control described D/A conversion circuit, to adjust described the second current potential on described D/A conversion circuit; And
According to described the second comparative result, produce corresponding described carry-out bit.
11. 1 kinds of Continuous Approximation formula analog-digital converters, comprising:
One sampling and D/A conversion circuit, in order to by sampling to produce one first current potential to an analog signal;
One comparator, during last decision in being used to during a plurality of decisions, continuously one second current potential on described the first current potential and described sampling and D/A conversion circuit is carried out repeatedly relatively to obtain respectively a plurality of the first comparative results, and during determining in all the other positions, respectively described the first current potential is once compared to obtain the second corresponding comparative result with the carrying out of described the second current potential; And
One Continuous Approximation formula control circuit, comprising:
One first decision module, during being used to described last decision, produces one group of last carry-out bit according to described the first comparative result;
At least one the second decision module, one of them during corresponding to described all the other decisions of the second decision module described in each, during determining with the institute's rheme in corresponding, according to described second comparative result of correspondence, produce a carry-out bit, and control described sampling and D/A conversion circuit according to described second comparative result of correspondence, to adjust described the second current potential on described sampling and D/A conversion circuit; And
One output logic, in order to export a digital signal according to described carry-out bit and described group of last carry-out bit.
12. Continuous Approximation formula analog-digital converters according to claim 11, wherein, the figure place of described group of last carry-out bit is positive integer, and is less than or equal to the number of comparisons of described comparator.
13. Continuous Approximation formula analog-digital converters according to claim 11, wherein, described group of last carry-out bit is a last carry-out bit, and described the first decision module comprises:
A plurality of generation units, correspond respectively to described the first comparative result, and described in each, generation unit produces a digital code in order to described the first comparative result according to correspondence; And
One identifying unit, in order to carry out majority rule to obtain described last carry-out bit to described digital code.
14. Continuous Approximation formula analog-digital converters according to claim 11, wherein, described group of last carry-out bit is a last carry-out bit, and described the first decision module comprises:
A plurality of generation units, correspond respectively to described the first comparative result, and described in each, generation unit produces a digital code in order to described the first comparative result according to correspondence; And
One identifying unit, in order to average carry to obtain described last carry-out bit again to described digital code.
15. Continuous Approximation formula analog-digital converters according to claim 11, wherein, described group of last carry-out bit is a plurality of last carry-out bits, and described the first decision module comprises:
A plurality of generation units, correspond respectively to described the first comparative result, and described in each, generation unit produces a digital code in order to described the first comparative result according to correspondence; And
One identifying unit, in order to utilize a conversion table according to the described last carry-out bit of described digital code output.
16. Continuous Approximation formula analog-digital converters according to claim 11, wherein, during each decision in during described comparator is also used to the 2nd to k position and determines, the carrying out of described the first current potential and described the second current potential repeatedly compared to obtain respectively a plurality of the 3rd comparative results, and described Continuous Approximation formula control circuit also comprises:
At least one the 3rd decision module, during corresponding respectively to described the 2nd to k position decision reciprocal, during determining, produces corresponding carry-out bit according to described the 3rd comparative result of described comparator with the institute's rheme in corresponding.
17. Continuous Approximation formula analog-digital converters according to claim 16, wherein, described in each, the 3rd decision module comprises:
A plurality of generation units, correspond respectively to described the 3rd comparative result producing during same institute rheme determines, described in each, generation unit produces a digital code in order to described the 3rd comparative result according to correspondence; And
One identifying unit, in order to carry out majority rule to obtain corresponding described carry-out bit to described digital code.
18. Continuous Approximation formula analog-digital converters according to claim 16, wherein, described in each, the 3rd decision module comprises:
A plurality of generation units, correspond respectively to described the 3rd comparative result producing during same described decision, and described in each, generation unit produces a digital code in order to described the 3rd comparative result according to correspondence; And
One identifying unit, in order to average carry to obtain corresponding described carry-out bit again to described digital code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310173319.XA CN104143983B (en) | 2013-05-10 | 2013-05-10 | Continuous Approximation formula analog-digital converter and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310173319.XA CN104143983B (en) | 2013-05-10 | 2013-05-10 | Continuous Approximation formula analog-digital converter and its method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104143983A true CN104143983A (en) | 2014-11-12 |
| CN104143983B CN104143983B (en) | 2017-08-15 |
Family
ID=51853067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310173319.XA Active CN104143983B (en) | 2013-05-10 | 2013-05-10 | Continuous Approximation formula analog-digital converter and its method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104143983B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712772A (en) * | 2015-11-18 | 2017-05-24 | 瑞昱半导体股份有限公司 | Successive approximation analog to digital converter testing method and circuit |
| CN106817128A (en) * | 2015-12-01 | 2017-06-09 | 瑞昱半导体股份有限公司 | The method and its digital correction circuit of adaptivity adjustment coded system |
| CN107306135A (en) * | 2016-04-22 | 2017-10-31 | 瑞昱半导体股份有限公司 | The correcting circuit of digital analog converter and bearing calibration |
| CN107493104A (en) * | 2016-06-13 | 2017-12-19 | 瑞昱半导体股份有限公司 | Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297614A (en) * | 1998-04-20 | 2001-05-30 | 艾利森电话股份有限公司 | Analog-to-digital converter with successive approximation |
| CN101379707A (en) * | 2006-02-02 | 2009-03-04 | 新加坡国立大学 | An analog-to-digital converter |
| CN101682332A (en) * | 2007-06-06 | 2010-03-24 | Nxp股份有限公司 | Circuit with a successive approximation analog to digital converter |
| US20100127908A1 (en) * | 2008-11-26 | 2010-05-27 | Analog Devices, Inc. | Self-timed clocked analog to digital converter |
| CN101800549A (en) * | 2009-02-09 | 2010-08-11 | 义隆电子股份有限公司 | Analog-to-digital converter capable of switching bit resolution and control method thereof |
| WO2011151671A1 (en) * | 2010-06-02 | 2011-12-08 | Indian Institute Of Technology Bombay | Successive approximation register analog to digital converter circuit |
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| US20120112938A1 (en) * | 2010-11-08 | 2012-05-10 | Seiko Epson Corporation | A/d converter circuit, electronic apparatus and a/d conversion method |
| CN102571094A (en) * | 2010-12-10 | 2012-07-11 | 乐金显示有限公司 | Successive approximation register analog-to-digital converter and analog-to-digital conversion method using the same |
-
2013
- 2013-05-10 CN CN201310173319.XA patent/CN104143983B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297614A (en) * | 1998-04-20 | 2001-05-30 | 艾利森电话股份有限公司 | Analog-to-digital converter with successive approximation |
| CN101379707A (en) * | 2006-02-02 | 2009-03-04 | 新加坡国立大学 | An analog-to-digital converter |
| CN101682332A (en) * | 2007-06-06 | 2010-03-24 | Nxp股份有限公司 | Circuit with a successive approximation analog to digital converter |
| US20100127908A1 (en) * | 2008-11-26 | 2010-05-27 | Analog Devices, Inc. | Self-timed clocked analog to digital converter |
| CN101800549A (en) * | 2009-02-09 | 2010-08-11 | 义隆电子股份有限公司 | Analog-to-digital converter capable of switching bit resolution and control method thereof |
| WO2011151671A1 (en) * | 2010-06-02 | 2011-12-08 | Indian Institute Of Technology Bombay | Successive approximation register analog to digital converter circuit |
| US20120112938A1 (en) * | 2010-11-08 | 2012-05-10 | Seiko Epson Corporation | A/d converter circuit, electronic apparatus and a/d conversion method |
| CN102571094A (en) * | 2010-12-10 | 2012-07-11 | 乐金显示有限公司 | Successive approximation register analog-to-digital converter and analog-to-digital conversion method using the same |
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712772A (en) * | 2015-11-18 | 2017-05-24 | 瑞昱半导体股份有限公司 | Successive approximation analog to digital converter testing method and circuit |
| CN106712772B (en) * | 2015-11-18 | 2020-03-24 | 瑞昱半导体股份有限公司 | Test method and test circuit of successive approximation type analog-digital converter |
| CN106817128A (en) * | 2015-12-01 | 2017-06-09 | 瑞昱半导体股份有限公司 | The method and its digital correction circuit of adaptivity adjustment coded system |
| CN106817128B (en) * | 2015-12-01 | 2020-07-10 | 瑞昱半导体股份有限公司 | Method for self-adaptive regulating coding mode and its digital correcting circuit |
| CN107306135A (en) * | 2016-04-22 | 2017-10-31 | 瑞昱半导体股份有限公司 | The correcting circuit of digital analog converter and bearing calibration |
| CN107306135B (en) * | 2016-04-22 | 2020-03-10 | 瑞昱半导体股份有限公司 | Correction circuit and correction method for digital-to-analog converter |
| CN107493104A (en) * | 2016-06-13 | 2017-12-19 | 瑞昱半导体股份有限公司 | Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof |
| CN107493104B (en) * | 2016-06-13 | 2020-11-27 | 瑞昱半导体股份有限公司 | Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104143983B (en) | 2017-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103905049B (en) | A kind of high-speed flash adds alternately comparison expression gradually-appoximant analog-digital converter | |
| US9432046B1 (en) | Successive approximation analog-to-digital converter | |
| TWI524679B (en) | Successive-approximation-register analog-to-digital converter (sar adc) and method therefor | |
| CN105007079A (en) | Fully differential increment sampling method of successive approximation type analog-digital converter | |
| TWI521887B (en) | Successive approximation register anolog-to-digital converter | |
| US20140184434A1 (en) | Analog/digital converter | |
| US7535391B1 (en) | Analog-to-digital converter having random capacitor assignment and method thereof | |
| US10084470B2 (en) | Analogue-digital converter of non-binary capacitor array with redundant bit and its chip | |
| CN105306059A (en) | Successive approximation analog to digital converter device | |
| TWI532328B (en) | Analog to digital converter and converting method thereof | |
| CN102904573A (en) | Analog-to-digital converters and analog-to-digital conversion methods | |
| TW201715849A (en) | Successive approximation register (SAR) analog- to-digital converter (ADC) circuit and method thereof | |
| CN110190854B (en) | Two-step SAR ADC-oriented shared reference voltage realization circuit and method | |
| CN103095300A (en) | Successive approximation register analog-to-digital converter and conversion method thereof | |
| CN104143983A (en) | Continuous approximation type analog-digital converter and method thereof | |
| CN111800132A (en) | Segmented architecture analog-to-digital converter | |
| TWI479806B (en) | Analog-to-digital converting system | |
| CN106341133A (en) | Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter | |
| CN101207384A (en) | Analog-to-digital converting system | |
| CN106656190A (en) | Continuous approximation type analog-to-digital conversion circuit and method therefor | |
| CN112994699B (en) | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method | |
| JP2014236373A (en) | A/d conversion device | |
| CN110198167B (en) | Asymmetric SAR ADC capacitance switch sequential circuit and method | |
| Choi et al. | A low energy two-step successive approximation algorithm for ADC design | |
| CN102195651B (en) | High-speed analogue-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |