TWI479806B - Analog-to-digital converting system - Google Patents

Description

Analog to digital conversion system

The present invention is generally related to analog to digital conversion systems and, more specifically, to analog to digital conversion systems by using a cascade of flash analog to digital converters and progressively analog to digital converters.

Analog to digital converters (ADCs) have a variety of architectures, such as fast analog to digital converters (flash ADCs), pipeline analog to digital converters (pipeline ADCs), and step-by-step analog-to-digital converters (SA ADCs) These have appropriate application areas.

Flash ADCs are typically the fastest, but have the highest implementation cost. In the N-bit ADC, there are 2 ^N possible digital digital outputs. The total 2 ^N -1 boundary defines the analog input range corresponding to the digital digital output. In a flash ADC, a 2 ^N -1 analog reference signal is generated. The input is compared to each reference signal simultaneously. 2 ^N -1 comparators produce a digital output signal that is decoded to produce the desired digital output number.

Because the input-to-output delay includes the response time of a comparator stage and subsequent decoding logic, the flash ADC is the fastest. Because the analog reference signal and the number of comparators increase exponentially with N, flash ADCs can be implemented at a large cost.

The SA ADC system is much slower than a flash ADC, but has a relatively low implementation cost when it has a large N. In the progressive method, a binary tree search is performed on the possible digital output numbers. The binary tree search is performed in the order of the N-forward steps. In each step, it is possible that the digital output number is passed to an N-bit digit to an analog to analog (D/A) converter that produces a corresponding analog value. This value is compared to the analog input signal. The result of the comparison is used in the following steps to select a new possible digit value.

For components, N-bit SA ADCs require a comparator, N-bit D/A converter, and logic to direct the search and store results. The converter and comparator can be reused in the search for each step. The speed of the SA converter depends on the N and the settling time of the comparator, D/A converter and logic circuit. For example, a 12-bit SA ADC would require 12 comparison steps for 12 separate 12-bit D/A conversion results, while an 8-bit SA ADC would only require 8 separate D/A conversion results for 8 Comparison step.

The main disadvantage of prior art flash ADCs is that although they are very fast, they typically require a large number of components, occupying a large amount of wafer space and consuming a large amount of power. The number of components increases with the exponential increase and the power consumption of the flash ADC limits the amount of economic efficiency that these converters can achieve. The main drawbacks of SA ADCs are that they have low component cost and are economical for higher accuracy than flash ADCs, but they are usually slow and do not work effectively with the resources consumed. Accordingly, it is an object of the present invention to provide a novel ADC that is fast enough and low complexity.

Accordingly, it is an object of the present invention to provide an analog to digital conversion system for converting an analog input signal to a digital output signal. An analog to digital conversion system for converting an analog input signal to a digital output signal includes: a tracking and holding circuit for tracking the input signal in a tracking mode and maintaining the tracked input signal in a hold mode; a voltage generator for generating a first reference voltage and a second reference voltage; a coarse analog to digital converter for converting the output signal of the tracking and holding circuit into a first digital code and having a first digital to analog converter The first digital code is converted into a first analog signal, wherein the first digital code is related to the most efficient bit of the digital output signal of the analog to digital conversion system; a subtractor is used for the tracking And subtracting the first analog signal from the output signal of the hold circuit; a fine analog to digital conversion means for converting the output signal of the subtractor to a second digital code according to the second reference voltage, wherein the second digital bit The code system has the least significant bit group of the digital output signal of the analog to digital conversion system.

The preferred embodiments of the present invention will now be described in detail, and the examples of the present embodiments are illustrated in the accompanying drawings. In the drawings, the same reference numerals are used to identify the same or similar elements.

In this embodiment of the invention, an analog to digital conversion (ADC) system employs a dual-ranging technique based on a two-step architecture where the coarse ADC uses a flash ADC architecture and the thin ADC uses a SA (step-by-step) ADC. Architecture. Therefore, the present invention can obtain a high sampling frequency and low power consumption.

Referring to FIG. 1, a circuit block diagram of an ADC system 100 for outputting (m+n-1)-bit digital code in accordance with the present invention. The ADC system 100 of FIG. 1 includes a tracking and holding circuit (T/H circuit) 10, a coarse ADC 20, a subtractor 40, a fine ADC 50, and a digital error correction unit 80.

During the tracking mode, the T/H circuit 10 will track an input signal. During the hold mode, the T/H circuit 10 will hold the tracked input signal and pass the input signal to the subsequent stage circuits (coarse ADC 20, subtractor 40, and fine ADC 50).

The coarse ADC 20 receives the output signal V1 of the T/H circuit 10, performs high bit data conversion to generate a digital code MSB, and sends the digital code MSB to the digital error correcting unit 80. The code MSB is the most efficient byte MSB for the final result (m+n-1). The coarse ADC 20 includes an m-bit flash ADC 22 and an m-bit digital to analog converter (DAC) 30, the connection is used to determine the m-bit code MSB and is used to output corresponding to the final result (m+n) -1) - Analog signal V2 of the MSB of the bit digit code.

The subtractor 40 receives the sample analog signal V1 from the T/H circuit 10 and the analog signal V2 from the m-bit DAC 30 to subtract the V2 from the received signal V1 such that the analog signal Vt corresponds to the final result (m+n-1) ) - LSB of the bit digit code.

The fine ADC 50 is an n-bit progressive progressive converter (SA ADC) that receives the analog signal Vt from the subtractor 40. The n-bit SA ADC 50 then quantizes the analog signal Vt into an n-bit LSB code.

The digital error correction unit 80 combines the codes MSB and LSB (generated by the flash ADC 22 and the SA ADC 50, respectively), in which the final result of the (m+n-1)-bit digital code is generated.

2 shows a detailed circuit diagram of the ADC system 100 of FIG. This ADC system 100 is described as a 9-bit flash-SA dual-interval ADC in which the flash ADC 22 and the SA ADC 50 are implemented in a 5-bit architecture, respectively.

The T/H circuit 10 samples the continuous input signal to become the discrete signal V1. The 5-bit flash ADC 22 includes a reference ladder circuit 23, a preamplifier 24, a comparator 25, and a 5-bit encoder 26, which are connected in a series architecture.

The reference ladder circuit 23 provides an appropriate reference voltage, each of which is supplied to the inverting (-) input terminal of the individual preamplifier of the preamplifier 24. The discrete signal V1 is coupled to the non-inverting (+) input of each preamplifier 24. The comparator 25 then quantizes the output signal of the preamplifier 24 to become a thermometer code. The 5-bit encoder 26 converts the temperature code into a 5-bit coarse code MSB for output to the digital error correcting unit 80.

As shown, the 5-bit DAC 30 generates an analog voltage V2 by capacitively switching the 5-bit coarse code MSB by the 5-bit encoder 26. The subtracter 40 receives the sampling analog signal V1 from the T/H circuit 10 and the analog signal V2 from the m-bit DAC 30 and outputs an analog signal Vt.

The SA ADC 50 includes a comparator 60, a 5-bit capacitive DAC 62, and an SA logic circuit 64. The 5-bit capacitive DAC 62 produces a reference voltage VF. The comparator 60 compares the output signal Vt from the subtractor 52 with the reference voltage VF from the capacitive DAC 62 and outputs an analog signal VL. The SA logic circuit 64 receives the analog signal VL and quantizes it into a 5-bit fine code LSB for output to the capacitive DAC 62 and the digital error correction unit 80.

The outputs of the codes MSB and LSB (generated for the flash ADC 22 and the SA ADC 50) are in the digital error correction unit 80 by the most efficient bit (D _L4 ) of the overlapping code LSB and the least significant bit of the code MSB (D _{M0 )} And add up so that the overall digital output is a 9-bit (D ₀ -D ₈ ) digital signal.

As shown in FIG. 2, in addition to the T/H circuit 10, the coarse ADC 20, the fine ADC 50, and the digital error correction unit 80 as shown in FIG. 1, the ADC system 100 of the present invention further includes a reference voltage generator 90 on the wafer. Capacitive DACs are supplied to capacitive DACs 30 and V2P and V2N to generate appropriate reference voltages V1P, V1N.

It will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the scope and spirit of the invention. Accordingly, the invention is intended to be included within the scope of the appended claims

10. . . T/H circuit

20. . . Rough ADC

twenty two. . . M-bit flash ADC

30. . . M-bit DAC

40. . . Subtractor

50. . . Fine ADC

80. . . Digital error correction unit

twenty three. . . Reference ladder

twenty four. . . Preamplifier

25. . . Comparators

26. . . 5-bit encoder

60. . . Comparators

62. . . 5-bit capacitive DAC

64. . . SA logic circuit

90. . . On-wafer reference voltage generator

100. . . ADC system

The drawings are included to provide a further understanding of the invention and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description of the invention

1 is a block diagram of an analog to digital conversion system provided in accordance with the present invention;

2 is an exemplary circuit diagram of the analog to digital conversion system of FIG.

10. . . T/H circuit

20. . . Rough ADC

twenty two. . . M-bit flash ADC

30. . . M-bit DAC

40. . . Subtractor

50. . . Fine ADC

80. . . Digital error correction unit

100. . . ADC system

Claims (4)

An analog to digital conversion system for converting an analog input signal into a digital output signal, comprising: a tracking and holding circuit for tracking the input signal in a tracking mode and maintaining the tracked input in a hold mode a signal; a reference voltage generator for generating a first reference voltage and a second reference voltage; a flash analog to digital converter for converting the output signal of the tracking and holding circuit into a first digital code and having a first digit An analog to converter for converting the first digital code into a first analog signal, wherein the first digital code is related to a most efficient byte of the digital output signal of the analog to digital conversion system; a subtractor Subtracting the first analog signal from the output signal of the tracking and holding circuit; and progressively converting the analog to digital converter to convert the output signal of the subtractor to the second digital code according to the second reference voltage, Wherein the second digit code has a least significant bit group of the digital output signal of the analog to digital conversion system; and an error correction circuit for Combining the most efficient bit with the least significant bit of the least significant bit of the digital output signal of the digit conversion system with the least significant bit of the most efficient byte, combining the most efficient byte with the least significant byte To generate the digital output signal. An analog to digital conversion system as described in claim 1 wherein the step-by-step analog to digital converter comprises: a second digit to analog converter for converting the second digit code into a second analog signal; a comparator for comparing the second analog signal with an output signal of the subtractor; and stepwise forcing the logic circuit The output signal of the comparator is converted into a second digital code. An analog to digital conversion system as described in claim 1, wherein the flash analog to digital converter comprises: a reference ladder circuit for generating a majority of reference voltages; and a plurality of preamplifiers, each of which is derived from the reference ladder circuit The reference voltage is analogous to the analog signal; and corresponds to most comparators. An analog to digital conversion system as described in claim 3, wherein the flash A/D converter establishes a temperature code based on a comparison result of the plurality of comparators.