CN111295843B

CN111295843B - Pipeline analog-to-digital converter with at least three sampling channels

Info

Publication number: CN111295843B
Application number: CN201780093363.6A
Authority: CN
Inventors: 哈希姆·扎尔·霍西尼; 塔米姆·费克; 骆智峯
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-07-19
Filing date: 2017-07-19
Publication date: 2022-05-10
Anticipated expiration: 2037-07-19
Also published as: CN111295843A; WO2019015751A1

Abstract

A pipelined analog-to-digital converter in which at least one stage includes three or more sampling channels. The at least one stage includes an input sampling circuit, a quantization circuit, and an amplification circuit. The input sampling circuit includes three or more channels, one of which samples the received analog signal in each cycle. The quantization circuit receives the samples from the input sampling circuit one cycle after the samples are generated, such that the quantization circuit receives samples from one of the three or more channels in each cycle and quantizes each received sample to one or more bits of the digital word for that sample. The amplification circuit receives the samples from the input sampling circuit two cycles after the generation of the samples and the bits corresponding to the samples in one cycle after the generation of the samples, such that the amplification circuit receives samples from one of the three or more channels and the corresponding bits (or an analog signal representing the bits) from the quantization circuit in each cycle and generates an amplified residual signal from the samples.

Description

Pipeline analog-to-digital converter with at least three sampling channels

Technical Field

The application relates to a pipeline analog-to-digital converter.

Background

An analog-to-digital converter (ADC) samples an input analog signal at uniform time intervals (i.e., sampling periods) and assigns a digital value including one or more bits to each sample, thereby converting the input analog signal into a digital signal. The ADC may be implemented using a variety of different architectures such as, but not limited to, flash (also may be referred to as direct conversion or parallel), successive approximation, ramp comparison, Wilkinson, integration, Delta coding (also may be referred to as inverse ramp), Sigma-Delta, time interleaving, and pipelining.

The pipelined ADC divides the conversion of each sample into a plurality of low resolution cascaded stages, where each stage generates one or more bits of a digital value assigned to the sample. For example, an ADC for generating a 12-bit value for each sample (which may be referred to as a 12-bit ADC) may be divided into four 3-bit stages. Each stage (except the last stage) receives an analog signal (input analog signal or residual from the previous stage), samples and holds the received signal, and quantizes the samples to a predetermined number of bits (e.g., 3 bits). The quantized values are then converted to analog signals and subtracted from the samples to generate residual signals. The residual signal is amplified and then transferred to the next stage. The last stage simply samples and quantizes the received residual signal.

Each stage may operate simultaneously on a different sample of the input analog signal. The first stage runs on the latest sample and the subsequent stage runs on the residual of the previous sample.

The parallel operation of these stages makes pipelined ADCs suitable for applications requiring high-speed analog-to-digital conversion, such as multiple GS/s applications. Other suitable ADCs for high speed applications are time interleaved ADCs, which are subject to time interleaved spur signals. Pipelined ADCs have higher performance in terms of spurious signals than time interleaved ADCs, while traditional pipelined ADCs for high speed conversion have high power consumption.

The embodiments described below are provided by way of example only and are not limited to implementations that address any or all disadvantages of known pipeline analog-to-digital converters.

Disclosure of Invention

It is an object of the present invention to provide an improved pipelined analog-to-digital converter.

The above and other objects are achieved by the features of the independent claims. Further implementations are apparent from the dependent claims, the detailed description and the accompanying drawings.

According to a first aspect, there is provided a pipelined analog-to-digital converter comprising: a plurality of stages for generating one or more bits of an output digital signal from an input analog signal, at least one of the stages comprising: an input sampling circuit comprising three or more channels, wherein one of the three or more channels is used to sample the input analog signal within a cycle; a quantization circuit in the loop to receive samples from another one of the three or more channels and quantize the received samples into one or more bits of the output digital signal; an amplification circuit in the loop to receive a sample and the one or more quantization bits corresponding to the sample from a further channel of the three or more channels and to generate an amplified residual signal from the received sample and the one or more quantization bits. Using at least three channels allows each of the input sampling circuit, the quantization circuit, and the amplification circuit to operate simultaneously on different samples. This may reduce the time constraints on these circuits, allowing one or more of the input sampling circuit, the quantisation circuit and the amplification circuit to use lower power components, thereby reducing the power consumption of the pipelined analogue to digital converter at a given sampling rate.

Advantageously, such a pipeline analog-to-digital converter consumes less power at a given sampling frequency than a conventional pipeline analog-to-digital converter; and/or an increased sampling rate at a given power consumption compared to conventional pipelined analog-to-digital converters.

In further implementations of the first aspect, the quantization circuit is to quantize the received samples for a maximum time period, the maximum time being a sampling period of the pipeline analog-to-digital converter. Providing a full cycle for the quantization circuit to quantize the received samples allows the quantization circuit to be implemented using lower power devices (e.g., lower power flash ADCs), thereby reducing the power consumption of the pipelined analog-to-digital converter.

In a further implementation form of the first aspect, the amplification circuit is configured to quantize the received samples within a maximum time period, which is a sampling period of the pipeline analog-to-digital converter. Providing the amplification circuit with a full cycle to generate the amplified residual signal allows the amplification circuit to be implemented using lower power devices (e.g., lower power amplifiers), thereby reducing power consumption of the pipelined analog-to-digital converter.

In a further implementation form of the first aspect, each of the three or more channels is configured to sample the input analog signal for a longest time period, which is a sampling period of the pipelined analog-to-digital converter. Providing a complete cycle for each channel to generate/obtain samples from the input analog signal may alleviate the requirements on the circuitry driving the pipeline analog-to-digital converter. In particular, this allows the circuitry driving the pipeline analog-to-digital converter to be implemented using lower power devices, thereby reducing the power consumption of a system incorporating the pipeline analog-to-digital converter.

In a further implementation of the first aspect, at least one of the three or more channels of the input sampling circuit includes a first sample-and-hold circuit and a second sample-and-hold circuit, the first sample-and-hold circuit being configured to sample the input analog signal in a first cycle and output the sample to the quantization circuit in a second cycle after the first cycle, and the second sample-and-hold circuit being configured to sample the input analog signal in the first cycle and output the sample to the amplification circuit in a third cycle after the second cycle. This allows the samples to be provided to the subsequent two circuits (e.g., the quantization circuit and the amplification circuit) in different cycles.

In further implementations of the first aspect, the first sample-and-hold circuit includes a first switching network enabled in the first cycle such that the input analog signal is sampled to the capacitor network in the first cycle, a capacitor network, and a second switching network enabled in the second cycle such that the sample is provided to the quantization circuit in the second cycle. Implementing the first sample-and-hold circuit using switches and capacitors allows the first sample-and-hold circuit to be implemented without active devices, thereby reducing the complexity of the first sample-and-hold circuit.

In a further implementation of the first aspect, the second sample-and-hold circuit includes a first switch network, a capacitor network, and a second switch network; the first switch is enabled in the first cycle such that the input analog signal is sampled to the capacitor network in the first cycle; the second switching network is enabled in the third cycle such that the sample is provided to the amplification circuit in the third cycle. Implementing the second sample-and-hold circuit using switches and capacitors allows the second sample-and-hold circuit to be implemented without active devices, thereby reducing the complexity of the second sample-and-hold circuit.

In a further implementation form of the first aspect, the quantization circuit comprises a single sub-adc shared by the three or more channels. Sharing one sub-adc between the channels reduces the number of devices in the pipeline adc (since there is no sub-adc per channel), thereby reducing the complexity of the pipeline adc.

In a further implementation of the first aspect, the single-sub analog-to-digital converter is a flash analog-to-digital converter. Flash ADCs provide a fast way to convert analog signals to digital signals.

In further implementations of the first aspect, the amplification circuit is to: converting the one or more bits to a second analog signal; subtracting the second analog signal from the received samples to generate a residual signal; amplifying the residual signal to generate the amplified residual signal.

In a further implementation form of the first aspect, the amplification circuit comprises an amplifier for amplifying the residual signal to generate the amplified residual signal, the amplification circuit further being configured to reset the amplifier before the amplifier amplifies the residual signal to generate the amplified residual signal. Continuously operating (e.g., not resetting) amplifiers may cause memory effects. Thus, resetting the amplifier every cycle can at least reduce (and in some cases eliminate) these memory effects.

In a further implementation form of the first aspect, the amplification circuit comprises a multiplying digital-to-analog converter circuit.

In further implementations of the first aspect, in a first reference cycle, a first channel of the three or more channels samples the input analog signal, the quantization circuit quantizes the samples from a third channel of the three channels, and the amplification circuit generates an amplified residual signal based on samples from a second channel of the three or more channels; in a second reference cycle immediately following the first reference cycle, the second channel samples the input analog signal, the quantization circuit quantizes the samples from the first channel, and the amplification circuit generates an amplified residual signal from the samples from the third channel; in a third reference cycle immediately following the second reference cycle, the third channel samples the input analog signal, the quantization circuit quantizes the samples from the second channel, and the amplification circuit generates an amplified residual signal from the samples from the first channel.

In a further implementation of the first aspect, each of the three or more channels is to sample the input analog signal at a rate of one third of a sampling rate of the pipeline analog-to-digital converter.

In a further implementation of the first aspect, the plurality of stages includes a second stage subsequent to the at least one stage, the second stage including one of: (i) a flash memory analog-to-digital converter; (ii) a successive approximation analog-to-digital converter; and (iii) a second input sampling circuit comprising three or more channels, one of the three or more channels of the second input sampling circuit being used to sample the amplified residual signal in the loop; a second quantization circuit in the loop to receive samples from another one of the three or more channels of the second input sampling circuit and quantize the received samples into one or more bits of the output digital signal; a second amplification circuit in the loop to receive a sample and the one or more quantization bits corresponding to the sample from a further one of the three or more channels of the second input sampling circuit and to generate a second amplified residual signal from the received sample and the one or more quantization bits.

In a further implementation of the first aspect, the three or more channels include only three channels.

According to a second aspect, there is provided a method of generating one or more bits of an output digital signal representative of an input analogue signal, the method comprising, in one cycle: sampling the input analog signal for one of the three or more channels, the one of the three or more channels being selected in a cyclic manner; a quantization circuit to quantize samples received from another of the three or more channels into one or more bits of the output digital signal; an amplification circuit generates an amplified residual signal from a sample received through yet another one of the three or more channels and the one or more bits corresponding to the sample.

Drawings

The invention will now be described by way of example with reference to the accompanying drawings. In the drawings:

FIG. 1 is a block diagram of a conventional pipelined ADC;

FIG. 2 is a block diagram of an example pipelined ADC with three sampling channels;

FIG. 3 is a timing diagram illustrating an example operation of the pipelined ADC of FIG. 2;

FIG. 4 is a block diagram of an example implementation of the input sampling circuit of FIG. 3;

FIG. 5 is a block diagram of an example implementation of the sample-and-hold circuit of FIG. 4;

6A-6B are timing diagrams illustrating example control signals for the switching network of FIG. 5;

FIG. 7 is a circuit diagram of an example implementation of the sample-and-hold circuit of FIG. 5;

FIG. 8 is a flow diagram of an example method of generating a predetermined number of bits of a digital value from an analog signal.

Detailed Description

The following description is presented by way of example to enable any person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art. The embodiments are described by way of example only.

As described above, the ADC functions to convert an input analog signal into a digital signal by sampling the input analog signal at uniform time intervals (sampling periods) and assigning a digital value including one or more bits to each sample. The term "cycle" as used herein is used to refer to a sampling cycle (i.e., sampling period or sampling interval) of the ADC, which is defined by the sampling frequency (or sampling rate) of the ADC. As known to those skilled in the art, the cyclic sampling frequency (or sampling rate) is the average number of samples taken in a second.

Described herein are pipelined ADCs that consume less power and sample at the same rate as conventional pipelined ADCs. At least three sampling channels may be implemented by at least one stage of the pipelined ADC to reduce power consumption. Specifically, the at least one stage includes an input sampling circuit, a quantization circuit, and an amplification circuit. The input sampling circuit includes three channels, one of which samples the received analog signal in each cycle. The quantization circuit receives the samples from the input sampling circuit one cycle after the samples are generated, such that the quantization circuit receives samples from one of the three or more channels in each cycle and quantizes each received sample to one or more bits of the digital word for that sample. The amplification circuit receives the samples from the input sampling circuit two cycles after the sample generation and receives the bits corresponding to the samples (or an analog signal representing the values of the bits) in one cycle after the sample generation, such that the amplification circuit receives samples from one of the three or more channels and receives the corresponding bits (or an analog signal representing the bits) from the quantization circuit in each cycle and generates an amplified residual signal from the samples.

This configuration allows each sub-circuit (the input sampling circuit, the quantization circuit, the amplification circuit) to have a full loop to perform its function, i.e. the input sampling circuit has a full loop to sample the analog signal, the quantization circuit has a full loop to quantize the received samples, and the amplification circuit has a full loop to generate the amplified residual signal. This may reduce the time constraints of these circuits, at least one of which performs less than a full cycle, compared to a conventional pipelined ADC. By shortening the time constraints of these circuits, these circuits can be implemented using lower power devices, thereby reducing the overall power consumption of the pipelined ADC.

To more clearly illustrate the improved pipelined ADC and reduce power consumption, please first refer to fig. 1, which shows an example of a conventional pipelined ADC 100. The conventional pipeline ADC 100 converts an input analog signal into a digital signal. Specifically, the conventional pipelined ADC 100 samples an input analog signal at a predetermined sampling rate and generates an X-bit digital value for each sample, where X is the resolution of the conventional pipelined ADC 100. The conventional pipelined ADC 100 includes cascaded

stages

102, 104 and a time alignment module 106. Each

stage

102, 104 generates one or more bits of the digital value for sampling. For example, in FIG. 1, the first stage generates N1 bits, the second stage generates N2 bits, the third stage generates N3 bits, and so on. Each

stage

102, 104 may generate the same number of bits (e.g., N1 ≠ N2 ═ N3 ═ N4 ≠ N5), or two or more stages may generate a different number of bits (e.g., N1 ≠ N2). The first stage generates the most significant bits of the digital value and the final stage 104 generates the least significant bits of the digital value.

In addition to the final stage 104, each stage 102 includes a first sample-and-hold circuit 108, a second sample-and-hold circuit 110, a sub-analog-to-digital converter (sub-ADC) 112, a digital-to-analog converter (DAC) 114, a subtraction circuit 116, and an amplifier 118. The sample and hold

circuits

108, 110 are used to sample the voltage of the received analog signal and hold its value in a first stage (e.g., a first portion) of the cycle. In a second stage (e.g., a second portion) of the cycle, the sub-ADC 112 quantizes the sample from the first sample-and-hold circuit 108 into one or more bits (e.g., N1, N2, N3, N4 bits) and outputs the one or more bits. The DAC 114 then converts one or more bits of the sub-ADC output to an analog signal, the subtraction circuit 116 subtracts the analog signal of the DAC 114 from the samples of the second sample and hold circuit 110 to generate a residual signal, and the amplifier 118 applies a gain (G) to the residual signal to generate an amplified residual signal. The amplified residual signal is then provided to the

next stage

102, 104. The residuals then continue to subsequent stages (e.g., stages 2, 3, and 4) until the last or final stage 104 is reached.

The final stage 104 samples only the amplified residual signal received from the previous stage (e.g., stage 4 in the example of fig. 1) and quantizes the samples to a predetermined bit number. The final stage 104 is typically implemented using a flash ADC.

Since the bits of each

stage

102 and 104 are determined in different cycles, the time alignment module 106 aligns the bits corresponding to a particular sample (e.g., via a shift register) to generate a final digital value for that sample. The time alignment module 106 may also be used to perform digital error correction on the final digital values before outputting the final values.

After one stage has processed the first sample, another sample can be processed in the next cycle. This enables the stages to run continuously and simultaneously on different samples, making the pipelined ADC suitable for high-throughput or high-speed applications.

Each non-final stage 102 may be described as performing three main functions or operations: sampling, quantization (or digitization), and amplification (i.e., generation of an amplified residual signal). Since each non-final stage 102 can only process one sample at a time, the sampling, quantization and amplification functions are all performed in the same cycle. This means that each of these three functions is completed/executed in less than a full loop (e.g., the sampling can occupy 1/3 of the loop, the quantization can occupy 1/3 of the loop, and the amplification can occupy 1/3 of the loop). If such a conventional pipelined ADC is used for high-speed applications, e.g. multi-Gigahertz (GHz) applications, the high-speed sub-ADCs are required to provide sufficient time to generate an amplified residual signal in the same cycle as the quantization. Such high-speed sub-ADCs typically consume more power than low-speed sub-ADCs, thereby increasing the overall power consumption of the pipelined ADC. Even with high-speed sub-ADCs, implementing a high-speed pipelined ADC typically requires a high-speed amplifier. High speed amplifiers typically consume more power than low speed amplifiers, which increases the overall power consumption of the pipelined ADC.

One proposed solution to this problem is to reduce the time required to sample the received analog signal. By reducing the time required to sample the received analog signal, a larger fixed period (set by the fixed sampling clock) is provided to perform the quantization and amplification functions, thereby using lower power sub-ADCs and/or amplifiers. However, this increases the power consumption of the system or components that drive the ADC (i.e., the ADC driver), thereby increasing the power consumption of the larger system of pipelined ADCs. For example, if the pipelined ADC forms part of a Radio Frequency (RF) receiver, reducing the time that the pipelined ADC samples a received analog signal may increase the overall power consumption of the RF receiver, even though this may reduce the power consumption of the pipelined ADC itself.

Another proposed solution to this problem is to implement one or more stages using a ping-pong configuration (which may also be referred to as a double sampling configuration). A stage with a ping-pong configuration may process or operate on two samples simultaneously. In particular, in a ping-pong configuration, a stage may generate/obtain the second samples without losing the first samples (e.g., it may have two sampling circuits, operating in an interleaved or alternating manner). This provides two cycles for processing each sample. In other words, this provides the stage with two cycles to perform the three key functions of each sample (sampling, quantization and amplification).

Typically, the sampling is performed during a first cycle, the amplifying is performed during a second cycle, and the quantizing is performed during the first cycle or the second cycle. For example, in some ping-pong configurations of a first cycle, the received analog signal is sampled into a first sampling circuit, and in a second cycle, the samples from the first sampling circuit are quantized and amplified while the received analog signal is sampled into a second sampling circuit. Although the ping-pong configuration may provide some benefits because more time is provided to perform three functions, it still has a number of disadvantages. For example, if the quantization is performed in the same period as the sampling, then in order to significantly reduce the power of the sub-ADCs (in order to use lower power sub-ADCs), a large part or portion of the first period must be dedicated to the quantization, leaving only a small portion of the cycles for the sampling. This may increase the power consumption of the ADC driver, thereby increasing the power consumption of the larger system to which the pipelined ADC belongs. Conversely, if the quantization is performed in the same cycle as the amplification, both functions have to be performed in one cycle, which usually requires a high-speed (and high-power consumption) quantization circuit or a high-speed (and high-power consumption) amplification circuit. Therefore, the speed of a pipelined ADC with one or more ping-pong stages is limited to achieve reasonable power consumption.

Thus, described herein is a pipelined ADC having at least three sampling channels. In particular, the pipelined ADC described herein includes an input sampling circuit that includes at least three sampling channels that sample (and hold) a received analog signal in a cyclic manner (or in an alternating manner). Samples from three or more channels are then provided to a quantization circuit; the amplification circuits are then performed in the order in which they were generated (sampled). The quantization circuit quantizes the received samples and the amplification circuit generates an amplified residual signal. By being able to accommodate at least three different samples at a time, each sub-circuit (the input sampling circuit, the quantization circuit and the amplification circuit) can run on a different sample, each cycle allowing each sub-circuit (the input sampling circuit, the quantization circuit and the amplification circuit) to have a complete cycle to perform its function.

An example in which the input sampling circuit contains three sampling channels will now be described, but in other examples the input sampling circuit may contain more sampling channels. In these examples, rather than implementing a three cycle repeat pattern, the pipeline analog-to-digital converter may implement an N cycle repeat pattern, where N is the number of channels.

Referring now to fig. 2, fig. 2 illustrates an example of reduced power consumption of a pipelined ADC 200 over the same sampling period (or sampling frequency) as compared to the conventional pipelined ADC 100 of fig. 1. The pipelined ADC 200 of fig. 2 converts the input analog signal to a digital signal by sampling the input analog signal at a predetermined sampling rate and generating an X-bit digital value for each sample (where X is the resolution of the pipelined ADC 200).

The pipelined ADC 200 of fig. 2, like the conventional pipelined ADC 100 of fig. 1, includes cascaded

stages

202, 203, 204 (one or more

non-final stages

202, 203 and a final stage 204) and a time alignment module 206. Each

stage

202, 203, 204 is for generating one or more bits of the digital value for each sample. For example, in FIG. 2, the first stage generates N1 bits, the second stage generates N2 bits, the third stage generates N3 bits, and so on. Each

stage

202, 203, 204 may generate the same number of bits (e.g., N1 ≠ N2 ═ N3 ═ N4 ═ N5), or two or more stages may generate a different number of bits (e.g., N1 ≠ N2). Although five

stages

202, 203, and 204 are shown in fig. 2, it will be apparent to those skilled in the art that in other examples, the pipelined ADC 200 may have only two pipeline stages (e.g., a non-final stage and a final stage) or any number greater than two stages.

The time alignment module 206, similar to the time alignment module of fig. 1, time aligns the bits corresponding to a particular sample (e.g., via a shift register) to generate the last digital value for that sample. The time alignment module 206 may also be used to perform digital error correction on the final digital values before outputting the final values.

The

non-final stages

202, 203 are stages that generate residual signals for subsequent stages. At least one of the

non-final stages

202, 203 is a modified non-final stage 202 that includes an input sampling circuit 208, a quantization circuit 210, and an amplification circuit 212. The input sampling circuit 208 includes three

channels

214, 216, 218, wherein the channels operate in a cyclic or alternating manner such that one of the

channels

214, 216, 218 samples the received analog signal during each cycle. For example, in a first cycle, the first channel 214 may sample the received analog signal, in a second cycle, the second channel 216 may sample the received analog signal, in a third cycle, the third channel 218 may sample the received analog signal, in a fourth cycle, the first channel 214 may sample the received analog signal, and so on. In this manner, each

channel

214, 216, and 218 samples the received analog signal at one-third of the sampling rate of the pipelined ADC 200.

Wherein, as shown in fig. 2, the modified non-final stage 202 is the first stage, and the received analog signal is the original input analog signal. However, if the modified non-final stage 202 is not the first stage, then the received analog signal is an amplified residual signal received from a previous stage. As described in more detail below, in some examples, each channel may include multiple sample and hold circuits. However, it will be apparent to those skilled in the art that this is merely an example and that the input sampling circuit 208 and its

channels

214, 216 and 218 may be implemented in any suitable manner.

The quantization circuit 210 is configured to receive a sample from one of the three

channels

214, 216, and 218 of the input sampling circuit 208 in each cycle and quantize the received sample into one or more bits. As known to those skilled in the art, quantization is a process of approximately converting a real number to a finite set of discrete values, which are represented by a predetermined number of bits. The number of bits used to represent the value determines the number of discrete values. For example, if eight bits are used to represent a value, there will be 256 different discrete values.

In some examples, such as the example shown in fig. 2, the quantization circuit 210 may include a sub-analog-to-digital converter (sub-ADC) 220 that quantizes the received samples into a digital value that includes one or more bits (e.g., N bits). In some examples, the sub-ADC is a flash ADC. As known to those skilled in the art, a flash ADC (which may also be referred to as a direct conversion ADC or a parallel ADC) includes a series of comparators, each of which compares an input signal to a unique reference voltage. The comparator output is connected to the input of the priority encoder and then generates a binary output. However, it will be clear to those skilled in the art that this is only an example and that the quantization circuit 210 may be implemented in any suitable way.

In some examples, the quantization circuit 210 is to receive samples from the

channels

214, 216, and 218 of the input sampling circuit 208 in cycles after the respective channels of the input sampling circuit 208 generate samples. For example, if in a first cycle a first channel 214 of the input sampling circuitry 208 samples a received analog signal, in a second cycle the quantization circuitry 210 may receive samples from the first channel 214 and quantize the samples while a second channel 216 of the input sampling circuitry 208 samples the received analog signal, and then in a third cycle the quantization circuitry 210 may receive samples from the second channel and quantize the samples while a third channel 218 of the input sampling circuitry 208 samples the received analog signal.

The amplification circuit 212 is configured to receive a sample from one of the three

channels

214, 216, 218 of the input sampling circuit 208 and one or more quantized bits (or analog signals representing the values of these bits) corresponding to the sample from the quantization circuit 210 each cycle and generate an amplified residual signal. In particular, the amplification circuit 212 is configured to convert the one or more quantized bits into a second analog signal representative of the values of the bits (if the analog signal representative of the values of the bits was not originally received), subtract the second analog signal from the received samples to generate a residual signal, and amplify the residual signal to generate an amplified residual signal. The amplified residual signal is then provided to the

next stage

203, 204.

In some examples, such as the example shown in fig. 2, the amplification circuit 212 may be implemented as a multiplying digital to analog converter (MDAC) circuit that generates a sampled amplified residual signal received from one of the

channels

214, 216, 218. As known to those skilled in the art, MDAC circuits perform digital-to-analog conversion and multiplication. An exemplary MDAC circuit is shown in fig. 2 and includes a digital to analog converter (DAC) 222, a subtraction circuit 224, and an amplifier 226. The digital-to-analog converter 222 receives one or more bits from the quantization circuit 210, the one or more bits representing sampled bits of a particular channel, and converts the one or more bits to a second analog signal. The subtraction circuit 224 receives the second analog signal from the digital-to-analog converter 222 and a sample from one of the

channels

214, 216, 218 and subtracts the second analog signal from the sample to generate a residual signal. The amplifier 226 applies a gain to the residual signal generated by the subtraction circuit 224 to generate an amplified residual signal. However, it will be apparent to those skilled in the art that this is merely an example, and that the amplification circuit 212 may be implemented in any suitable manner. For example, although fig. 2 shows a separate DAC 222 component, in other examples, the DAC 222 functionality may be implemented by or incorporated into another component.

Since a full cycle is provided for the amplification circuit 212 to generate the amplified residual signal, in some cases the amplification circuit 212 may be used to reset the amplifier 226 in each cycle before performing the amplification. In particular, if the amplifier 226 is used for continuous operation (e.g., turned on at two stages of the cycle), this may result in a memory effect because the amplifier 226 is not reset. In a conventional pipelined ADC, the speed of the circuit is reduced if a reset is performed, or compensated for using a higher speed amplifier (consuming more power than a lower speed amplifier), since less time is allotted to perform the amplification function. Since a full cycle is provided to the amplification circuit 212 to generate the amplified residual signal, a reset may be inserted without having to slow down the amplification circuit 212 or significantly increase the power consumption of the amplification circuit 212.

In some examples, the amplification circuit 212 is to receive samples from the

channels

214, 216, 218 of the input sampling circuit 208 in two cycles after the samples are generated by the respective channels of the input sampling circuit 208, and to receive one or more bits (or an analog signal representing values of one or more bits) corresponding to the samples in a cycle period after the one or more bits are generated. For example, in a first cycle, the first channel 214 of the input sampling circuit 208 may sample the received analog signal; then, in a second cycle, the quantization circuit 210 may receive samples from the first channel 214 and quantize the samples, while the second channel 216 of the input sampling circuit 208 samples the received analog signal; then in a third cycle, the amplification circuit 212 receives samples from the first channel 214 and one or more bits from the quantization circuit 210 corresponding to the samples from the first channel 214, while the quantization circuit 210 receives samples from the second channel 216 and quantizes the samples, and a third channel 218 of the input sampling circuit 208 samples the received analog signal.

Using at least three sampling channels in the input sampling circuit 208 allows each of the input sampling circuit 208, quantization circuit 210, and amplification circuit 212 to simultaneously generate or perform operations on samples of different channels of the three or

more channels

214, 216, 218 in the same cycle. For example, as shown in fig. 3, in a first reference period 302, a first channel 214 of the three channels may sample the input analog signal, the quantization circuit 210 may quantize samples from the third channel 218 of the three channels, and the amplification circuit 212 may generate an amplified residual signal based on samples from a second channel 216 of the three channels. Then, in a second reference cycle 304, which follows the first reference cycle 302, the second channel 216 samples the received analog signal, the quantization circuit 210 may quantize the samples from the first channel 214, and the amplification circuit 212 may generate an amplified residual signal from the samples from the third channel 218. Then, in a third reference cycle 306, which may be immediately subsequent to the second reference cycle, the third channel 218 may sample the received analog signal, the quantization circuit 210 may quantize the samples from the second channel 216, and the amplification circuit 212 may generate an amplified residual signal from the samples from the first channel 214. In other words, each channel successive rotation is associated with the three

circuits

208, 210, 212, i.e. each channel rotation is associated with the input sampling circuit 208, the quantization circuit 210 and the amplification circuit 212.

This allows each of these circuits (the input sampling circuit 208, the quantization circuit 210 and the amplification circuit 212) to be assigned a maximum cycle equal to a full cycle to perform its function. In other words, each circuit has a full cycle to perform its function. Specifically, the input sampling circuit 208 has a full cycle for sampling the received analog signal, the quantization circuit 210 has a full cycle for quantizing the received sample, and the amplification circuit 212 has a full cycle for generating an amplified residual signal for the received sample.

Providing these

circuits

208, 210, 212 with a full cycle to perform their functions may relax the time constraints on these circuits (i.e., each of these circuits has more time to perform their functions) compared to the conventional pipelined ADC. Relaxing this time constraint allows these circuits to be implemented using lower power devices, thereby reducing the overall power consumption of the pipelined ADC. In particular, the quantization stage is implemented by a sub-ADC, which allows the use of a lower power sub-ADC, while allowing the use of a low power amplifier in the amplification circuit. Furthermore, component requirements for providing the input to at least one stage (e.g., a driver of a previous stage or pipelined ADC 200) are reduced due to relaxed time constraints on the input sampling circuit.

A pipelined ADC having a single modified non-final stage may improve the power consumption of the pipelined ADC compared to the conventional pipelined ADC, but the more non-final stages that are implemented as modified non-final stages, the more significant the power consumption reduction of the pipelined ADC.

The modified non-final stage 202 may be the first stage shown in fig. 2 or may be an intermediate stage (i.e., a stage that receives a residual signal from an earlier stage and provides a residual signal to a later stage). One or more of the

further stages

203, 204 of the ADC may be the same as or different from the modified non-final stage. For example, in some cases, the modified non-final stage may be followed by another modified non-final stage. In particular, the modified non-final stage may be followed by a second modified non-final stage comprising a second input sampling circuit comprising three or more channels, wherein one of the three or more channels of the second input sampling circuit is used to sample the amplified residual signal generated by the last modified non-final stage; a second quantization circuit in the loop to receive samples from one of the three or more channels of the second input sampling circuit and quantize the received samples into one or more bits; and a second amplification circuit for receiving a sample and one or more quantization bits (or analog signals representing values of the bits) corresponding to the sample from one of the three or more channels of the second input sampling circuit in the period, and generating a second amplified residual signal from the received sample and the one or more quantization bits (or analog signals representing values of the bits). However, in other cases, the at least one modified non-final stage may be followed by

stages

203, 204, which are implemented using any known ADC stage configuration. For example, the modified non-final stage 202 may be followed by a stage implemented as a flash analog-to-digital converter (which may be a final stage), a successive approximation analog-to-digital converter, or the like.

Referring now to fig. 4, fig. 4 illustrates an example implementation of the modified input sampling circuit 208 of the non-final stage 202 of fig. 2. In this example, the input sampling circuit 208 includes three

channels

214, 216, 218, where each channel includes a first sample and hold

circuit

402, 404, 406 and a second sample and hold

circuit

408, 410, 412, and specifically, the first channel 214 includes a first sample and hold circuit 402 and a second sample and hold circuit 408, the second channel 216 includes a first sample and hold circuit 404 and a second sample and hold circuit 410, and the third channel 218 includes a first sample and hold circuit 406 and a second sample and hold circuit 412.

The first sample and hold

circuit

402, 404, 406 for each channel is used to sample the received analog signal every nth cycle (where N is the number of channels) and hold the sample at least until the next cycle. In the cycle after the sampling (or generation) is completed, the samples are provided by the first sample and hold

circuits

402, 404, 406 to the quantization circuit 210 for quantization. The first sample and hold

circuits

402, 404, 406 are configured to operate in an alternating manner such that only one of the first sample and hold

circuits

402, 404, 406 samples the received analog signal during any cycle.

For example, in the case of three channels, in a first cycle, the first sample and hold circuit 402 of the first channel 214 may sample the received analog signal; in a second cycle, the first sample and hold circuit 402 of the first channel 214 may provide its samples to the quantization circuit 210, the first sample and hold circuit 404 of the second channel 216 sampling the received analog signal; in a third cycle, the first sample and hold circuit 404 of the second channel 216 provides its samples to the quantization circuit 210, and the first sample and hold circuit 406 of the third channel 218 samples the received analog signal; in a fourth cycle, the first sample and hold circuit 406 of the third channel 218 provides its samples to the quantization circuit 210, and the first sample and hold circuit 404 of the first channel 214 samples the received analog signal; and so on. Thus, the quantization circuit 210 receives samples from one of the three or more channels in each cycle. This is summarized in table 1.

TABLE 1

The second sample and hold

circuit

408, 410, 412 of each

channel

214, 216, 218 is configured to sample the received analog signal in the same cycle as the first sample and hold

circuit

402, 404, 406 of the

same channel

214, 216, 218 and hold the sample at least until a second cycle after sampling the received signal. In a second cycle after sampling the received analog signal, the samples are provided by the second sample and hold

circuit

408, 410, 412 to the amplification circuit 212, generating an amplified residual signal in the amplification circuit 212. Since the second sample and hold

circuits

408, 410, 412 are used to sample the received analog signal in the same cycle as the first sample and hold

circuits

402, 404, 406 of the

same channel

214, 216, 218, the second sample and hold

circuits

408, 410, 412 are also used to operate in an alternating manner such that only one sample and hold

circuit

408, 410, 412 of the second sample and hold

circuits

408, 410, 412 samples the received analog signal in any cycle.

For example, in the case of three channels, in a first cycle, the second sample and hold circuit 408 of the first channel 214 may sample the received analog signal; in a second cycle, the second sample and hold circuit 410 of the second channel 216 samples the received analog signal; in a third cycle, the second sample and hold circuit 408 of the first channel 214 provides its samples to the amplification circuit 212, and the second sample and hold circuit 412 of the third channel 218 samples the received analog signal; in a fourth cycle, the second sample and hold circuit 410 of the second channel 216 provides its samples to the amplification circuit 212, and the second sample and hold circuit 408 of the first channel 214 samples the received analog signal; in a fifth cycle, the second sample and hold circuit 412 of the third channel 218 provides its samples to the amplification circuit 212, and the second sample and hold circuit 410 of the second channel 216 samples the received analog signal; and so on. Thus, the amplification circuit 212 receives samples from one of the three or more channels in each cycle. This is summarized in table 2.

TABLE 2

Fig. 4 shows an example implementation of the input sampling circuit, the quantization circuit and the amplification circuit. These circuits are independent of each other and thus the example implementation of one type of circuit shown in fig. 4 may be used not only with the example implementations of other types of circuits shown in fig. 4, but also with other suitable implementations of these circuits. For example, the example implementation of the input sampling circuit described with respect to fig. 4 may be used with a different implementation of the amplification circuit shown and described with respect to fig. 4.

Referring now to fig. 5, fig. 5 illustrates an example implementation of the sample and hold

circuits

402, 404, 406, 408, 410, 412 of fig. 4. In fig. 5, each sample-and-

hold circuit

402, 404, 406, 408, 410, 412 includes a first switching network, a capacitor network, and a second switching network. Specifically, in the example of FIG. 5, the first sample-and-hold circuit 402 of the first channel 214 includes a first switching network SN1, a capacitance network CN1, and a second switching network SN 2; the first sample-and-hold circuit 404 of the second channel 216 comprises a first switching network SN3, a capacitor network CN2, and a second switching network SN 4; the first sample-and-hold circuit 406 of the third channel 218 includes a first switching network SN5, a capacitor network CN3, and a second switching network SN 6. Similarly, the second sample-and-hold circuit 408 of the first channel 214 includes a first switching network SN7, a capacitor network CN4, and a second switching network SN 8; the second sample and hold circuit 410 of the second channel 216 comprises a first switch network Sn9, a capacitor network CN5, and a second switch network Sn 10; the second sample-and-hold circuit 412 of the third channel 218 includes a first switching network SN11, a capacitor network CN6, and a second switching network SN 12. Each switch network includes one or more switches and each capacitor network includes one or more capacitors. An example implementation of the switching network and the capacitor network will be described below with reference to fig. 7.

The one or more capacitors of the respective capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 are charged by an input signal when the first switch network SN1, SN3, SN5, SN7, SN9, or SN11 of a sample and hold circuit is enabled or activated, and the one or more capacitors of the respective capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 are discharged to provide an output signal when the second switch network SN2, SN4, SN6, SN8, SN10, SN12 is enabled or activated. Since each sample and hold circuit receives the analog signal as an input, when the one or more capacitors of the capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 are charged, the one or more capacitors of the capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 are charged to a value (e.g., voltage) corresponding to the received analog signal at that time. Thus, when charged, the one or more capacitors of capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 hold a sample of the received analog signal. When the one or more capacitors of capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 are discharged, the capacitor networks output acquired values (e.g., voltages) of the received analog signals. In other words, upon discharge, one or more capacitors of capacitor networks CN1, CN2, CN3, CN4, CN5, CN6 output the sampled value.

As described above, the

channels

214, 216, 218 are configured to operate in an alternating manner such that only one channel samples the received analog signal in one cycle. If there are three channels, each channel samples the received analog signal every three cycles. To enable this operation, the first switching networks SN1, SN7 of the first and second sample-and-

hold circuits

402, 408 of the first channel 214 may be enabled in a first cycle. The first switching networks SN3, SN9 of the first and second sample-and-

hold circuits

404, 410 of the second channel 216 may be enabled in a second cycle, and the first switching networks SN5, SN11 of the first and second sample-and-

hold circuits

406, 412 of the third channel 218 may be enabled in a third cycle; and so on.

As described above, the output of the first sample and hold

circuit

402, 404, 406 of each

channel

214, 216, 218 is coupled to the input of the quantization circuit 210 (e.g., sub-ADC 220). Thus, when the one or more capacitors of the capacitor networks CN1, CN2, CN3 of the first sample-and-hold circuit are discharged (when the second switch networks SN2, SN4, SN6 are enabled), the sample is output to the quantization circuit 210. As described above, in some examples, the first sample and hold

circuit

402, 404, 406 is to provide the captured samples to the quantization circuit 210 in a cycle immediately after a cycle in which the samples are captured (e.g., in a cycle immediately after a cycle in which the capacitor is charged). To enable this operation, said second switch network SN2, SN4, SN6 of each first sample-and-

hold circuit

402, 404, 406 may be enabled in a cycle immediately following the capacitor charging/recharging cycle of the respective capacitor network CN1, CN2, CN 3.

As described above, the second sample and hold

circuit

408, 410, 412 of each

channel

214, 216, 218 is coupled to an input of the amplification circuit 212 (e.g., MDAC circuit). Thus, when the one or more capacitors of the capacitor networks CN4, CN5, CN6 of the second sample-and-

hold circuits

408, 410, 412 are discharged (when the second switch networks SN8, SN10, SN12 are enabled), the sample is output to the amplification circuit 212. As described above, in some examples, the second sample and hold

circuits

408, 410, 412 are to provide the captured samples to the amplification circuit 212 in a cycle that is two cycles after the cycle in which the samples are captured (e.g., two cycles after charging the capacitors of the respective capacitor networks). To enable this operation, the second switching network SN8, SN10, SN12 of each second sample and hold

circuit

408, 410, 412 may be enabled in a cycle of two cycles after charging the capacitor of the respective capacitor network.

Implementing the sample-and-hold circuit using switches and capacitors enables the sample-and-hold circuit to be implemented using active components, enabling the sample-and-hold circuit to be implemented in a simple manner, thereby reducing the complexity of the sample-and-hold circuit and the overall pipelined ADC.

Each switching network may be enabled by one or more control signals (e.g., clock signals). Referring now to fig. 6A-6B, fig. 6A-6B illustrate examples of control signals that may be used to control the switching network of fig. 5. For example, the first switching networks SN1, SN7 of the first and second sample-and-hold circuits of the first channel 214 may be controlled by a sampling channel 1 signal that causes the one or more capacitors of the respective capacitor networks CN1, CN4 to be charged by the received analog signal every three cycles; said first switching networks SN3, SN8 of said first and second sample-and-hold circuits of said second channel 216 are controllable by a sampling channel 2 signal, said sampling channel 2 signal being offset from said sampling channel 1 signal by a cycle which causes said one or more capacitors of respective capacitor networks CN2 and CN5 to be charged by said received analog signal every three cycles; the first switching networks SN5, SN9 of the first and second sample-and-hold circuits of the third channel 218 may be controlled by a sampling channel 3 signal that causes the one or more capacitors of the respective capacitor networks CN3 and CN6 to be charged by the received analog signal every three cycles.

The second switching networks SN2, SN4, SN6 of the first sample-and-

hold circuits

402, 404, 406 of the first, second and

third channels

214, 216, 218 may be controlled by Q-

channel

1, 2 and 3 signals, respectively, which cause the one or more capacitors of the respective capacitor networks CN1, CN2, CN3 to discharge for one cycle after charging the one or more capacitors of the capacitor networks CN1, CN2, CN 3. (e.g., one cycle after sampling the received analog signal).

The second switch networks SN8, SN10, SN12 of the second sample-and-

hold circuits

408, 410, 412 of the first, second, and

third channels

214, 216, 218 may be controlled by

channel

1, 2, and 3 signals, respectively, that cause the one or more capacitors of the respective capacitance networks CN4, CN5, CN6 to discharge two cycles (e.g., two cycles after sampling of the received analog signal) after the one or more capacitors of the capacitor networks CN4, CN5, CN6 are charged.

As can be seen in fig. 6A-6B, this results in the presence of a continuously repeating three cycle pattern, wherein in a first cycle 602 of the three cycle pattern, the one or more capacitors of capacitor networks CN1 and CN4 are charged by the received analog signal (e.g., the capacitors of the CN1 and CN4 capacitor networks sample the received analog signal). The one or more capacitors of the CN3 capacitor network are discharged to the quantization circuit 210 (e.g., samples from the CN3 capacitor network are output to the quantization circuit 210), the one or more capacitors of the CN5 capacitor network are discharged to the amplification circuit 212 (e.g., samples of the CN5 capacitor network are output to the amplification circuit 212), and the one or more capacitors of the CN6 capacitor network retain their values.

In the second cycle 604 of this three-cycle mode, the one or more capacitors of the CN2 and CN5 capacitor networks are charged, the one or more capacitors of the CN1 capacitor network are discharged to the quantization circuit 210, the one or more capacitors of the CN6 capacitor network are discharged to the amplification circuit 212, and the one or more capacitors of the CN4 capacitor network maintain their values. In the third cycle 606 of this three-cycle mode, the one or more capacitors of the CN3 and CN6 capacitor networks are charged by the received analog signal, the one or more capacitors of the CN2 capacitor network are discharged to the quantization circuit 210, the one or more capacitors of the CN4 capacitor network are discharged to the amplification circuit 211, and the one or more capacitors of the CN5 capacitor network maintain their values.

Referring now to fig. 7, fig. 7 illustrates an example implementation of a switch and capacitor network in a channel. In particular, fig. 7 shows the first and second sample-and-

hold circuits

402 and 408 of the first channel 214. The first sample and hold circuit 402 includes first and second switches S1, S1 'forming a first switch network SN1, a capacitor C1 forming a capacitor network CN1, and third and fourth switches S2, S2' forming a second switch network SN 2. Likewise, the second sample and hold circuit 408 includes first and second switches S7 and S7 'forming a switch network SN7, a capacitor C4 forming a capacitor network CN4, and third and fourth switches S8 and S8' forming a switch network SN 8. The switches of the switching network may be enabled simultaneously, or one switch of the switching network may be enabled after another switch of the switching network. For example, in some cases, S7 may be enabled after S7'.

In one example, in a first cycle, the switches S1, S1 ', S7, and S7' close and charge the respective capacitors C1 and C4. In a second cycle after the first cycle (e.g., in a cycle after the first cycle), switches S1, S1 ', S7, and S7 ' are open, and S2 and S2 ' are closed, so that the voltage in capacitor C1 is provided to the sub-ADC 220, and the sub-ADC 220 converts the voltage to an N-bit value. In a third cycle after the second cycle (e.g., in a cycle after the second cycle), the switches S7 and S7 'are opened, the switches S8 and S8' are closed, so that the second analog signal (the analog signal representing the N-bit value output from the sub-ADC 220) is connected to C4, and C4 causes the second sample-and-hold circuit 408 to function as a subtraction circuit to output the residual error (the difference between the sample value in C4 and the second analog signal (the analog signal representing the N-bit value output from the sub-ADC 220)). The amplifier 226 then amplifies the residual signal to generate the amplified residual signal for the samples in the first channel.

Although fig. 7 shows the switch and capacitor network for the first channel 214, the switch and capacitor networks for the

other channels

216, 218 may be implemented in a similar manner.

Referring now to fig. 8, fig. 8 illustrates a flow chart of an example method 800 for generating a predetermined number of bits representing digital values of an analog signal that may be implemented by the modified non-final stage 202 of the pipelined ADC 200 of fig. 2. In each cycle, the received analog signal is sampled by one of the three channels of the input sampling circuit 208 (in block 802). Channels are selected as sampling channels in a round robin fashion (e.g., channel 1 selected, channel 2 selected, channel 3 selected, channel 1 selected, channel 2 selected, etc.). Samples from a channel other than the channel used to sample the received analog signal are quantized (in block 804) to a predetermined number of bits in the same cycle. For example, if channel 1 is used to sample the received analog signal, the samples of channel 3 may be quantized. Further, in the same cycle, an amplified residual signal is generated (in block 806) for samples of a channel different from the channel used to sample the received signal or the quantized channel. For example, if channel 1 is used for samples 22014and the received analog signal is quantized and the samples of channel 3 are quantized, an amplified residual signal is generated for the samples of channel 2. As described above, generating the sampled residual signal may include: generating an analog signal according to a predetermined number of bits generated from the quantizing to generate a second analog signal, subtracting the second analog signal from the samples to generate a residual signal, and amplifying the residual signal to generate an amplified residual signal.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features. Such features or combinations of features can be implemented as a whole based on the present description, without regard to whether such features or combinations of features solve any of the problems disclosed herein, with the ordinary knowledge of a person skilled in the art; and do not contribute to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A pipelined analog-to-digital converter (200), comprising:

a plurality of stages (202, 203, 204) for generating one or more bits of an output digital signal from an input analog signal, at least one (202) of the plurality of stages comprising:

an input sampling circuit (208) comprising three or more channels (214, 216, 218), wherein one channel of the three or more channels (214, 216, 218) is used to sample the input analog signal within a cycle;

a quantization circuit (210) in the loop for receiving samples from another of the three or more channels (214, 216, 218) and quantizing the received samples into one or more bits of the output digital signal;

an amplification circuit (212) in the loop for receiving a sample and the one or more bits corresponding to the sample from a further one of the three or more channels (214, 216, 218) and generating an amplified residual signal from the received sample and the one or more bits.

2. The pipeline analog-to-digital converter (200) of claim 1, wherein the quantization circuit (210) is configured to quantize the received samples for a maximum time period, the maximum time being a sampling period of the pipeline analog-to-digital converter (200).

3. The pipeline analog-to-digital converter (200) of claim 1, wherein the amplification circuit (212) is configured to generate the amplified residual signal for the received samples within a maximum time period, the maximum time period being a sampling period of the pipeline analog-to-digital converter (200).

4. The pipeline analog-to-digital converter (200) of any preceding claim, wherein each of the three or more channels (214, 216, 218) is configured to sample the input analog signal for a maximum time, the maximum time being a sampling period of the pipeline analog-to-digital converter (200).

5. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein at least one of the three or more channels (214, 216, 218) of the input sampling circuit (208) comprises a first sample-and-hold circuit (402, 404, 406) and a second sample-and-hold circuit (408, 410, 412), the first sample-and-hold circuit (402, 404, 406) being configured to sample the input analog signal in a first cycle and output the sample to the quantization circuit (210) in a second cycle after the first cycle, and the second sample-and-hold circuit (408, 410, 412) being configured to sample the input analog signal in the first cycle and output the sample to the amplification circuit (212) in a third cycle after the second cycle.

6. Pipeline analog-to-digital converter (200) according to claim 5, characterized in that the first sample-and-hold circuit (402, 404, 406) comprises a first switch network (SN1, SN3, SN5), a capacitor network (CN1, CN2, CN3) and a second switch network (SN2, SN4, SN6), the first switch network (SN1, SN3, SN5) being enabled in the first cycle such that the input analog signal is sampled to the capacitor network (CN1, CN2, CN3) in the first cycle, the second switch network (SN2, SN4, SN6) being enabled in the second cycle such that the sample is provided to the quantization circuit (210) in the second cycle.

7. The pipelined analog-to-digital converter (200) of claim 5, characterized in that the second sample-and-hold circuit (408, 410, 412) comprises a first switch network (SN7, SN9, SN11), a capacitor network (CN4, CN5, CN6) and a second switch network (SN8, SN10, SN12), the first switch (SN7, SN9, SN11) being enabled in the first cycle such that the input analog signal is sampled to the capacitor network (CN4, CN5, CN6) in the first cycle, the second switch network (SN8, SN10, SN12) being enabled in the third cycle such that the sample is provided to the amplifying circuit (212) in the third cycle.

8. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein the quantization circuit (210) comprises a single sub-analog-to-digital converter (220) shared by the three or more channels (214, 216, 218).

9. The pipeline analog-to-digital converter (200) of claim 8, wherein the single sub-analog-to-digital converter (220) is a flash analog-to-digital converter.

10. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein the amplification circuit (212) is configured to:

converting the one or more bits to a second analog signal;

subtracting the second analog signal from the received samples to generate a residual signal;

amplifying the residual signal to generate the amplified residual signal.

11. The pipeline analog-to-digital converter (200) of claim 10, wherein the amplification circuit (212) comprises an amplifier (226), the amplifier (226) being configured to amplify the residual signal to produce the amplified residual signal, the amplification circuit (212) being further configured to reset the amplifier (226) before the amplifier (226) amplifies the residual signal to produce the amplified residual signal.

12. The pipeline analog-to-digital converter (200) of claim 10, wherein the amplification circuit (212) comprises a multiplying digital-to-analog converter circuit.

13. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein:

in a first reference cycle (302), a first channel (214) of the three or more channels samples the input analog signal, the quantization circuit quantizes the samples from a third channel (218) of the three channels, and the amplification circuit generates an amplified residual signal based on samples from a second channel (216) of the three or more channels;

in a second reference cycle (304) immediately following the first reference cycle, the second channel (216) samples the input analog signal, the quantization circuit quantizes the samples from the first channel (214), the amplification circuit generates an amplified residual signal from the samples from the third channel (218);

in a third reference cycle (306) immediately following the second reference cycle, the third channel (218) samples the input analog signal, the quantization circuit quantizes the samples from the second channel (216), and the amplification circuit generates an amplified residual signal from the samples from the first channel (214).

14. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein each of the three or more channels (214, 216, 218) is configured to sample the input analog signal at a rate of one-third of a sampling rate of the pipeline analog-to-digital converter (200).

15. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein the multiple stages (202, 203, 204) comprise a second stage (203, 204) after the at least one stage (202), the second stage (203, 204) comprising one of:

(i) a flash memory analog-to-digital converter;

(ii) a successive approximation analog-to-digital converter;

(iii) a second input sampling circuit comprising three or more channels, one of the three or more channels of the second input sampling circuit being used to sample the amplified residual signal in the loop;

a second quantization circuit in the loop to receive samples from another one of the three or more channels of the second input sampling circuit and quantize the received samples into one or more bits of the output digital signal;

a second amplification circuit in the loop to receive a sample and the one or more bits corresponding to the sample from a further one of the three or more channels of the second input sampling circuit and to generate a second amplified residual signal from the received sample and the one or more bits.

16. The pipeline analog-to-digital converter (200) of any of claims 1-3, wherein the three or more channels comprise only three channels.

17. A method (800) of generating one or more bits of an output digital signal representing an input analog signal, the method comprising, in one cycle:

a. sampling (802) the input analog signal for one of three or more channels, the one of the three or more channels being selected in a cyclic manner;

b. a quantization circuit quantizes (804) samples received from another of the three or more channels into one or more bits of the output digital signal;

c. an amplification circuit generates (806) an amplified residual signal from a sample received through yet another one of the three or more channels and the one or more bits corresponding to the sample.