KR20110090669A - Analog-to-digital converter with successive approximation register - Google Patents

Abstract

PURPOSE: An ADC(Analog to Digital Converter) with a successive approximation register is provided to reduce a design area by simply changing the structure of an analog to digital converter with a SAR(Successive Approximation Register). CONSTITUTION: A reference unit(100) generates the reference voltage of a conversion section. A timing unit(500) generates the reference time for the total conversion process of an analog input signal. A digital error correction unit(600) mixes conversion codes in a digital part based on the reference generated in the timing unit. The digital error correction unit generates the digital total conversion codes of the analog input signal. The conversion codes in a digital part are generated in a first flash ADC(ANALOG TO DIGITAL CONVERTER,200) and a second flash ADC(300).

Description

ANALOG-TO-DIGITAL CONVERTER WITH SUCCESSIVE APPROXIMATION REGISTER}

The present invention relates to a Successive Approximation Register Analog to Digital Converter (SAR ADC), and more particularly, to a Successive Approximation Register (SAR) used in an analog-to-digital converter. It is possible to reduce the design area of the analog-to-digital converter by simply changing the structure of the digital-to-analog converter, and the present invention relates to a successive approximation register-type analog-to-digital converter that can minimize power consumption and reduce internal noise. .

Analog-to-digital converters are devices for converting analog signals into digital codes and have various capabilities and forms. Among ADCs, in particular, SAR ADCs have a successive approximation register (SAR), which combines the digital code sequentially from the higher bits and combines it with an analog signal to approximate the analog input voltage.

1 is a control block diagram of a conventional SAR ADC.

As shown in FIG. 1, a conventional SAR ADC receives an analog input voltage through a non-inverting terminal (+), receives a reference voltage through an inverting terminal (-), and compares the comparator 2 and the comparator 2. The control logic circuit 8 generates a control signal after receiving the output signal of the control signal and outputs the control signal, and a digital signal corresponding to the reference voltage input to the comparator 2 in response to the control signal of the control logic circuit 8. A SAR (Successive Approximation Register) section 10 for outputting and an N-bit Digital-Analog Converter (DAC) 4 for converting a digital signal corresponding to the reference voltage into an analog reference voltage and outputting the analog signal to the comparator 2 do.

 The N bit DAC 4 converts the N bit digital code into a corresponding reference voltage. The comparator 2 compares the reference voltage output from the N-bit DAC 4 with the analog input voltage to be converted. If the voltage of the input voltage is larger than the voltage of the comparison signal, the output of the comparator 2 becomes a high level Hi, that is, a logic value 1. On the contrary, if the voltage of the input voltage is smaller than the voltage of the comparison signal, the comparator 2 outputs a signal of the low level Lo, that is, the logic value 0.

The SAR unit 10 includes an N-shift register 15 and an N-bit storage register 18 to produce a final conversion code at the time of partial conversion code output. After all the bits of the SAR unit 10 are initialized to '0' by the control signal of the adjustment logic circuit 8, an '1' is assigned to the first bit, which is the most significant bit of the SAR unit 10, and converted into analog. After that, the comparator 30 compares the analog input voltage.

According to the comparison result, if the analog input voltage is greater than the reference voltage, the first bit of the SAR 50 is stored as '1', and if the analog input voltage is smaller, the first bit is cleared to '0'. That is, when the analog input voltage is larger than the reference voltage, the contents of the SAR 10 are changed.

FIG. 2 is a control block diagram of a conventional SAR unit 10, which shows the structure of a register when two bits are obtained at a stage and the data is stored.

The timing register 15 of the SAR unit 10 is composed of the total number of registers up to the final output in the case of the data coming out of the first stage, and in the case of the next stage, a pair of registers is reduced in the number of stages. It consists of. In this way, the shift register for the total N stages is configured and the error of the digital code converted by the error correction logic circuit 19 is corrected.

According to this configuration, the conventional SAR unit 10 repeats the above-described comparison process while sequentially changing subsequent bits of the digital code input to the N-bit DAC 100, so that the SAR unit 15 after N cycles A digital code of N bits corresponding to the analog input signal can be determined.

For example, when a 12-bit SAR ADC is configured, the comparison process of the reference voltage and the analog input voltage is performed 12 times. When the analog input signal corresponding to the 12-bit is input, the signal of the comparator is the first according to the comparison result. The SAR unit 10 from cycle to twelfth cycle may sequentially determine the digital code of the final input voltage.

The conventional SAR DAC structure has a large increase in the number of required shift registers when the resolution is increased or the number of bits processed in one stage increases, resulting in an increase in design area and power consumption, and there is a concern of noise generation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a successive approximation register type analog-to-digital converter that can reduce a design area and minimize power consumption.

According to the present invention, there is provided a successive approximation register type analog-to-digital converter comprising: a reference unit for generating a reference voltage in a conversion section; A first flash ADC and a second flash ADC for comparing the reference voltage with an input voltage of an analog input signal to generate a digital partial conversion code of a predetermined section of the input voltage; A multiplying DAC (MDAC) for amplifying a difference between the input voltage and a reference voltage and inputting the first and second flash ADCs to the first and second flash ADCs; A timing unit for generating a reference time of the entire conversion process of the analog input signal; A digital error correction unit configured to generate the entire digital conversion code of the analog input signal by combining the digital partial conversion codes generated from the first flash ADC and the second flash ADC based on the reference time generated by the timing unit; do.

As described above, the successive approximation register type analog-to-digital converter of the present invention can reduce the design area by simply changing the structure of the successive approximation register (SAR) type digital-analog conversion element. In addition, it is possible to provide a successive approximation register type analog-to-digital converter that can minimize power consumption and reduce internal noise.

1 is a block diagram of a SAR ADC according to the prior art,
2 is a register configuration diagram of a SAR of the SAR ADC of FIG. 1;
3 is a block diagram of a SAR ADC according to the present invention;
4 is a control block diagram of a digital error correction unit of a SAR ADC according to a first embodiment of the present invention;
5 is a control block diagram of a digital error correction unit of a SAR ADC according to a second embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the successive approximation register type analog-to-digital converter according to the present invention. However, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

3 is a control block diagram of a successive access register analog to digital converter (SAR ADC) according to the present invention.

As shown in FIG. 3, the SAR ADC according to the present invention includes a reference unit 100 for generating a reference voltage in a conversion period, a first flash ADC 200 for comparing a reference voltage and an input voltage of an input signal, and Digital generation using the second flash ADC (300), MDAC (Multiplying DAC) 400 to amplify the difference between the input voltage and the reference voltage and a partial conversion code generated at each step An error correction unit 600 and a timing unit 500 for generating a reference time of the entire conversion process.

The reference unit 100 determines a range of the converted input voltage of the ADC and generates a reference voltage for dividing the sections. The reference voltage generated by the reference unit 100 is input to the first flash ADC 200, the second flash ADC 300, and the MDAC 400. Therefore, since the voltage is always compared only in a predetermined voltage section, only the resolution of the generated partial code is required for the first flash ADC 200, the second flash ADC 300, and the MDAC 400.

The first flash ADC 200 and the second flash ADC 300 compare the reference voltage output from the MDAC 400 with the analog input voltage to be converted. When the input voltage is greater than the voltage of the comparison signal, the outputs of the first flash ADC 200 and the second flash ADC 300 are at a high level Hi, that is, a logic value 1. On the contrary, when the voltage of the input voltage is smaller than the voltage of the comparison signal, the first flash ADC 200 and the second flash ADC 300 output a low level Lo, that is, a signal having a logic value of zero. The first flash ADC 200 may output the first partial conversion code [1: 0], and the second flash ADC 300 may output the second partial conversion code [1: 0].

The MDAC 400 amplifies the difference between the input voltage and the reference voltage output from the first flash ADC 200 and the second flash ADC 300. The MDAC 400 provides the difference between the amplified reference voltages to the first flash ADC 200 and the second flash ADC 300, respectively. In addition, by using an amplifier shared with the MDAC 400, power and design area can be minimized while doubling the conversion speed.

The digital error correction unit 600 generates the entire code using the partial conversion code, and corrects an error generated during the conversion process. In other words, the entire digital code is generated by performing only the interval conversion corresponding to each step, not changing the entire bit. Here, the error may occur in the ambiguity and all other circuit noises in the change of the reference voltage or the signal processing at the reference voltage boundary, so that the digital error correction unit 600 corrects the error of the partial conversion code and outputs the error. It may include.

The timing unit 500 receives an external reference clock and generates clocks Q1 and Q2 for determining sampling timings of the first and second flash ADCs, and a counter signal counting the clocks.

With this configuration, the SAR ADC of the present invention receives an analog input voltage to be converted only when performing an operation for making the first partial conversion code, and thereafter, converts it using the block sampling function of the flash ADC in the operation. Code generation can be performed. Therefore, the SAR ADC of the present invention can be implemented without adding a configuration for maintaining the analog input voltage to be converted during the generation of the conversion code.

4 is a control block diagram of the digital error correction unit 600 of the SAR ADC according to the first embodiment of the present invention.

The digital error correction unit 600 of the SAR ADC according to the first embodiment includes a timing register 610 including a demultiplexer 612 and a register unit 616, and an error correction logic circuit 650 for error correction. Include.

The timing register 610 is supplied with clocks Q1 and Q2 for determining sampling timings of the first and second flash ADCs, and a counter signal SP for counting the clocks to indicate the order of the partial conversions. Code (Most Significant Bit (MSB): Least Significant Bit (LSB) "LSB") is transmitted. The clocks Q1 and Q2 and the counter signal SP provided to the timing register 610 may be generated by the timing unit 500, and the partial conversion code MSB: LSB may be generated by the first flash ADC 200. And a second flash ADC 300.

Demultiplexer 612 of timing register 610 includes N output ports for outputting the output of each partial conversion step. The demultiplexer 612 receives the partial conversion code [MSB: LSB] from the first flash ADC 200 and the second flash ADC 300, and demultiplexes according to the counter signal SP to convert each step. The partial conversion code [MSB: LSB] is transferred to the register section 616.

The register unit 616 of the timing register 610 operates by receiving clocks Q1 and Q2 that determine sampling timings of the flash ADCs 200 and 300. Therefore, the partial conversion code [MSB: LSB] is stored only in the register (Reg) into which the clocks (Q1, Q2) are input, so that the partial conversion code generated at the stage of the predetermined sequence is immediately stored in the register (Reg) of the corresponding sequence. Can be. Here, the individual registers constituting the register unit 616 operate as a single cell in which the storage register Reg1 in which the partial conversion code is stored and the correction register Reg2 in which additional information necessary for error correction are stored. Can be configured to

As described above, when the partial conversion codes generated at these stages are stored in the corresponding registers by using the demultiplexer 612 and the counter signal, the shift register for timing is not required. In addition, since the demultiplexer 612 and the counter have a nearly constant size even when the resolution of the ADC increases, the design area is reduced by minimizing the number of registers when the shift register is replaced by using the demultiplexer 612 and the counter. You can get the effect.

For example, when designing a SAR ADC for converting a 12-bit digital code according to the present invention, a storage register Reg1 in which a partial conversion code is stored and a correction register Reg2 in which additional information necessary for error correction are stored are included. Designed with 24 registers. On the other hand, in the 12-bit ADC according to the prior art, one bit for data and one bit for correction are generated for each stage for error correction, and a total of 156 registers are required when converting through a total of 12 steps.

5 is a schematic control block diagram of a SAR ADC according to a second embodiment of the present invention, which illustrates a case where a demultiplexing function of the digital error correction unit 600 is implemented using a decoder.

The timing unit 500 receives an external reference clock and receives clocks Q1 and Q2 for determining sampling timings of the first flash ADC and the second flash ADC, and a counter signal SP1 that counts the clocks to inform each partial conversion order. ~ SPN). Accordingly, the timing unit 500 may be configured with two dividers for generating the clocks Q1 and Q2 and counters for generating the counter signals SP1 to SPN.

The digital error correction unit 600 may include a timing register 610 and an error correction logic circuit 650, where the timing register 610 may include a decoder unit 614 and a register unit 618. have.

The decoder 614 performs AND on the clock signal Q and the counter signal SP provided by the timing unit 500 to generate register clock signals S1 to SN. The register clock signals S1 to SN generated by the decoder 614 may be made to have the same waveform as the counter signals SP1 to SPN generated by the timing unit 500.

The register unit 618 includes a plurality of registers that operate according to the register clock signals S1 to SN output from the decoder unit 614. The plurality of registers selectively perform operations according to a high edge or a high level of the register clock signals S1 to SN, and are output by the first flash ADC 200. The first partial conversion code [MSB: LSB] (F1), the second partial conversion code [MSB: LSB] (F2) output from the second flash ADC 300, and the conversion code [MSB: LSB of the last step (SN) Each can be stored up to] (FN). Here, the individual registers constituting the register unit 618 operate as a single cell in which the storage register Reg1 in which the partial conversion code is stored and the correction register Reg2 in which additional information necessary for error correction are stored. Can be configured to These individual registers can be implemented as flip-flops or a single latch.

With this configuration, when the decoder unit 614 outputs the register clock signals S1 to SN, the corresponding register is operated to perform only interval conversion corresponding to each step to generate the entire digital code, and the error correction logic circuit 650. ) Can be used to generate the entire digital code by correcting errors.

As described above, in the case of converting an input voltage into a digital code, the SAR ADC according to the present invention performs only the interval conversion corresponding to each partial conversion step, and then outputs after correcting an error in the stored partial conversion code. Has a structure. Accordingly, the number of registers is optimized by the sum of the number of bits of the final digital code and the number of bits for correction. Reducing the number of resistors not only reduces design area, but also reduces power consumption and reduces the amount of digital noise.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

100: reference unit 200: first flash ADC
300: second flash ADC 400: MDAC
500: timing unit 600: digital error correction unit
610: timing register 612: demultiplexer
614: decoder 650: error correction logic circuit

Claims (9)

A reference unit generating a reference voltage of the conversion section;
A first flash ADC and a second flash ADC for comparing the reference voltage with an input voltage of an analog input signal to generate a digital partial conversion code of a predetermined section of the input voltage;
A multiplying DAC (MDAC) for amplifying a difference between the input voltage and a reference voltage and inputting the first and second flash ADCs to the first and second flash ADCs;
A timing unit for generating a reference time of the entire conversion process of the analog input signal;
A digital error correction unit configured to generate the entire digital conversion code of the analog input signal by combining the digital partial conversion codes generated from the first flash ADC and the second flash ADC based on the reference time generated by the timing unit; Sequential Approximation Register Type Analog-to-Digital Converter. The method of claim 1,
The timing unit,
Dividing a clock input from an external device to generate sampling timing clocks of the first and second flash ADCs;
And a counter for counting the timing clock to generate a counter signal informing the conversion order of the partial conversion code. The method of claim 2,
The digital error correction unit,
A demultiplexer receiving the partial conversion code from the first flash ADC and the second flash ADC and demultiplexing the partial conversion code into a plurality of output terminals according to the counter signal;
And a register portion having a plurality of registers respectively connected to the plurality of output stages of the demultiplexer and storing the partial conversion code in accordance with the sampling timing clock. The method of claim 3,
The register unit,
A storage register connected to the plurality of output terminals of the demultiplexer, respectively, to store the partial conversion code;
And a correction register for storing information for error correction of the partial conversion code stored in the storage register. The method of claim 3,
The digital error correction unit,
And an error correction logic circuit for combining the partial conversion codes stored in the plurality of registers to generate a digital total conversion code of the analog input signal. The method of claim 2,
The digital error correction unit,
A decoder unit for generating a register clock signal for activating a register in which a partial conversion code of a current conversion step is to be stored, based on the sampling timing clock and the counter signal;
And a register section having a plurality of registers for storing the partial conversion codes outputted from the first flash ADC and the second flash ADC according to the register clock signal provided by the decoder section. The method of claim 6,
The decoder unit,
And a step approximation register type analog-to-digital converter for generating the register clock signal by performing an AND operation on the sampling timing clock and the counter signal. The method of claim 6,
The register unit,
A storage register connected to the plurality of output terminals of the demultiplexer, respectively, to store the partial conversion code;
And a correction register for storing information for error correction of the partial conversion code stored in the storage register. The method of claim 6,
The digital error correction unit,
And an error correction logic circuit for combining the partial conversion codes stored in the plurality of registers to generate a digital total conversion code of the analog input signal.

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