CN110690901A - High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit - Google Patents
High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit Download PDFInfo
- Publication number
- CN110690901A CN110690901A CN201910851588.4A CN201910851588A CN110690901A CN 110690901 A CN110690901 A CN 110690901A CN 201910851588 A CN201910851588 A CN 201910851588A CN 110690901 A CN110690901 A CN 110690901A
- Authority
- CN
- China
- Prior art keywords
- calibration
- module
- sar adc
- capacitor
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
Abstract
The invention provides a capacitor mismatch calibration technology applied to a high-speed low-power-consumption successive approximation type digital-to-analog converter (SAR ADC). The invention is a capacitance mismatch foreground calibration scheme based on code density statistics, the calibration circuit cost is low, and high-speed low-power-consumption design is easy to realize. The SAR ADC calibration circuit mainly comprises an SAR ADC core conversion module, a calibration circuit module, a calibration capacitor module and an on-chip linear waveform generator. After a system is electrified, an ADC firstly enters a calibration mode, capacitors to be calibrated are sequentially calibrated from low level to high level, at the moment, an SAR ADC core conversion module samples and converts signals generated by an on-chip linear waveform circuit, and calibration codes of the capacitors to be calibrated are output; after the calibration is finished, the ADC enters a normal conversion mode, and the SAR ADC core conversion module samples and converts external input; and the digital calibration logic controls the capacitor bottom plate of the calibration capacitor module to be connected with corresponding potential according to the calibration code and ADC digital output, and completes each comparison successively.
Description
The technical field is as follows:
the invention discloses a self-calibration method and a circuit for capacitor mismatch in SAR ADC, which are mainly applied to ADC chips or SOC design in high-speed low-power consumption small-size application.
Background art:
since the invention, the integrated circuit has been developed rapidly along moore's law, the line width of the process is continuously reduced, and the integration level is continuously increased. The continuous improvement of the process is crucial to the development of digital circuits, and the development of digital signal processing capability and digital storage technology is mature to the present society. As a bridge between the analog world and the digital circuit, an Analog Digital Converter (ADC) is a very important module, and has wide applications in various fields including communication, energy, medical treatment, instruments and meters, and even in the AI field which is now rapidly developing. It can be said that the development of ADCs has restricted the development of integrated circuits as a whole.
In many applications, many modules need to be integrated into a system, so-called SOC (system on chip), in which the ADC is often located at the analog back end or the radio frequency front end. In the SOC design, the ADC is required to be designed with small size and low power consumption, and in order to reduce the load on the previous stage, the input capacitance of the ADC is often designed to be very small, which puts more strict requirements on the area and power consumption of the ADC. In these applications, the SAR ADC is the most commonly used structure because of its simple structure, small area and low power consumption, while in the conventional SAR ADC, the DAC capacitor array occupies the largest area ratio, often occupying about 1/3 of the whole ADC, and the large DAC capacitor means a large input capacitor, so in order to further reduce the capacitor size and reduce the input capacitor, the unit capacitor needs to be designed to be small, which brings about a large capacitor mismatch, and a capacitor mismatch calibration technique needs to be added. The invention provides a capacitance mismatch foreground calibration method based on code density statistics, which is simple in circuit structure, low in power consumption and great in prospect in high-speed low-power consumption and small-size application.
The invention content is as follows:
the invention provides a capacitance mismatch foreground calibration scheme applied to a high-speed SAR ADC, which is designed according to the principle that the density distribution of codes at certain specific positions can generate multiple codes or less codes due to capacitance mismatch, and the calibration circuit has low cost and is easy to realize high-speed low-power-consumption design.
The capacitor mismatch calibration circuit of the invention is composed of a calibration circuit module 101, a calibration capacitor module 102, an SAR ADC core conversion module 103 and an on-chip linear waveform generator 104, and the circuit architecture is shown in figure 1.
The SAR ADC core conversion module contained in the calibration circuit is a full-capacitance asynchronous clock SAR ADC, the high n bits (C1, C2 and …) of the SAR ADC core conversion module need to be calibrated, the value of n is related to the number of the designed ADC bits, and the capacitance needing to be calibrated is 205; and each capacitor needing to be calibrated corresponds to the capacitor section of different section bits in the calibration capacitor module. The calibration circuit module comprises a state controller 206, a digital calibration logic 207, a calibration code output register 208, a digital comparator 209; the state controller controls the SARADC core conversion module to enter different working modes, and the digital calibration logic module generates a control signal for calibrating the potential connected with the bottom plate of the capacitor; the calibration code output register stores a calibration code of each bit of capacitor to be calibrated; and the digital comparator completes the statistics and comparison of the digital codes output by the SAR ADC core conversion module.
The whole ADC work flow is as follows, after the system is powered on, a state controller in a calibration circuit module controls a SARADC core conversion module to firstly enter a calibration mode, capacitors to be calibrated are sequentially calibrated from low level to high level, at the moment, the SAR ADC core conversion module samples and converts signals generated by an on-chip linear waveform generation circuit, then a digital comparator in the calibration circuit module completes statistics and comparison of digital codes output by the SAR ADC core conversion module, a digital calibration logic outputs calibration codes of each bit of capacitors to be calibrated according to comparison results, and controls a capacitor bottom plate of the calibration capacitor module to be connected with corresponding electric potential; after the calibration is finished, the state controller controls the SAR ADC core conversion module to enter a normal conversion mode, and sampling and conversion are carried out on external input; and the digital calibration logic controls the capacitor bottom plate of the calibration capacitor module to be connected with corresponding potential according to the calibration code and the digital code output by the SAR ADC core conversion module. When the capacitance of the lower bit is calibrated, the capacitance higher than the number of the bits does not participate in DA conversion, and the bottom plates of the high-bit capacitors are connected with a common mode level, so that the capacitance of each bit can be considered as the highest-bit capacitor when being calibrated.
The SAR ADC core conversion module is in a capacitance type synchronous logic asynchronous clock SAR ADC circuit structure, the sampling input of the SAR ADC core conversion module can be external analog input, and can also be a signal generated by an on-chip linear waveform generator, wherein the on-chip linear waveform generator can generate a triangular wave signal or a ramp signal; in the calibration mode, the state controller controls the SAR ADC core conversion module to sample a signal generated by the on-chip linear waveform generator; during normal conversion, the SAR ADC core conversion module samples external analog input.
The control signal of the level connected with a capacitor bottom plate in the calibration capacitor array is generated by a digital calibration logic module, and in a calibration mode, the digital calibration logic module generates a control signal according to the output of a digital comparator; under the normal conversion mode, the digital calibration logic module generates a control signal according to the calibration code and the digital code output by the SAR ADC core conversion module.
The calibration capacitor module is a full capacitor array, each capacitor needing to be calibrated in the SAR ADC core module corresponds to a calibration capacitor section of the SAR ADC core module, the capacitors share a top plate, and a bottom plate can be connected with different voltages; one end of Cc in the calibration capacitor module is connected with a common top plate of the calibration capacitor, and the other end of Cc is connected with a top plate of the capacitor array in the SAR ADC core module.
The invention has the advantages that the cost of the capacitor mismatch calibration circuit is low, the circuits added on the basis of the SAR ADC main circuit are few, the SAR ADC main circuit is basically not changed, and high-speed conversion can be realized.
Description of the drawings:
FIG. 1 shows a circuit structure for calibrating a capacitor mismatch applied in a high-speed SAR ADC according to the present invention
FIG. 2 Overall ADC work flow diagram
FIG. 3 illustrates the corresponding change in symbol distribution when the highest bit capacitance mismatch occurs
The specific implementation mode is as follows:
the invention is further described below with reference to the figures and examples.
The invention relates to a capacitor mismatch self-calibration method and a circuit applied to a high-speed SAR ADC, wherein the circuit framework of the circuit is shown in figure 1, and the whole ADC circuit mainly comprises a calibration circuit module 101, a calibration capacitor module 102, an SAR ADC core conversion module 103 and an on-chip linear waveform generator 104.
The SAR ADC core conversion module contained in the calibration circuit is a full-capacitance asynchronous clock SAR ADC, the high n bits (C1, C2 and …) of the SAR ADC core conversion module need to be calibrated, the value of n is related to the number of the designed ADC bits, and the capacitance needing to be calibrated is 205; and each capacitor needing to be calibrated corresponds to a capacitor section of different section bits in the calibration capacitor module, and the calibration capacitor only participates in DA conversion and does not participate in sampling. The calibration circuit module comprises a state controller 206, a digital calibration logic 207, a calibration code output register 208 and a digital comparator 209; the state controller control circuit enters different working modes, and the digital calibration logic module generates a control signal for calibrating the potential connected with the capacitor bottom plate; the calibration code output register stores a calibration code of each bit of capacitor to be calibrated; and the digital comparator completes the statistics and comparison of the digital codes output by the SAR ADC core conversion module.
The invention provides a foreground calibration scheme.A linear waveform generator on a chip comprises a triangular wave generator and a ramp signal generator, wherein the triangular wave generator is used below, and a calibration conversion process is illustrated by taking high two-bit capacitors C1 and C2 in a calibration SAR ADC core conversion module as an example:
after the system is powered on, the ADC operation flow chart is shown in fig. 2, the state controller in the calibration circuit module controls the sar ADC core conversion module to first enter the calibration mode, first calibrate C2, and the bottom plate of the capacitor C1 is connected to a fixed potential, so that C2 is equivalent to the highest-order capacitor. For a binary SAR ADC, when the input signal varies linearly around zero, the digital code will be distributed uniformly at the middle position of the whole symbol interval (all 0 to all 1), and if the capacitance value of C2 is larger than the designed value, multi-code will occur; as shown in fig. 3, based on this principle, after the SAR ADC core conversion module samples and converts the signal generated by the on-chip triangular wave circuit, the digital comparator in the calibration circuit module completes the statistics and comparison of the digital code, and according to the statistical result, the capacitance mismatch information can be obtained, and the DAC used for calibrating C1 in the calibration capacitance module is controlled to increase or decrease the number of capacitances participating in DA conversion, so that the code density is uniformly distributed; after calibration at C2, calibration at C1 is started, the same procedure as for calibration at C2. From the above analysis, it can be seen that, for the calibration of each bit of capacitor, the signal generated by the on-chip linear waveform generator only needs to have good linearity near the zero point, and the signal amplitude can be very small, so that the power consumption and the calibration time of the calibration circuit are greatly reduced.
After the whole calibration is finished, the state controller controls the SAR ADC core conversion module to enter a normal conversion mode, and sampling and conversion are carried out on external input; and the digital calibration logic controls the capacitor bottom plate of the calibration capacitor module to be connected with corresponding potential according to the calibration code and the digital code output by the SAR ADC core conversion module.
From the above analysis, the capacitor mismatch calibration circuit provided by the invention can realize the mismatch calibration of the multi-bit capacitor, has a simple circuit structure and low power consumption, does not influence the high-speed conversion of the SAR ADC, and has a great application prospect in the low-power small-size high-speed SARADC.
Claims (8)
1. The circuit is characterized by mainly comprising an SAR ADC core conversion module (103), a calibration circuit module (101), a calibration capacitor module (102) and an on-chip linear waveform generator (104), wherein the calibration circuit module (101) is connected with the SAR ADC core conversion module (103) and outputs calibration codes to the SAR ADC core conversion module (103), the SAR ADC core conversion module samples and converts signals generated by the on-chip linear waveform generator (104), the SAR ADC core conversion module (103) outputs digital codes to the calibration circuit module (101), the SAR ADC core conversion module (103) is connected with the calibration capacitor module (102), and the calibration circuit module (101) outputs level control signals connected with a capacitor bottom plate to the calibration capacitor module (102).
2. The capacitance mismatch self-calibration circuit of claim 1, wherein the SAR ADC core conversion module (103) is a full-capacitance asynchronous SAR ADC, the high n-bit capacitance of which, i.e., the calibrated capacitance (205), needs to be calibrated, the value of n being related to the designed ADC bit number.
3. The capacitance mismatch self-calibration circuit of claim 1, wherein said calibration circuit module (101) mainly comprises a state controller (206), a digital calibration logic (207), a calibration code output register (208), a digital comparator (209); the SAR ADC core conversion module (103) is controlled to enter different working modes by the state controller (206), and the digital calibration logic module (207) generates a control signal of the potential connected with the bottom plate of the calibration capacitor (205); the calibration code output register (208) stores the calibration code of each bit of the capacitor (205) to be calibrated; the digital comparator (209) completes the statistics and comparison of the digital code output by the SAR ADC core conversion module (103).
4. The capacitance mismatch self-calibration method according to claim 1, based on the capacitance mismatch self-calibration circuit according to claim 1, wherein after a system is powered on, a state controller (206) in a calibration circuit module (101) controls a SAR ADC core conversion module (103) to enter a calibration mode, capacitors (205) to be calibrated are sequentially calibrated from a low bit to a high bit, at this time, the SAR ADC core conversion module (103) samples and converts signals generated by an on-chip linear waveform generator (104), then a digital comparator (209) in the calibration circuit module (101) completes statistics and comparison of digital codes, and a digital calibration logic (207) outputs calibration codes of each bit of the capacitors (205) to be calibrated according to comparison results and controls a capacitor bottom plate of the calibration capacitor module (102) to be connected to a corresponding potential; after the calibration is finished, the state controller (206) controls the SAR ADC core conversion module (103) to enter a normal conversion mode, and sampling and conversion are carried out on external input; and the digital calibration logic (207) controls a capacitor bottom plate of the calibration capacitor module (102) to be connected with a corresponding potential according to the calibration code and the digital code output by the SAR ADC core conversion module (103).
5. The capacitance mismatch self-calibration circuit of claim 1, wherein capacitances higher than their number of bits do not participate in DA conversion when calibrating capacitances of lower bits, and the bottom plates of these capacitances of higher bits are connected to a common mode level.
6. The capacitance mismatch self-calibration circuit according to claim 1, wherein the digital calibration logic (207) generates a control signal for calibrating the level to which the capacitive bottom plate of the capacitive module (102) is connected, and in the calibration mode, the digital calibration logic (207) generates the control signal according to the output of the digital comparator (209); in the normal conversion mode, the digital calibration logic module (207) generates a control signal according to the calibration code and the digital code output by the SAR ADC core conversion module (103).
7. The capacitance mismatch self-calibration circuit of claim 1, wherein the SAR ADC core conversion module (103) is a capacitive synchronous logic asynchronous clock SAR ADC circuit structure, and its sampling input can be an external analog signal input, or a signal generated by an on-chip linear waveform generator (104), wherein the on-chip linear waveform generator (104) can generate a triangular wave signal or a ramp signal; the state controller (206) controls the sampling of the signal generated by the on-chip linear waveform generator (104) in the calibration mode; during normal conversion, the external analog input signal is sampled.
8. The circuit of claim 1, wherein the calibration capacitor module (102) is a full capacitor array, each capacitor (205) to be calibrated corresponds to its own calibration capacitor segment, and the capacitors share a top plate and a bottom plate that can be connected to different voltages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910851588.4A CN110690901A (en) | 2019-09-10 | 2019-09-10 | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910851588.4A CN110690901A (en) | 2019-09-10 | 2019-09-10 | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110690901A true CN110690901A (en) | 2020-01-14 |
Family
ID=69108877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910851588.4A Pending CN110690901A (en) | 2019-09-10 | 2019-09-10 | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110690901A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290945A (en) * | 2020-09-30 | 2021-01-29 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN112751565A (en) * | 2021-01-06 | 2021-05-04 | 北京遥测技术研究所 | Self-calibration on-chip reference voltage module |
| CN114614821A (en) * | 2022-03-30 | 2022-06-10 | 深圳齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9397679B1 (en) * | 2015-02-19 | 2016-07-19 | Stichting Imec Nederland | Circuit and method for DAC mismatch error detection and correction in an ADC |
| CN107437944A (en) * | 2017-07-21 | 2017-12-05 | 北京大学（天津滨海）新代信息技术研究院 | The self-alignment capacitor type gradually-appoximant analog-digital converter of numeral and its method for self-calibrating in a kind of strap |
-
2019
- 2019-09-10 CN CN201910851588.4A patent/CN110690901A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9397679B1 (en) * | 2015-02-19 | 2016-07-19 | Stichting Imec Nederland | Circuit and method for DAC mismatch error detection and correction in an ADC |
| CN107437944A (en) * | 2017-07-21 | 2017-12-05 | 北京大学（天津滨海）新代信息技术研究院 | The self-alignment capacitor type gradually-appoximant analog-digital converter of numeral and its method for self-calibrating in a kind of strap |
Non-Patent Citations (2)
| Title |
|---|
| 谷宪: "高速低功耗小尺寸SAR ADC IP设计", 《中国优秀硕士学位论文全文数据库 (信息科技辑)》 * |
| 谷宪等: "A Calibration Technique for SAR ADC Based On Code Density Test", 《2015年IEEE第11届ASIC国际会议》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112290945A (en) * | 2020-09-30 | 2021-01-29 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN112290945B (en) * | 2020-09-30 | 2023-03-28 | 西安电子科技大学 | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC |
| CN112751565A (en) * | 2021-01-06 | 2021-05-04 | 北京遥测技术研究所 | Self-calibration on-chip reference voltage module |
| CN112751565B (en) * | 2021-01-06 | 2024-02-09 | 北京遥测技术研究所 | Self-calibration on-chip reference voltage module |
| CN114614821A (en) * | 2022-03-30 | 2022-06-10 | 深圳齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
| CN114614821B (en) * | 2022-03-30 | 2023-10-20 | 广东齐芯半导体有限公司 | SAR ADC offset error correction method and circuit based on differential structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| US6473021B1 (en) | Analog to digital conversion circuits, systems and methods with gain scaling switched-capacitor array | |
| CN105007079A (en) | Fully differential increment sampling method of successive approximation type analog-digital converter | |
| CN110690901A (en) | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit | |
| CN105049049B (en) | A kind of capacitors exchange method for improving gradually-appoximant analog-digital converter DNL/INL | |
| CN102324934A (en) | Resistance-string multiplexing circuit structure of SAR ADC (successive approximation analog to digital converter) | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| CN102386923A (en) | Asynchronous successive approximation analog-to-digital converter and conversion method | |
| CN109787633A (en) | The Σ Δ ADC suitable for mixed type ADC structure with chopped wave stabilizing | |
| CN102594353A (en) | Digital-to-analog converter and successive approximation storage converter | |
| KR20060052937A (en) | Space efficient low power cyclic a/d converter | |
| CN105187065A (en) | Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof | |
| CN109936369A (en) | A kind of mixed structure SAR-VCO ADC | |
| CN204376879U (en) | There is the SAR ADC of mixed type DAC capacitor array structure | |
| US8963763B2 (en) | Configuring an analog-digital converter | |
| US7098840B2 (en) | Domino asynchronous successive approximation ADC | |
| CN106341133A (en) | Dual-channel time interleaved asynchronous assembly line flash analog-to-digital converter | |
| CN109462402B (en) | Mixed type assembly line ADC structure | |
| CN102857226B (en) | Successive approximation type analog-to-digital converter | |
| CN104753533A (en) | Staged shared double-channel assembly line type analog to digital converter | |
| CN101980446A (en) | High-performance low-power consumption pipeline analogue-to-digital converter | |
| CN102075192A (en) | High speed digital-analog conversion circuit and operating method thereof | |
| CN112187265A (en) | Mixed type analog-digital converter and signal transceiver for electric power special communication network | |
| CN114024550B (en) | Analog-to-digital converter and automatic power distribution equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200114 |