CN105187065A - Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof - Google Patents
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Abstract
The invention discloses a successive approximation ADC ultra-low power consumption capacitor array and a logic control method thereof and belongs to the successive approximation ADC ultra-low power consumption design technical field. The successive approximation ADC ultra-low power consumption capacitor array includes a binary capacitor array, a switch array and references (Vref, Vcm=Vref/2 and Gnd=0); the logic control method is a novel logic control method. According to the method, capacitor upper polar plate sampling, switch control time sequence initialization, parasitic capacitance power consumption reduction and capacitor monotonic switching are used in combination. The average energy consumption of the capacitor array is only 1.2% of a traditional charge redistribution structure. The capacitor array has advantages of simple structure, low power consumption, small size and so on. When the capacitor array and the logic control method thereof of the invention are applied to successive approximation ADC, power consumption can be significantly reduced. Under the same conversion accuracy, the size of the capacitor array of the invention can be decreased, so that improvement of A/D conversion rate can be benefitted.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly relate to a kind of super low-power consumption capacitor array for successive approximation analog to digital C and logic control method thereof.
Background technology
With capacitor array be agent structure Charge scaling type Approach by inchmeal (SAR) ADC rely on its low-power consumption advantage be applied widely, along with the progress of CMOS integrated circuit (IC) design technology and the reduction of technology feature size, SoC scale is increasing, especially at nerve signal record (EEG, ECOG etc.) in implantating biological electronic system, the ADC embedded wherein needs to possess super low-power consumption, miniaturized feature, the scale of traditional Charge scaling type SARADC capacitor array exponentially doubly increases with ADC figure place, be unfavorable for area, power consumption and speed-optimization.Shown in Fig. 1 is traditional N-bit fully differential Charge scaling type SARADC structure, and its capacitor array comprises 2 altogether
n+1individual specific capacitance.On the one hand, by the constraint of matching precision and noiseproof feature, not only circuit area is comparatively large, and process costs is high, and the dynamic power consumption of capacitor array is larger; On the other hand, large-scale capacitor array, causes the input capacitance of SARADC comparatively large, not only affects the raising of ADC sampling rate, and require that AFE (analog front end) (AFE) circuit has stronger driving force, affect the low-power consumption optimization of AFE circuit and whole SoC.
Summary of the invention
The object of the invention is to the shortcoming overcoming above-mentioned prior art, a kind of successive approximation analog to digital C super low-power consumption capacitor array and logic control method thereof are provided, it has super low-power consumption, miniaturized capacitance array and logic control mode, significantly can reduce the power consumption of SARADC, reduce chip area, save cost, the flexibility of capacitor array compatibility design can be improved simultaneously.
The object of the invention is to be achieved through the following technical solutions:
Successive approximation analog to digital C super low-power consumption capacitor array of the present invention, comprise (N-2)-bit binary capacitor array that two groups are connected to two inputs of comparator, often group (N-2)-bit binary capacitor array connects voltage reference V by switch arrays
ref, V
cm, Gnd; Often group (N-2)-bit binary capacitor array is by electric capacity C
0, C
1, C
2... C
n-2connect to form, wherein N is natural number; The electric capacity C of first group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
ip, the other end of each electric capacity is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The electric capacity C of second group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
in, the other end is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The output of comparator connects Approach by inchmeal logic control element SARLogic, according to the output of comparator, described Approach by inchmeal logic control element SARLogic realizes the logic control to capacitor array switch under the effect of clock signal clk and soc, and the numeral producing ADC exports B
0-B
n-1.
Further, above C
0=C
1, C
i=2C
i-1, i=1 ~ N-2.
Further, the switch arrays be connected with first group of (N-2)-bit binary capacitor array are the first switch arrays, and the first switch arrays are by switch S
0p, S
1p, S
2p... S
(N-2) pcomposition.
Further, the switch arrays be connected with second group of (N-2)-bit binary capacitor array are second switch array, and second switch array is by switch S
0n, S
1n, S
2n... S
(N-2) ncomposition.
The present invention also proposes a kind of logic control method of above-mentioned successive approximation analog to digital C super low-power consumption capacitor array:
(1) in sample phase, switch arrays sequential initialization technique is taked, S
(N-2) n=S
(N-2) p=" 1 ", S
(N-3) n=S
(N-4) n=... S
1n=S
0n=" 0 ", S
(N-3) p=S
(N-4) p=... S
1p=S
0p=" 0 ", according to B
n-1result change S
(N-2)(S
(N-2) nor S
(N-2) p) value, export the control signal S of the larger highest order switch corresponding to capacitor array
(N-2)be connected to " 0 " by " 1 ", and then again compare the size of capacitor array output, produce second-order digit and export B
n-2; " 1 " and " 0 " represents respective switch respectively and the electric capacity corresponding to it is connected to V
refand Gnd;
(2) by adopting top crown sampling and switch arrays logical sequence initialization technique, in the process producing highest order and second-order digit output, benchmark is not needed to provide energy consumption; B is exported in generation the 3rd bit digital
n-3time, if upper saltus step, capacitor array switch controlling signal is become " 11/21/2 ... 1/2 " by " 100 ... 0 ", and energy consumption is-C
n-2v
ref 2/ 2; If lower saltus step, capacitor array switch controlling signal is become " 1/200 ... 0 " by " 100 ... 0 ", and energy consumption is also-C
n-2v
ref 2/ 2; " 1/2 " represents respective switch and the electric capacity corresponding to it is connected to V
cm, V
cm=V
ref/ 2.
Further, in above method, export B in the numeral producing front three
n-1-B
n-3afterwards, in follow-up transfer process, capacitor array takes dull switch logic control mode, only has the change of an electric capacity generation annexation in each clock cycle.
Further, above according to second-order digit output B
n-2difference, the change of the common mode output level of capacitor array presents two kinds of trend:
1) if B
n-2output logic 1, capacitor array needs that upper saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 2;
2) if B
n-2output logic 0, capacitor array needs that lower saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 4.
The present invention has following beneficial effect:
Capacitor array structure provided by the invention has obvious advantage, capacitor array scale and number of switches are only 25% and 38.5% of conventional charge reallocation structure, when not considering parasitic capacitance energy consumption, capacitor array energy consumption is only 1.2% of traditional structure, when considering parasitic capacitance energy consumption, with C
pt=0.1C
tot, C
pb=0.15C is example, and the energy consumption of capacitor array provided by the invention is only 1.4% of conventional charge reallocation structure.
Accompanying drawing explanation
Fig. 1 is conventional charge reallocation type SARADC structure;
Fig. 2 is New type of S ARADC structure of the present invention;
Fig. 3 is 4-bitA/D conversion embodiment of the present invention;
A, the generation that the highest two digits exports,
B, the generation that minimum two digits exports;
Fig. 4 be in the embodiment of the present invention logic control mode to the improvement of converted-wave;
Fig. 5 be in the embodiment of the present invention logic control mode to the improvement of parasitic capacitance power consumption;
Fig. 6 is the energy consumption curve of 10-bit embodiment of the present invention and conventional charge reallocation structure;
Embodiment
First the present invention proposes successive approximation analog to digital C super low-power consumption capacitor array: comprise (N-2)-bit binary capacitor array that two groups are connected to two inputs of comparator, and often group (N-2)-bit binary capacitor array connects voltage reference V by switch arrays
ref, V
cm, Gnd; Often group (N-2)-bit binary capacitor array is by electric capacity C
0, C
1, C
2... C
n-2connect to form, wherein N is natural number; The electric capacity C of first group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
ip, the other end of each electric capacity is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The electric capacity C of second group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
in, the other end is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The output of comparator connects Approach by inchmeal logic control element SARLogic, according to the output of comparator, described Approach by inchmeal logic control element SARLogic realizes the logic control to capacitor array switch under the effect of clock signal clk and soc, and the numeral producing ADC exports B
0-B
n-1.
Wherein above C
0=C
1, C
i=2C
i-1, i=1 ~ N-2.The switch arrays be connected with first group of (N-2)-bit binary capacitor array are the first switch arrays, and the first switch arrays are by switch S
0p, S
1p, S
2p... S
(N-2) pcomposition.The switch arrays be connected with second group of (N-2)-bit binary capacitor array are second switch array, and second switch array is by switch S
0n, S
1n, S
2n... S
(N-2) ncomposition.
Logic control method based on above successive approximation analog to digital C super low-power consumption capacitor array is as follows:
(1) in sample phase, switch arrays sequential initialization technique is taked, S
(N-2) n=S
(N-2) p=" 1 ", S
(N-3) n=S
(N-4) n=... S
1n=S
0n=" 0 ", S
(N-3) p=S
(N-4) p=... S
1p=S
0p=" 0 ", according to B
n-1result change S
(N-2)(S
(N-2) nor S
(N-2) p) value, export the control signal S of the larger highest order switch corresponding to capacitor array
(N-2)be connected to " 0 " by " 1 ", and then again compare the size of capacitor array output, produce second-order digit and export B
n-2; " 1 " and " 0 " represents respective switch respectively and the electric capacity corresponding to it is connected to V
refand Gnd;
(2) by adopting top crown sampling and switch arrays logical sequence initialization technique, in the process producing highest order and second-order digit output, benchmark is not needed to provide energy consumption; B is exported in generation the 3rd bit digital
n-3time, if upper saltus step, capacitor array switch controlling signal is become " 11/21/2 ... 1/2 " by " 100 ... 0 ", and energy consumption is-C
n-2v
ref 2/ 2; If lower saltus step, capacitor array switch controlling signal is become " 1/200 ... 0 " by " 100 ... 0 ", and energy consumption is also-C
n-2v
ref 2/ 2; " 1/2 " represents respective switch and the electric capacity corresponding to it is connected to V
cm, V
cm=V
ref/ 2.
In above method: export B in the numeral producing front three
n-1-B
n-3afterwards, in follow-up transfer process, capacitor array takes dull switch logic control mode, only has the change of an electric capacity generation annexation in each clock cycle.B is exported according to second-order digit
n-2difference, the change of the common mode output level of capacitor array presents two kinds of trend:
1) if B
n-2output logic 1, capacitor array needs that upper saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 2;
2) if B
n-2output logic 0, capacitor array needs that lower saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 4.
Below in conjunction with drawings and Examples, the present invention is described in further detail:
Embodiment
The successive approximation analog to digital C super low-power consumption capacitor array of the present embodiment is as shown in Figure 2: comprise (N-2)-bit binary capacitor array that two groups are connected to two inputs of comparator, and often group (N-2)-bit binary capacitor array connects voltage reference V by switch arrays
ref, V
cm, Gnd; Often group (N-2)-bit binary capacitor array is by electric capacity C
0, C
1, C
2... C
n-2connect to form, wherein N is natural number; The electric capacity C of first group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
ip, the other end of each electric capacity is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The electric capacity C of second group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
in, the other end is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The output of comparator connects Approach by inchmeal logic control element SARLogic, and according to the output of comparator, described SARLogic realizes the logic control to capacitor array switch under the effect of clock signal clk and soc, and the numeral producing ADC exports B
0-B
n-1.。
Wherein C
0=C
1, C
i=2C
i-1, i=1 ~ N-2; Reference voltage V
cm=V
ref/ 2.The switch arrays be connected with first group of (N-2)-bit binary capacitor array are the first switch arrays, and the first switch arrays are by switch S
0p, S
1p, S
2p... S
(N-2) pcomposition.The switch arrays be connected with second group of (N-2)-bit binary capacitor array are second switch array, and second switch array is by switch S
0n, S
1n, S
2n... S
(N-2) ncomposition.
In above-mentioned differential capacitance array structure, take electric capacity top crown to sample, after sampling terminates, compare V by comparator
ipand V
insize directly produce the output B of highest order
n-1, this process does not consume energy consumption, and directly produces after sampling terminates due to highest order, reduces the scale of capacitor array, and then reduces power consumption, chip area and cost.
In above-mentioned differential capacitance array structure, in sample phase, take switch arrays sequential initialization technique, S
(N-2) n=S
(N-2) p=" 1 ", S
(N-3) n=S
(N-4) n=... S
1n=S
0n=" 0 ", S
(N-3) p=S
(N-4) p=... S
1p=S
0p=" 0 ", according to B
n-1result change S
(N-2)(S
(N-2) nor S
(N-2) p) value, export the control signal (S of the larger highest order switch corresponding to capacitor array
(N-2) nor S
(N-2) p) be connected to " 0 " by " 1 ", as shown in Figure 3 a, and then again compare the size of capacitor array output, produce second-order digit and export B
n-2, this process does not also consume energy consumption.
In above-mentioned capacitor array structure, by adopting top crown sampling and switch arrays logical sequence initialization technique, in the process producing highest order and second-order digit output, benchmark is not needed to provide energy consumption.In addition, B is exported in generation the 3rd bit digital
n-3time, if upper saltus step (up-transition), capacitor array switch controlling signal is become " 11/21/2 ... 1/2 " by " 100 ... 0 ", and energy consumption is-C
n-2v
ref 2/ 2; If lower saltus step (down-transition), capacitor array switch controlling signal is become " 1/200 ... 0 " by " 100 ... 0 ", and energy consumption is also-C
n-2v
ref 2/ 2.By adopting this new logic control mode, the 3rd bit digital exports B
n-3generation do not need benchmark to provide energy consumption yet.Fig. 3 gives the concrete transfer process of 4-bit embodiment of the present invention and corresponding energy loss.
In above-mentioned capacitor array structure, export (B in the numeral producing front three
n-1-B
n-3) after, in follow-up transfer process, capacitor array takes dull switch logic control mode, only has the change of an electric capacity generation annexation, not only simplify logic-controlled sequential, also reduce power consumption in each clock cycle.
In above-mentioned capacitor array structure, export B according to second-order digit
n-2difference, the change of the common mode output level of capacitor array presents two kinds of trend: 1) if B
n-2for logical one, capacitor array needs that upper saltus step (as shown in A and D in Fig. 3) occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 2; 2) if B
n-2for logical zero, capacitor array needs that lower saltus step (as shown in B and C in Fig. 3) occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 4.Fig. 4 compares the capacitor array output waveform of 4-bit embodiment of the present invention and the dull switch mode of tradition, compare traditional dull switch mode, the common mode of capacitor array provided by the invention exports (that is: the common mode input of comparator) level excursion and significantly reduces, can effectively reduce because comparator common mode electrical level changes the input offset error caused, be beneficial to the Low Power Optimization of comparator.
In above-mentioned capacitor array structure, the new logic control mode taked can effectively reduce the extra power consumption caused by parasitic capacitance, and Fig. 5 gives the schematic diagram of 4-bit inventive embodiments.All there is parasitic capacitance between the upper bottom crown of electric capacity and substrate (" 0 "), wherein, the parasitic capacitance between bottom crown and substrate is directly connected with benchmark by switch, in electric capacity handoff procedure, the discharge and recharge of parasitic capacitance can consume extra energy, wherein, and highest order electric capacity C
n-2weight is maximum, and the power consumption of its parasitic capacitance at most, by optimizing the logical sequence of capacitor array switch, under the prerequisite not increasing logical complexity, ensure that in whole A/D transfer process, highest order electric capacity C
n-2only there is dull lower saltus step (" 1 " → " 0 " or " 1 " → " 1/2 "), avoid its parasitic capacitance (2C
pb) recharge, thus effectively reduce the power consumption of parasitic capacitance.
In the conventional charge reallocation type SARADC structure shown in Fig. 1, electric capacity bottom crown is taked to sample and traditional Approach by inchmeal mode, C
0, C
1, C
2... C
n-1composition binary capacitor array, C
0=C
1, C
i=2C
i-1, i=1 ~ N-1; S
ip, S
in(i=0 ~ N-1) is capacitor array switch; V
ipand V
infor differential input signal; V
reffor voltage reference.Whole capacitor array is not only larger, and area, power consumption and process costs are higher, and large-scale capacitor array causes the input capacitance of SARADC comparatively large, causes overall work limited speed.
The comparison (10-bitADC) of table 1 the present invention and conventional charge reallocation structure
For 10-bitADC in upper table, in capacitor array scale, number of switches and capacitor array energy consumption, the present invention and conventional charge reallocation structure are compared, wherein, C
ptrepresent the parasitic capacitance sum of the top crown of whole capacitor array to substrate, C
pbthe bottom crown of representation unit electric capacity to the parasitic capacitance of substrate, C
totrepresent the total capacitance value of whole capacitor array.Capacitor array structure provided by the invention has obvious advantage, capacitor array scale and number of switches are only 25% and 38.5% of conventional charge reallocation structure, when not considering parasitic capacitance energy consumption, capacitor array energy consumption is only 1.2% of traditional structure, when considering parasitic capacitance energy consumption, with C
pt=0.1C
tot, C
pb=0.15C is example, and the energy consumption of capacitor array provided by the invention is only 1.4% of conventional charge reallocation structure.Specifically can see Fig. 6.
Claims (7)
1. a successive approximation analog to digital C super low-power consumption capacitor array, it is characterized in that, comprise (N-2)-bit binary capacitor array that two groups are connected to two inputs of comparator, often group (N-2)-bit binary capacitor array connects voltage reference V by switch arrays
ref, V
cm, Gnd; Often group (N-2)-bit binary capacitor array is by electric capacity C
0, C
1, C
2... C
n-2connect to form, wherein N is natural number; The electric capacity C of first group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
ip, the other end of each electric capacity is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The electric capacity C of second group of (N-2)-bit binary capacitor array
0, C
1, C
2... C
n-2one end connect differential input signal V respectively
in, the other end is connected to voltage reference V respectively by the switch in switch arrays
ref, V
cm, Gnd; The output of comparator connects Approach by inchmeal logic control element SARLogic, according to the output of comparator, described Approach by inchmeal logic control element SARLogic realizes the logic control to capacitor array switch under the effect of clock signal clk and soc, and the numeral producing ADC exports B
0-B
n-1.
2. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, C
0=C
1, C
i=2C
i-1, i=1 ~ N-2.
3. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, the switch arrays be connected with first group of (N-2)-bit binary capacitor array are the first switch arrays, and the first switch arrays are by switch S
0p, S
1p, S
2p... S
(N-2) pcomposition.
4. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, the switch arrays be connected with second group of (N-2)-bit binary capacitor array are second switch array, and second switch array is by switch S
0n, S
1n, S
2n... S
(N-2) ncomposition.
5. a logic control method for successive approximation analog to digital C super low-power consumption capacitor array described in claim 1-4 any one, is characterized in that:
(1) in sample phase, switch arrays sequential initialization technique is taked, S
(N-2) n=S
(N-2) p=" 1 ", S
(N-3) n=S
(N-4) n=... S
1n=S
0n=" 0 ", S
(N-3) p=S
(N-4) p=... S
1p=S
0p=" 0 ", according to B
n-1result change S
(N-2)(S
(N-2) nor S
(N-2) p) value, export the control signal S of the larger highest order switch corresponding to capacitor array
(N-2)be connected to " 0 " by " 1 ", and then again compare the size of capacitor array output, produce second-order digit and export B
n-2; " 1 " and " 0 " represents respective switch respectively and the electric capacity corresponding to it is connected to V
refand Gnd;
(2) by adopting top crown sampling and switch arrays logical sequence initialization technique, in the process producing highest order and second-order digit output, benchmark is not needed to provide energy consumption; B is exported in generation the 3rd bit digital
n-3time, if upper saltus step, capacitor array switch controlling signal is become " 11/21/2 ... 1/2 " by " 100 ... 0 ", and energy consumption is-C
n-2v
ref 2/ 2; If lower saltus step, capacitor array switch controlling signal is become " 1/200 ... 0 " by " 100 ... 0 ", and energy consumption is also-C
n-2v
ref 2/ 2; " 1/2 " represents respective switch and the electric capacity corresponding to it is connected to V
cm, V
cm=V
ref/ 2.
6. logic control method according to claim 5, is characterized in that, exports B in the numeral producing front three
n-1-B
n-3afterwards, in follow-up transfer process, capacitor array takes dull switch logic control mode, only has the change of an electric capacity generation annexation in each clock cycle.
7. logic control method according to claim 5, is characterized in that, exports B according to second-order digit
n-2difference, the change of the common mode output level of capacitor array presents two kinds of trend:
1) if B
n-2output logic 1, capacitor array needs that upper saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 2;
2) if B
n-2output logic 0, capacitor array needs that lower saltus step occurs and exports B to produce the 3rd
n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process
ref/ 4.
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| CN107968656B (en) * | 2016-10-20 | 2021-08-20 | 国民技术股份有限公司 | Successive approximation type analog-digital converter and application switching method thereof |
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| CN106549669A (en) * | 2016-12-06 | 2017-03-29 | 南京邮电大学 | A kind of analog-digital converter based on monotonicity capacitance switch |
| CN106685420A (en) * | 2016-12-15 | 2017-05-17 | 西安邮电大学 | Low-power and high-linearity switching method for successive approximation register (SAR) ADC capacitor array |
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| CN108649956A (en) * | 2018-05-15 | 2018-10-12 | 西安电子科技大学 | A kind of gradual approaching A/D converter based on asymmetric differential capacitance array |
| CN112039528A (en) * | 2020-07-22 | 2020-12-04 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN112039528B (en) * | 2020-07-22 | 2022-11-29 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
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