CN103166644B - A kind of low-power consumption gradual approaching A/D converter and conversion method thereof - Google Patents

Abstract

The invention discloses a kind of low-power consumption gradual approaching A/D converter and conversion method thereof, its switched capacitor network comprises the electric capacity pair of few one of specific output binary coding quantity, by completely newly arranging the sequential of switch and introduce common mode electrical level Vcm in comparison procedure, eliminate the building-out capacitor in conventional successive approach type analog to digital converter switched capacitor network, reach N-1 electric capacity to realizing the effect that resolution is N position, lacked highest order and time high-order two electric capacity pair by comparatively conventional successive approach type analog to digital converter, whole total capacitance also reduces by 75%.Along with the reduction of electric capacity, charging and discharging currents is corresponding reduction also, thus reduces overall power, and decreases chip area, improves economic benefit.In transfer process, the common-mode voltage variation amount of comparator input terminal, compared with traditional structure, is only , common mode shake is very little.

Description

A kind of low-power consumption gradual approaching A/D converter and conversion method thereof

Technical field

The invention belongs to technical field of integrated circuits, particularly a kind of gradual approaching A/D converter and conversion method thereof.

Background technology

Gradual approaching A/D converter is the analog-digital converter structure of a kind of middle high accuracy, moderate rate, super low-power consumption.For the application such as wireless sense network, portable set, analog to digital converter is required can work at low supply voltages.But along with the reduction of supply voltage, the gain of circuit is restricted, and the structure of gradual approaching A/D converter only includes comparator, digital to analog converter and successive approximation register, does not need the circuit providing gain.The power consumption of digital circuit constantly can reduce along with process reduction ratio, and the power consumption of analog circuit is difficult to synchronously reduce along with the progress of technique.Capacitor type gradual approaching A/D converter is under high definition case, and need to use bulky capacitor, not only discharge and recharge power consumption is large, and makes bulky capacitor waste chip area, and economic benefit is not high.

Summary of the invention

Goal of the invention: propose a kind of low-power consumption gradual approaching A/D converter and conversion method thereof, when equal accuracy, capacitance comparatively traditional scheme reduces 75%, reduces power consumption.

Technical scheme: a kind of low-power consumption gradual approaching A/D converter, comprises comparator and switched capacitor network; Described switched capacitor network comprises the positive capacitance network connecting described comparator normal phase input end and the inverted capacitance network being connected described comparator inverting input; Described positive capacitance network and inverted capacitance network comprise N-1 the electric capacity of few one of the binary coding figure place N exported than analog to digital converter respectively.

Wherein, the electric capacity top crown of described positive capacitance network is selected to connect positive input voltage Vin, common mode electrical level Vcm, low level VL, high level VH respectively by switch; The electric capacity bottom crown of described positive capacitance network is coupled the normal phase input end that is connected to described comparator connect common mode electrical level Vcm by positive switch; The electric capacity top crown of described inverted capacitance network is selected to connect reverse inter-input-ing voltage Vip, common mode electrical level Vcm, low level VL, high level VH respectively by switch; The electric capacity bottom crown of described inverted capacitance network is coupled the inverting input that is connected to described comparator connect common mode electrical level Vcm by anti-phase opening.

Wherein, the first electric capacity C of described positive capacitance network ₁capacitance is C, and second is C to the capacitance of N-1 electric capacity _i=2 ^i-2c, wherein, i is the natural number of 2≤i≤N-1; First electric capacity C of described inverted capacitance network ₁capacitance is C, and second is C to the capacitance of N-1 electric capacity _i=2 ^i-2c, wherein, i is the natural number of 2≤i≤N-1.

Based on a D conversion method for above-mentioned low-power consumption gradual approaching A/D converter, it is characterized in that: its transfer process comprises the steps:

Sample phase:

In switched capacitor network, the bottom crown of all electric capacity connects common mode electrical level Vcm, and the top crown of all electric capacity of positive capacitance network be connected with comparator normal phase input end connects positive input voltage Vin; The top crown of all electric capacity of inverted capacitance network be connected with comparator inverting input connects reverse inter-input-ing voltage Vip;

The AD conversion cycle:

First, the bottom crown of all electric capacity of switched capacitor network disconnects the connection with common mode electrical level Vcm; The top crown of all electric capacity of positive capacitance network be connected with comparator normal phase input end connects common mode electrical level Vcm; The top crown of all electric capacity of inverted capacitance network be connected with comparator inverting input connects common mode electrical level Vcm; After switched capacitor network carries out electric charge distribution again; Comparator compares normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size and outputs results to control circuit; If Vxp > Vxn, i.e. V _ip-V _in> 0, then control circuit is by binary coding extreme higher position 1, if Vxp is less than Vxn, i.e. V _ip-V _in< 0, then control circuit is by binary coding extreme higher position 0;

According to the signal value that comparator exports, the highest order capacitance switch controlling positive capacitance network and inverted capacitance network respectively by control circuit meets low level VL or high level VH or maintained switch is failure to actuate, and switched capacitor network starts electric charge distribution again;

After switched capacitor network electric charge distribution again completes, comparator outputs signal to control circuit after comparing normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size, and control circuit is by binary coding time high position 1 or set to 0;

Successively compare down successively, until binary code extreme lower position 1 or after setting to 0, in this binary code write control circuit register, complete analog-to-digital conversion.

Beneficial effect: the switched capacitor network in the present invention comprises the electric capacity pair of few one of specific output binary coding quantity, by completely newly arranging the sequential of switch and introduce common mode electrical level Vcm in comparison procedure, eliminate the building-out capacitor in conventional successive approach type analog to digital converter switched capacitor network, reach N-1 electric capacity to realizing the effect that resolution is N position, lacked highest order and time high-order two electric capacity pair by comparatively conventional successive approach type analog to digital converter, whole total capacitance also reduces by 75%.Along with the reduction of electric capacity, charging and discharging currents is corresponding reduction also, thus reduces overall power, and decreases chip area, improves economic benefit.In transfer process, the common-mode voltage variation amount of comparator input terminal, compared with traditional structure, is only wherein N is analog-digital bit, V _ref=VH-VL, common mode shake is very little.

Accompanying drawing explanation

Fig. 1 is the circuit structure diagram of low-power consumption gradual approaching A/D converter of the present invention;

Fig. 2 is low-power consumption gradual approaching A/D converter of the present invention first three switch transition fundamental diagram;

Fig. 3 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [V _ref, V _ref/ 2] the 4th switch transition fundamental diagram;

Fig. 4 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [V _ref/ 2,0] the 4th switch transition fundamental diagram;

Fig. 5 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [0 ,-V _ref/ 2] the 4th switch transition fundamental diagram;

Fig. 6 is that low-power consumption gradual approaching A/D converter of the present invention is at input reference signal [-V _ref/ 2 ,-V _ref] the 4th switch transition fundamental diagram;

Fig. 7 is the working timing figure of low-power consumption gradual approaching A/D converter of the present invention.

Embodiment

Below in conjunction with accompanying drawing the present invention done and further explain.

As shown in Figure 1, the present embodiment is that one 4 the low-power consumption gradual approaching A/D converters exported comprise control circuit, comparator and switched capacitor network.Wherein switched capacitor network comprises the positive capacitance network being connected to comparator normal phase input end, and is connected to the inverted capacitance network of comparator inverting input.In positive capacitance network, have the electric capacity of the few number of specific output binary coding figure place, this example is 4 and exports B4B3B2B1, namely has 3 electric capacity, is followed successively by the first electric capacity C1 to the 3rd electric capacity C3 from lowest order to highest order.The common port of the first electric capacity C1 to the 3rd electric capacity C3 is connected to the normal phase input end of comparator jointly, and be connected to common mode electrical level Vcm by K switch p, the other end respectively by the first K switch 1 to the 3rd K switch 3 selectable connection input signal Vin, low level VL, high level VH or common mode electrical level Vcm.First electric capacity C1 capacitance is C, and the capacitance of other electric capacity is C _i=2 ^i-2c, (i=2,3).The pulse signal that all switches export by control circuit controls.In inverted capacitance network, there is the electric capacity of number identical with positive network, be followed successively by the 4th electric capacity C12, the 5th electric capacity C22, the 6th electric capacity C32 from lowest order to highest order.The common port of the 4th electric capacity C12, the 5th electric capacity C22, the 6th electric capacity C32 is connected to the inverting input of comparator jointly, and being connected to common mode electrical level Vcm by K switch n, the other end is respectively by the 4th K switch 12, the 5th K switch 22, the 6th K switch 32, selectable connection input signal Vip, low level VL, high level VH or common mode electrical level Vcm.4th electric capacity C12 capacitance is C, and the capacitance of other electric capacity is C _i2=2 ^i-2c, (i=2,3).Anti-phase network configuration is identical with positive network configuration.

As shown in Fig. 2 (A), sample phase, closed under the driving of positive network breaker in middle Kp at control circuit, the public termination common mode electrical level Vcm of the first electric capacity C1 to the 3rd electric capacity C3, first K switch 1 is closed under control circuit drives to the 3rd K switch 3 simultaneously, meet input signal Vin, to the capacitor charging of positive network; Closed under the driving of anti-phase network breaker in middle Kn at control circuit, the public termination common mode electrical level Vcm of the 4th electric capacity C12, the 5th electric capacity C22, the 6th electric capacity C32,4th K switch 12, the 5th K switch 22, the 6th K switch 32 are closed under control circuit drives simultaneously, meet input signal Vip, to the capacitor charging of anti-phase network.In now stored quantity of electric charge positive network be: Q _p=(V _cm-V _in) × 4C; In anti-phase network be: Q _n=(V _cm-V _ip) × 4C.

As shown in Fig. 2 (B), in comparison phase, positive K switch p and phase-veversal switch Kn all disconnects, in positive network, in the first K switch 1 to the 3rd K switch 3 and anti-phase network, the 4th K switch 12, the 5th K switch 22, the 6th K switch 32 meet common mode electrical level Vcm under control circuit drives simultaneously, in positive network and anti-phase network, the quantity of electric charge remains unchanged, electric charge carries out code reassignment, i.e. Q _xp=Q _p, Q _xn=Q _n, have:

Q _xp＝(V _xp-V _cm)×4C＝Q _p

Q _xn＝(V _xn-V _cm)×4C＝Q _n

Note $V_{\mathrm{ref}}=V_H-V_L,V_{\mathrm{cm}}=\frac{1}{2}(V_H+V_L),$ Then V _xp=2V _cm-V _in, V _xn=2V _cm-V _ip.

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, i.e. V _ip-V _in> 0, be then set to 1 by binary coding highest order B4; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, i.e. V _ip-V _in< 0, be then set to 0 by binary coding highest order B4.

(1) be the situation of 1 for B4:

When highest order B4 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the 3rd electric capacity C3 in positive network is made to be connected to low level VL by the 3rd K switch 3, the one end of the 6th electric capacity C32 in anti-phase network is connected to high level VH by the 6th K switch 32, as shown in Fig. 2 (C1).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _cm)×2C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding time high-order B3 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding time high-order B3 is set to 0.

Be the situation of 11 for B4B3:

When secondary high-order B3 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the second electric capacity C2 in positive network is made to be connected to low level VL by second switch K2, the one end of the 5th electric capacity C22 in anti-phase network is connected to high level VH by the 5th K switch 22, as shown in Fig. 2 (D1).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 0.

When B2 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the first electric capacity C1 in positive network be connected to low level VL by the first K switch 1, anti-phase network is constant, as shown in Fig. 3 (E1).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×4C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{2}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

When B2 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the 4th electric capacity C12 in anti-phase network be connected to low level VL by the 4th K switch 12, positive network is constant, as shown in Fig. 3 (E2).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×3C+(V _xn-V _L)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

Be the situation of 10 for B4B3:

When secondary high-order B3 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the second electric capacity C2 in positive network is made to be connected to high level VH by second switch K2, the one end of the 5th electric capacity C22 in anti-phase network is connected to low level VL by the 5th K switch 22, as shown in Fig. 2 (D2).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 0.

When B2 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the first electric capacity C1 in positive network be connected to low level VL by the first K switch 1, anti-phase network is constant, as shown in Fig. 4 (E3).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×3C+(V _xp-V _H)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×C+(V _xn-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

When B2 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the 4th electric capacity C12 in anti-phase network be connected to low level VL by the 4th K switch 12, positive network is constant, as shown in Fig. 4 (E4).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×2C+(V _xn-V _L)×2C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ V _xn＝2V _cm-V _ip。

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

(2) be the situation of 0 for B4:

When highest order B4 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the 3rd electric capacity C3 in positive network is made to be connected to high level VH by the 3rd K switch 3, the one end of the 6th electric capacity C32 in anti-phase network is connected to low level VL by the 6th K switch 32, as shown in Fig. 2 (C2).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _H)×2C+(V _xp-V _cm)×2C＝Q _p

Q _xn＝(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding time high-order B3 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding time high-order B3 is set to 0.

Be the situation of 01 for B4B3:

When secondary high-order B3 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the second electric capacity C2 in positive network is made to be connected to low level VL by second switch K2, the one end of the 5th electric capacity C22 in anti-phase network is connected to high level VH by the 5th K switch 22, as shown in Fig. 2 (D3).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×C+(V _xp-V _H)×2C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 0.

When B2 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the first electric capacity C1 in positive network be connected to low level VL by the first K switch 1, anti-phase network is constant, as shown in Fig. 5 (E5).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×2C+(V _xp-V _H)×2C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×2C+(V _xn-V _cm)×2C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: V _xp=2V _cm-V _in, $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

When B2 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the 4th electric capacity C12 in anti-phase network be connected to low level VL by the 4th K switch 12, positive network is constant, as shown in Fig. 5 (E6).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _L)×C+(V _xp-V _H)×2C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _H)×C+(V _xn-V _L)×3C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

Be the situation of 00 for B4B3:

When secondary high-order B3 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, the one end of the second electric capacity C2 in positive network is made to be connected to high level VH by second switch K2, the one end of the 5th electric capacity C22 in anti-phase network is connected to low level VL by the 5th K switch 22, as shown in Fig. 2 (D4).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _L)×3C+(V _xp-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then by binary coding again high-order B2 be set to 0.

When B2 is set to 1, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the first electric capacity C1 in positive network be connected to low level VL by the first K switch 1, anti-phase network is constant, as shown in Fig. 6 (E7).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _L)×C＝Q _p

Q _xn＝(V _xn-V _L)×3C+(V _xp-V _cm)×C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{1}{4}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.

When B2 is set to 0, control circuit produces corresponding control signal according to the Output rusults of comparator, and make the one end of the 4th electric capacity C12 in anti-phase network be connected to low level VL by the 4th K switch 12, positive network is constant, as shown in Fig. 6 (E8).Now due to the change of voltage, can there is code reassignment in the electric charge in positive network and anti-phase network on electric capacity, thus cause comparator normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn to change.According to principle of charge conservation, the quantity of electric charge stored by sample phase should remain unchanged, thus obtains following equation:

Q _xp＝(V _xp-V _H)×3C+(V _xp-V _cm)×C＝Q _p

Q _xn＝(V _xn-V _L)×4C＝Q _n

Above-mentioned two formulas of abbreviation can obtain: $V_{\mathrm{xp}}=2V_{\mathrm{cm}}+\frac{3}{8}{V}_{\mathrm{ref}}-V_{\mathrm{in}},$ $V_{\mathrm{xn}}=2V_{\mathrm{cm}}-\frac{1}{2}{V}_{\mathrm{ref}}-V_{\mathrm{ip}}.$

Now normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn compares by comparator, and result is outputted to control circuit.If normal phase input end voltage Vxp is greater than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 1; If normal phase input end voltage Vxp is less than anti-phase input terminal voltage Vxn, namely then binary coding lowest order B1 is set to 0.Finally, in this tetrad code write control circuit register, analog-to-digital conversion is completed.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (3)

1. a low-power consumption gradual approaching A/D converter, comprises comparator and switched capacitor network; Described switched capacitor network comprises the positive capacitance network connecting described comparator normal phase input end and the inverted capacitance network being connected described comparator inverting input; It is characterized in that: described positive capacitance network and inverted capacitance network comprise N-1 the electric capacity of few one of the binary coding figure place N exported than analog to digital converter respectively; The electric capacity top crown of described positive capacitance network is selected to connect positive input voltage Vin, common mode electrical level Vcm, low level VL, high level VH respectively by switch; The electric capacity bottom crown of described positive capacitance network is coupled the normal phase input end that is connected to described comparator connect common mode electrical level Vcm by positive switch; The electric capacity top crown of described inverted capacitance network is selected to connect reverse inter-input-ing voltage Vip, common mode electrical level Vcm, low level VL, high level VH respectively by switch; The electric capacity bottom crown of described inverted capacitance network is coupled the inverting input that is connected to described comparator connect common mode electrical level Vcm by phase-veversal switch.

2. a kind of low-power consumption gradual approaching A/D converter according to claim 1, is characterized in that: the first electric capacity C of described positive capacitance network ₁capacitance is C, and second is C to the capacitance of N-1 electric capacity _i=2 ^i-2c, wherein, i is the natural number of 2≤i≤N-1; First electric capacity C of described inverted capacitance network ₁capacitance is C, and second is C to the capacitance of N-1 electric capacity _i=2 ^i-2c, wherein, i is the natural number of 2≤i≤N-1.

3. based on a D conversion method for low-power consumption gradual approaching A/D converter described in claim 1, it is characterized in that: its transfer process comprises the steps:

Sample phase:

In switched capacitor network, the bottom crown of all electric capacity connects common mode electrical level Vcm, and the top crown of all electric capacity of positive capacitance network be connected with comparator normal phase input end connects positive input voltage Vin; The top crown of all electric capacity of inverted capacitance network be connected with comparator inverting input connects end of oppisite phase input voltage Vip;

The AD conversion cycle:

First, the bottom crown of all electric capacity of switched capacitor network disconnects the connection with common mode electrical level Vcm; The top crown of all electric capacity of positive capacitance network be connected with comparator normal phase input end connects common mode electrical level Vcm; The top crown of all electric capacity of inverted capacitance network be connected with comparator inverting input connects common mode electrical level Vcm; After switched capacitor network carries out electric charge distribution again; Comparator compares normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size and outputs results to control circuit; V _xp=2V _cm-V _in, V _xn=2V _cm-V _ipif, Vxp > Vxn, i.e. V _ip-V _in> 0, then control circuit is by binary coding extreme higher position 1, if Vxp is less than Vxn, i.e. V _ip-V _in< 0, then control circuit is by binary coding extreme higher position 0;

According to the signal value that comparator exports, the highest order capacitance switch controlling positive capacitance network and inverted capacitance network respectively by control circuit meets low level VL or high level VH or maintained switch is failure to actuate, and switched capacitor network starts electric charge distribution again;

After switched capacitor network electric charge distribution again completes, comparator outputs signal to control circuit after comparing normal phase input end voltage Vxp and anti-phase input terminal voltage Vxn size, and control circuit is by binary coding time high position 1 or set to 0;

Successively compare down successively, until binary code extreme lower position 1 or after setting to 0, in this binary code write control circuit register, complete analog-to-digital conversion.