CN104579348A

CN104579348A - Successive approximation type ADC structure and algorithm

Info

Publication number: CN104579348A
Application number: CN201510018681.9A
Authority: CN
Inventors: 李振海; 范涛
Original assignee: BEIJING TEEAPOGEE MICROELECTRONIC Co Ltd
Current assignee: BEIJING TEEAPOGEE MICROELECTRONIC Co Ltd
Priority date: 2015-01-15
Filing date: 2015-01-15
Publication date: 2015-04-29

Abstract

The invention discloses a successive approximation type ADC structure and an algorithm. An ADC involved in the successive approximation type ADC structure is a segment capacitor type electric charge redistribution successive approximation type ADC. Main modules include the novel segment capacitor type DAC, a comparator and successive approximation logic, wherein the novel segment capacitor type DAC is the structure core of the successive approximation type ADC structure, and the intersegmental difference to single-end algorithm matched with the segment capacitor type DAC is synthesized into the successive approximation logic. According to the successive approximation type ADC, the segment capacitor type DAC of a differential structure is adopted, the intersegmental difference to single-end technology is utilized, and the effect of obtaining an (N+1)-bit ADC resolution ratio with an N-bit ADC basis structure is achieved; meanwhile, the influence of parasitic capacitance on the linearity of the segment capacitor type DAC is greatly reduced, and the performance of the ADC is improved.

Description

A kind of SAR ADC structure and algorithm

Technical field

The invention belongs to the analog to digital converter field of integrated circuit, particularly relate to a kind of structure and algorithm of novel SAR ADC.

Background technology

SAR ADC (Analog to Digital Converter, analog to digital converter) is a kind of analog to digital converter that can provide higher conversion speed and high-resolution, and it possesses low in energy consumption, the advantage that area is little, therefore uses also more and more extensive.

The employing of SAR ADC is Charge scaling formula structure the most widely, Charge scaling formula DAC(Digital to Analog Converter, digital to analog converter) be its core circuit, its basic structure is the capacitor array with binary weights.General when ADC resolution is greater than 8, the mode of segmentation can be adopted to reduce the area of electric capacity, and Fig. 1 illustrates one more typical sectional capacitor type successive approximation analog to digital C.The ADC of this structure has an obvious irrational factors, and the top crown parasitic capacitance of sectional capacitance Cs can be introduced non-linear, thus affects the performance of ADC.。

Summary of the invention

The invention discloses a kind of successive approximation analog to digital C, main modular comprises novel sectional capacitor type DAC, comparator and Approach by inchmeal logic.Wherein novel sectional capacitor type DAC is structural core of the present invention, and contain algorithm core of the present invention in Approach by inchmeal logic, intersegmental difference turns single-ended algorithm.

Further, described SAR ADC, the novel sectional capacitor type DAC of employing has the basic structure of N position, but achieves the resolution of N+1 position.An extra bit resolution utilizes described intersegmental difference to turn single-ended algorithm to realize.

Further, described novel sectional capacitor type DAC has differential configuration, the segmented mode of DAC is (L+1)+M(wherein N=L+M, L is low weight segmentation, M is high weight segmentation), L position and M position are all realized by binary weights electric capacity, define the DAC of N position basic structure, and extra 1 turns single-ended method by difference and realizes.The data bit of DAC is followed successively by from low to high according to weight: 1,2 ... L, L+1 ... L+1+M, altogether L+1+M position.

Further, the 1 to the L+1 position of described novel sectional capacitor type DAC adopts single-ended working method, and L+2 to L+1+M position adopts the working method of difference.1 to the L position of DAC, forms binary weights relation by the binary weights electric capacity of correspondence; From L to L+1 position, form binary weights relation by sectional capacitance Cs; From L+1 to L+2 position, form binary weights relation by the conversion of single-ended-to-difference; From L+2 to L+1+M position, form binary weights relation by the binary weights electric capacity of correspondence equally.Thus described novel sectional capacitor type DAC, with the basic structure of N position binary capacitor, achieves the resolution of N+1 position.

Further, relative to the sectional capacitor type DAC of ordinary construction, the sectional capacitor type DAC of new structure only increases two specific capacitances, can not affect the area of DAC.Difference turns single-ended algorithm and makes the L position weight on the low limit of sectional capacitance Cs decline one, thus makes the family planning electric capacity of sectional capacitance Cs top crown reduce half, substantially improves the linearity of DAC, improves the performance of ADC.

Further, described difference turns that single-ended algorithm is directly comprehensive in described Approach by inchmeal logic, and Approach by inchmeal logic is to the control signal of novel sectional capacitor type DAC, and its L+1 position, low limit is single-ended control, and flash M position is that difference controls.In general, Approach by inchmeal logic not only provides classical binary search algorithm, and provides difference of the present invention and turn single-ended algorithm, and control ADC completes transfer process.

Accompanying drawing explanation

Fig. 1 is common sectional capacitor type successive approximation analog to digital C-structure;

Fig. 2 is novel sectional capacitor type successive approximation analog to digital C-structure of the present invention;

Fig. 3 is the voltage swing schematic diagram of common sectional capacitor type DAC output;

Fig. 4 is the voltage swing schematic diagram of novel sectional capacitor type DAC output of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.

As shown in Figure 2, main modular comprises novel sectional capacitor type DAC to SAR ADC structure of the present invention, comparator and Approach by inchmeal logic.Wherein novel difference sectional capacitor type DAC is structural core of the present invention, and contain algorithm core of the present invention in Approach by inchmeal logic, intersegmental difference turns single hop algorithm.

SAR ADC of the present invention is the modified model of classical SAR ADC, and the introduction of its specific implementation method needs from the SAR ADC introduction of classics.The difference SAR ADC structure of classical architecture as shown in Figure 2.

The difference SAR ADC of classical architecture, its nucleus module DAC is mainly made up of binary weights capacitor array, sectional capacitance Cs is divided into two parts capacitor array, wherein the capacitance size of L position, low limit is followed successively by from low level to a high position: C, 2C, 2 (L-2) C, the capacitance size of 2 (L-1) C (1) flash M position is followed successively by from low level to a high position: C, 2C, the size of 2 (M-2) C, 2 (M-1) C (2) sectional capacitance Cs is unit electric capacity C.

Fig. 3 illustrates the amplitude of oscillation of the DAC output node voltage of classical architecture difference SAR ADC, output voltage and numerically controlled corresponding relation are followed successively by: VL ... (3) VL+1 ... (4) VL+2 ... (5) by the requirement of binary relationship, voltage swing meets following requirement:

VL+1=2 VL ，VL+2=2 VL+1 (6)

The size of specific capacitance C is required determined by the coupling of electric capacity, is ADC to L+M, the coupling requirement of highest order electric capacity 2 (M-1) C demand fulfillment L+M position ADC, thus can determine the size of specific capacitance C.

There is an inherent shortcoming in segmentation Charge scaling formula ADC, namely the top crown family planning electric capacity of sectional capacitance Cs can be introduced non-linear, causes the differential nonlinearity (DNL) of ADC and the decline of integral nonlinearity (INL).This parasitic capacitance is generally made up of the cabling parasitism that parasitizes of electric capacity self, and parasitic capacitance is relevant with the normalized value of parasitic capacitance to specific capacitance on the impact of the ADC linearity, and normalized value is larger, also larger on the impact of the ADC linearity.

The successive approximation analog to digital C of novel successive approximation analog to digital C of the present invention to classical architecture improves.

Sectional capacitance Cs is divided into two parts capacitor array, wherein the capacitance size of L position, low limit is followed successively by from low level to a high position: C, 2C, 2 (L-2) C, the capacitance size of 2 (L-1) C (7) flash 1+M position is followed successively by from low level to a high position: C, C, 2C, the size of 2 (M-2) C, 2 (M-1) C (8) sectional capacitance Cs is unit electric capacity C.

With classical architecture difference successive approximation analog to digital C unlike, flash adds one and becomes 1+M position, and the L position on base and flash 1 of increasing adopts single-ended control, and namely the half control code of difference channel is fixed.As shown in Figure 4, output voltage and numerically controlled corresponding relation are followed successively by the corresponding DAC output end voltage amplitude of oscillation:

VL … (9)

VL+1 … (10)

VL+2 … (11)

Voltage swing meets binary relationship equally

VL+1=2 VL ，VL+2=2 VL+1 (12)

Can be found by contrast, the L position amplitude of oscillation on the low limit of sectional capacitance Cs diminishes half, and the impact of the parasitic capacitance of such electric capacity Cs top crown it also reduces half.

The general effect of novel successive approximation analog to digital C of the present invention is exactly on the basis of simple adjustment L+M position ADC structure, achieves the resolution of L+1+M position, reduces the impact of parasitic capacitance on the ADC linearity simultaneously, improve the performance of ADC.

Finally should be noted that: above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although with reference to above-described embodiment to invention has been detailed description, those of ordinary skill in the field are to be understood that: still can modify to the specific embodiment of the present invention or equivalent replacement, and not departing from any amendment of spirit and scope of the invention or equivalent replacement, it all should be encompassed in the middle of right of the present invention.

Claims

1. the structure of SAR ADC and an algorithm, it is characterized in that, described ADC comprises novel sectional capacitor type DAC, comparator and Approach by inchmeal logic.

2. wherein novel sectional capacitor type DAC is structural core of the present invention, contains algorithm core of the present invention in Approach by inchmeal logic.

3. novel sectional capacitor type DAC according to claim 1, is characterized in that, described DAC is the sectional capacitor type Charge scaling DAC of differential configuration, and it has the basic structure of N position DAC, but can realize the resolution that N+1 is DAC.

4. Approach by inchmeal logic according to claim 1, it is characterized in that, this Approach by inchmeal logic not only can comprise the binary search algorithm of all SAR ADC, also comprises the intersegmental difference wanted required for the present invention and turns single-ended algorithm.

5. the structure of SAR ADC according to claim 1 and algorithm, it is characterized in that, described novel sectional capacitor type DAC and described intersegmental difference turn single-ended algorithm and to cooperatively interact work, the effect realizing N+1 position ADC resolution with the basic structure of N position ADC can be reached, substantially reduce the impact of parasitic capacitance on the sectional capacitor type DAC linearity, the performance of ADC is improved simultaneously.