CN105375925B - The capacitive gradually-appoximant analog-digital converter of pseudo-differential - Google Patents
The capacitive gradually-appoximant analog-digital converter of pseudo-differential Download PDFInfo
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Abstract
The invention discloses a kind of capacitive gradually-appoximant analog-digital converters of pseudo-differential, including first and two capacitor arrays, calibration capacitance array and comparator, the low level cross-talk capacitor array of first capacitor array keeps single-ended structure, high-order first cross-talk capacitor array and the second capacitor array to form differential configuration, first and two capacitor array form the pseudo-differential capacitor array of single-ended combination difference.In analog-digital conversion process, least significant difference fraction weight position forms transition code value after converting and realizes differential-to-single-ended transition.The output end of the output end of calibration capacitance array and the second capacitor array is connected by coupled capacitor, and the offset of mismatch and the comparator for the capacitance to pseudo-differential capacitor array is calibrated.The present invention can save chip area, can carry out self calibration, improve conversion accuracy.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, turn more particularly to a kind of capacitive Approach by inchmeal modulus of pseudo-differential
Parallel operation.
Background technology
Gradually-appoximant analog-digital converter (SAR ADC) is widely used in Medical Devices, high-speed data acquistion system, number
The fields such as signal processing, spectrum analysis, industrial equipment, communication and engine.
Wherein with the relevant important component of accuracy and speed -- digital analog converter (DAC) is played reference voltage
(Vref) two points of key effect is carried out.Purely capacitive type analog-to-digital converter (CDAC) makes precision height because its noise is small, and
It is widely used.
In some in high-precision SAR ADC applications, design is generally using bridge joint capacitance structure, it is therefore an objective to further drop
The total specific capacitance number and size of CDAC in low SAR ADC.
Differential signal than single-ended signal have the advantages that better noise resisting ability, bigger dynamic range, and be used in
In high-performance analog-digital converter.Existing differential capacitance type gradually-appoximant analog-digital converter has larger area.
The dead resistance and parasitic capacitance and the error in industrial manufacturing process of various devices and cabling so that
Two times of relationships between the capacitance of CDAC adjacent bits are inaccurate, significantly limit the raising of SAR ADC precision.In order into one
Step improves two times of relationships between the capacitance of CDAC adjacent bits, to realize the requirement of higher precision, it is necessary to be calibrated to it.
Invention content
Technical problem to be solved by the invention is to provide a kind of capacitive gradually-appoximant analog-digital converters of pseudo-differential, can save
Chip area is saved, self calibration can be carried out, improve conversion accuracy.
In order to solve the above technical problems, the capacitive gradually-appoximant analog-digital converter of pseudo-differential provided by the invention includes first
Capacitor array, the second capacitor array, calibration capacitance array and comparator.
The output end of first capacitor array is connected to the first input end of the comparator and is switched by a switching
It is connected to common mode electrical level, the output end of second capacitor array is connected to the second input terminal of the comparator and passes through all
It changes switch and is connected to common mode electrical level, the first input end of the comparator and the input terminal that the second input terminal is reverse phase each other, by
First capacitor array and second capacitor array form pseudo-differential capacitor array.
First capacitor array includes the first cross-talk capacitor array and more than one low level cross-talk capacitor array, described
First cross-talk capacitor array is that digit is all higher than each low level cross-talk capacitor array.
The first cross-talk capacitor array includes multidigit capacitance, and each low level cross-talk capacitor array includes multidigit capacitance,
The capacitance digit of second capacitor array than the first cross-talk capacitor array capacitance digit more than one, second capacitance
The highest order capacitance of array is equal with the capacitance size of the first cross-talk capacitor array of identical bits successively to time bit capacitor
And form difference weight position capacitance；The lowest order capacitance of second capacitor array and time bit capacitor are equal in magnitude.
In analog-digital conversion process, difference by turn is carried out from the highest order of the first cross-talk capacitor array to lowest order first
Fraction weight position analog-to-digital conversion, the first cross-talk capacitor array least significant difference fraction weight position convert after, will described in most
Low potential difference fraction weight position code value is converted into transition code value；When least significant difference fraction weight position code value is 1, the transition code value
The secondary bit capacitor and lowest order capacitance for making second capacitor array are all grounded；When least significant difference fraction weight position code value is
When 0, the transition code value makes the secondary bit capacitor of second capacitor array and lowest order capacitance all connect reference voltage.
After the transition code value converts, the lowest order capacitance by the first cross-talk capacitor array and the low level section
The capacitance of sub- capacitor array forms single-ended weight bit pattern capacitor array and carries out the conversion of single-ended weight position.
The calibration capacitance array includes multidigit capacitance, the output end of the calibration capacitance array and the second capacitance battle array
The output end of row is connected by coupled capacitor, and the calibration capacitance array is used for the mistake to the capacitance of the pseudo-differential capacitor array
It is calibrated with the offset with the comparator.
A further improvement is that the top crown of every capacitance of the first cross-talk capacitor array links together and conduct
Capacitance positive terminal, the capacitance positive terminal be first capacitor array output end, the first cross-talk capacitor array it is each
The bottom crown of position capacitance is connected to one in positive input voltage, reference voltage and ground by three throw switch of a knife respectively
It is a；The top crown of every capacitance of the same low level cross-talk capacitor array links together, the same low level cross-talk capacitance
The bottom crown of every capacitance of array is connected to positive input voltage, reference voltage and ground by three throw switch of a knife respectively
In one；The top crown of every capacitance of the first cross-talk capacitor array and the adjacent low level cross-talk capacitor array
The top crown of every capacitance is connected by coupled capacitor, the upper pole of every capacitance of adjacent each low level cross-talk capacitor array
Plate is connected also by coupled capacitor；The top crown of every capacitance of second capacitor array links together and anti-as capacitance
Xiang Duan, the capacitance reverse side is the output end of second capacitor array, under every capacitance of second capacitor array
Pole plate is connected to one in reverse inter-input-ing voltage, reference voltage and ground by three throw switch of a knife respectively；The calibration
The top crown of every capacitance of capacitor array links together and as the output end of the calibration capacitance array, the calibration electricity
Hold array every capacitance bottom crown respectively by three throw switch of a knife be connected to reverse inter-input-ing voltage, reference voltage and
One in ground.
A further improvement is that the first input end of the comparator is normal phase input end, the second of the comparator is defeated
It is inverting input to enter end；The output end of the comparator is connected to control logic circuit, each three throw switch of a knife and each
The switching switch is controlled by the control logic circuit.
A further improvement is that the first cross-talk capacitor array includes 6 capacitances, there are one low level cross-talk electricity altogether
It includes 6 capacitances to hold array and the low level cross-talk capacitor array, and the calibration capacitance array includes 7 capacitances.
A further improvement is that the highest order capacitance of the first cross-talk capacitor array to lowest order capacitance size successively
For 32 times of specific capacitances, 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance；
The size of highest order capacitance to the lowest order capacitance of the low level cross-talk capacitor array is followed successively by 16 times of specific capacitances, 8 times of units
Capacitance, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance；The highest of the calibration capacitance array
The size of position capacitance to lowest order capacitance is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of unit electricity
Appearance, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance.
A further improvement is that adjusting capacitance is selectively provided in the first cross-talk capacitor array, each low level
Adjusting capacitance is selectively provided in cross-talk capacitor array, second capacitor array is selectively provided with adjusting capacitance, described
Calibration capacitance array is provided with adjusting capacitance, and the top crown of each adjusting capacitance and the top crown of corresponding position capacitance are connected to
Together, each bottom crown for adjusting capacitance is connected with ground.
A further improvement is that the offset of the mismatch and the comparator to the capacitance of the pseudo-differential capacitor array carries out
The calibration code storage of calibration is in memory.
A further improvement is that each calibration code by the control logic circuit to each three throw switch of a knife
Lower progress Approach by inchmeal measurement is controlled with each switching switch and is calculated.
A further improvement is that the calibration code corresponding to the mismatch of the capacitance of the pseudo-differential capacitor array includes：
The corresponding calibration code of every weight capacitance of the first cross-talk capacitor array, every weight capacitance of second capacitor array
The difference weight capacitance of the correspondence position composition of corresponding calibration code, the first cross-talk capacitor array and second capacitor array
Corresponding calibration code and the highest order of the adjacent low level cross-talk capacitor array of the first cross-talk capacitor array and time height
The corresponding calibration code of weight capacitance of position.
A further improvement is that obtaining the control of corresponding conversion position by multiple calibration codes in analog-digital conversion process
Code, and the control code by obtaining carries out control formation to the calibration capacitance array and is mended to the error of every analog-to-digital conversion
It repays.
Second capacitor array of the invention is only formed with the first cross-talk capacitor array in highest order of the first capacitor array
Difference modulus transformational structure, while one more than ratio the first cross-talk capacitor array that the capacitance digit of the second capacitor array is designed,
The least significant difference fraction weight position code value of the first cross-talk capacitor array is converted into transition code value using a capacitance having more, is passed through
It is realized using the control of the lowest order and time bit capacitor of the second capacitor array of transition code value pair and the first cross-talk capacitor array
The identical weight of least significant difference fraction weight position code value so that the lowest order lowest order capacitance of the first cross-talk capacitor array can and
The capacitance of low level cross-talk capacitor array forms single-ended weight bit pattern capacitor array and carries out the analog-to-digital conversion of single-ended weight position, institute
Transition of the difference modes to single-ended mode can be realized with the present invention, is not to use fully differential structure, relative to fully differential electricity
Appearance type gradually-appoximant analog-digital converter, the present invention can save chip area.
The high-order section of the present invention uses differential type structure simultaneously, can retain the capacitive Approach by inchmeal analog-to-digital conversion of fully differential
Advantage possessed by device, the i.e. present invention similarly can keep preferable noise resisting ability and larger dynamic range.
In addition, the present invention is by being arranged calibration capacitance array, it can be to each of the first capacitor array and the second capacitor array
The mismatch of the capacitance of the difference weight capacitance of the single-ended weight capacitance in position and the first capacitor array and the second capacitor array composition and
The offset of comparator is calibrated, and two times of relationships between analog-digital converter adjacent bit capacitance can be made more accurate, improved
The precision of analog-digital converter.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the capacitive gradually-appoximant analog-digital converter circuit diagram of pseudo-differential of the embodiment of the present invention；
Fig. 2 is the sample phase circuit diagram of circuit of the embodiment of the present invention shown in Fig. 1；
Fig. 3 is the highest order conversion stage circuit figure of circuit of the embodiment of the present invention shown in Fig. 1；
Fig. 4 is high 6 conversions stage circuit figure of circuit of the embodiment of the present invention shown in Fig. 1；
Fig. 5 is low 6 conversions stage circuit figure of circuit of the embodiment of the present invention shown in Fig. 1.
Specific implementation mode
As shown in Figure 1, being the capacitive gradually-appoximant analog-digital converter circuit diagram of pseudo-differential of the embodiment of the present invention；The present invention is real
It includes the first capacitor array 101, the second capacitor array 102, calibration electricity to apply the capacitive gradually-appoximant analog-digital converter of a pseudo-differential
Hold array 105, comparator (COMP) 103, control logic circuit (SAR&CAL Logic) 104 and memory (CAL Memory)
106。
The output end PX of first capacitor array 101 is connected to the first input end of the comparator 103 and by one
Switching switch SP is connected to common mode electrical level VCM, the output end NX of second capacitor array 102 and is connected to the comparator 103
The second input terminal and common mode electrical level VCM is connected to by a switching switch SN, by first capacitor array 101 and described the
Two capacitor arrays 102 form pseudo-differential capacitor array.
First capacitor array 101 includes the first cross-talk capacitor array and more than one low level cross-talk capacitor array,
The first cross-talk capacitor array is that digit is all higher than each low level cross-talk capacitor array.
The first cross-talk capacitor array includes multidigit capacitance, and each low level cross-talk capacitor array includes multidigit capacitance,
The capacitance digit of second capacitor array 102 than the first cross-talk capacitor array capacitance digit more than one, described second
The highest order capacitance of capacitor array 102 is big with the capacitance of the first cross-talk capacitor array of identical bits successively to time bit capacitor
It is small equal and form difference weight position capacitance；The lowest order capacitance of second capacitor array 102 and time bit capacitor size phase
Deng.
In analog-digital conversion process, difference by turn is carried out from the highest order of the first cross-talk capacitor array to lowest order first
Fraction weight position analog-to-digital conversion, the first cross-talk capacitor array least significant difference fraction weight position convert after, will described in most
Low potential difference fraction weight position code value is converted into transition code value；When least significant difference fraction weight position code value is 1, the transition code value
The secondary bit capacitor and lowest order capacitance for making second capacitor array 102 are all grounded；When least significant difference fraction weight position code
When value is 0, the transition code value makes the secondary bit capacitor of second capacitor array 102 and lowest order capacitance all connect reference voltage
VREF。
After the transition code value converts, the lowest order capacitance by the first cross-talk capacitor array and the low level section
The capacitance of sub- capacitor array forms single-ended weight bit pattern capacitor array and carries out the conversion of single-ended weight position.
The calibration capacitance array 105 includes multidigit capacitance, the output end of the calibration capacitance array 105 and described second
The output end of capacitor array 102 is connected by coupled capacitor CNS, and the calibration capacitance array 105 is used for pseudo-differential electricity
The offset for holding the mismatch and the comparator 103 of the capacitance of array is calibrated.
In the embodiment of the present invention, the top crown of every capacitance of the first cross-talk capacitor array links together and conduct
Capacitance positive terminal PX, the capacitance positive terminal PX are the output end PX of first capacitor array 101, the first cross-talk capacitance
The bottom crown of every capacitance of array is connected to positive input voltage VINP, reference voltage by three throw switch of a knife respectively
One in VREF and ground.
The top crown of every capacitance of the same low level cross-talk capacitor array links together, the same low level cross-talk
The bottom crown of every capacitance of capacitor array is connected to positive input voltage VINP, reference by three throw switch of a knife respectively
One in voltage VREF and ground；The top crown of every capacitance of the first cross-talk capacitor array and the adjacent low level section
The top crown of every capacitance of sub- capacitor array is connected by coupled capacitor CPS, adjacent each low level cross-talk capacitor array
The top crown of every capacitance connected also by coupled capacitor.
The top crown of every capacitance of second capacitor array 102 links together and as capacitance reverse side NX, institute
Capacitance reverse side NX is stated for the output end of second capacitor array 102, under every capacitance of second capacitor array 102
Pole plate is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground by three throw switch of a knife respectively.
The top crown of every capacitance of the calibration capacitance array 105 links together and as the calibration capacitance array
The bottom crown of 105 output end, every capacitance of the calibration capacitance array 105 is connected by three throw switch of a knife respectively
To one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground.
The first input end of the comparator 103 is normal phase input end, and the second input terminal of the comparator 103 is reverse phase
Input terminal；The output end of the comparator 103 is connected to control logic circuit 104, each three throw switch of a knife and each described
Switching switch is controlled by the control logic circuit 104.
In example shown in FIG. 1, the first cross-talk capacitor array include 6 capacitances, respectively capacitance CPM6, CPM5,
CPM4, CPM3, CPM2 and CPM1, the bottom crown of each capacitance respectively by three throw switch SPM6, SPM5 of a knife, SPM4, SPM3,
SPM2 and SPM1 is connected to one in positive input voltage VINP, reference voltage VREF and ground.The first cross-talk capacitance battle array
Row, which are additionally provided with, adjusts capacitance CPM0, and the top crown for adjusting capacitance CPM0 connects output end PX, bottom crown ground connection.
The low level cross-talk capacitor array and the low level cross-talk capacitor array include 6 capacitances there are one altogether, respectively
Capacitance CPN5, CPN4, CPN3, CPN2, CPN1 and CPN0, the bottom crown of each capacitance respectively by three throw switch SPN5 of a knife,
SPN4, SPN3, SPN2, SPN1 and SPN0 are connected to one in positive input voltage VINP, reference voltage VREF and ground.
Second capacitor array 102 includes then 7 capacitances, respectively capacitance CNM6, CNM5, CNM4, CNM3,
CNM2, CNM1 and CNM0, the bottom crown of each capacitance respectively by three throw switch SNM6, SNM5 of a knife, SNM4, SNM3, SNM2,
SNM1 and SNM1 is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground.
The calibration capacitance array include 7 capacitances, respectively capacitance CNN5, CNN4, CNN3, CNN2, CNN1, CNC and
The bottom crown of CNB, each capacitance are connected to by a knife three throw switch SNN5, SNN4, SNN3, SNN2, SNN1, SNC and SNB respectively
One in reverse inter-input-ing voltage VINN, reference voltage VREF and ground.The calibration capacitance array is additionally provided with adjusting capacitance
CNA, the top crown for adjusting capacitance CNA connect the output end of the calibration capacitance array 105, bottom crown ground connection.
The size of highest order capacitance to the lowest order capacitance of the first cross-talk capacitor array is followed successively by 32 times of specific capacitances
(C) i.e. 32C, 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance adjust electricity
Appearance CPM0 is 1 times of specific capacitance；
The size of highest order capacitance to the lowest order capacitance of the low level cross-talk capacitor array be followed successively by 16 times of specific capacitances,
8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance.
The size of highest order capacitance to the lowest order capacitance of the calibration capacitance array 105 is followed successively by 16 times of specific capacitances, 8
Times specific capacitance, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance,
It is 1/4 times of specific capacitance to adjust capacitance CNA.
Coupled capacitor CPS is 32/31 times of specific capacitance, and coupled capacitor CNS is 32/31 times of specific capacitance.
The calibration code that the offset of mismatch and the comparator 103 to the capacitance of the pseudo-differential capacitor array is calibrated
It is stored in memory 106.
Each calibration code by the control logic circuit 104 to each three throw switch of a knife and each switching
Switch control is lower to be carried out Approach by inchmeal measurement and is calculated.
The calibration code corresponding to the mismatch of the capacitance of the pseudo-differential capacitor array includes：The first cross-talk capacitance
The corresponding calibration code of every weight capacitance of array, the corresponding calibration code of every weight capacitance of second capacitor array 102,
The corresponding calibration of difference weight capacitance of the correspondence position of the first cross-talk capacitor array and second capacitor array 102 composition
The weight electricity of the highest order and a time high position of code and the adjacent low level cross-talk capacitor array of the first cross-talk capacitor array
Hold corresponding calibration code.
In analog-digital conversion process the control code of corresponding conversion position, and the institute by obtaining are obtained by multiple calibration codes
State the error compensation that control code carries out control formation to every analog-to-digital conversion to the calibration capacitance array 105.
The illustratively course of work of circuit of the embodiment of the present invention below：
The sub- SAR ADC of calibration that calibration capacitance array 105, comparator 103 and control logic circuit 104 form, first measure
The input offset voltage (OS) of comparator 103, calibration code DOS is converted into the coding mode of bipolarity offset binary,
It is stored in memory 106.
By total sampling capacitance of capacitance positive terminal PX and capacitance reverse side NX regard as respectively not error value Cptot and
Cntot, then the specific capacitance ideal value of capacitance positive terminal PX and capacitance reverse side NX are respectively Cptot/64 and Cntot/64,
The ideal value of each weight capacitance is the 2 of specific capacitance ideal valueiAgain (i=-5, -4 ..., 5), each weight capacitance and Qi Li
Think all there is error between value, all weight capacitance errors and be zero.
The control switching switch of control logic circuit 104 SP, SN, first capacitor array 101 and the second capacitance battle array
Single-pole three-throw switch three throw switch of an i.e. knife in row 102 generates the voltage letter containing weight capacitance CPM6 mismatch error information
Number, the sub- SARADC of calibration that calibration capacitance array 105, comparator 103 and control logic circuit 104 form, then measure this electricity
Pressure, obtains the coding mode measured value DMPM6 with bipolarity offset binary.The calibration code of weight capacitance CPM6 is calculated again
DCPM6=(DMPM6-DOS)/2, is deposited into memory 106.
The control switching switch of control logic circuit 104 SP, SN, first capacitor array 101 and the second capacitance battle array
Single-pole three-throw switch in row 102, then generate the voltage signal containing weight capacitance CPM5 mismatch error information, calibration capacitance battle array
The sub- SAR ADC of calibration that row 105, comparator 103 and control logic circuit 104 form, then this voltage is measured, it obtains with bipolar
The coding mode measured value DMPM5 of property offset binary.Calibration code DCPM5=(the DMPM5- of weight capacitance CPM5 are calculated again
DOS-DCPM6)/2, it is deposited into memory 106.
And so on, the code that calibrates for error of weight capacitance CPM6-CPM1, CPN5, CNM6-CNM1 are obtained successively：
DCPM6=(DMPM6-DOS)/2
DCPM5=(DMPM5-DOS-DCPM6)/2
DCPM4=(DMPM4-DOS-DCPM6-DCPM5)/2
DCPM3=(DMPM3-DOS-DCPM6-DCPM5-DCPM4)/2
DCPM2=(DMPM2-DOS-DCPM6-DCPM5-DCPM4-DCPM3)/2
DCPM1=(DMPM1-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2)/2
DCPN5=(DMPN5-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2-DCPM1)/2
DCPN4=(DMPN5-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2-DCPM1-DCPN4)/2
DCNM6=(DMNM6-DOS)/2
DCNM5=(DMNM5-DOS-DCNM6)/2
DCNM4=(DMNM4-DOS-DCNM6-DCNM5)/2
DCNM3=(DMNM3-DOS-DCNM6-DCNM5-DCNM4)/2
DCNM2=(DMNM2-DOS-DCNM6-DCNM5-DCNM4-DCNM3)/2
DCNM1=(DMNM1-DOS-DCNM6-DCNM5-DCNM4-DCNM3-DCNM2)/2
Calculate the calibration code DCNM0=0-DCNM6-DCNM5-DCNM4-DCNM3-DCNM2-DCNM1 of CNM0
Calculate the calibration code of high 6 potential difference fraction weight capacitance：
DCM6=DCPM6+DCNM6
DCM5=DCPM5+DCNM5
DCM4=DCPM4+DCNM4
DCM3=DCPM3+DCNM3
DCM2=DCPM2+DCNM2
DCM1=DCPM1+DCNM1
Calibration code DCM6-DCM1, DCPM1, DCPN5, DCPN4 and DCNM0 are stored in memory 106.
As shown in Fig. 2, being the sample phase circuit diagram of circuit of the embodiment of the present invention shown in Fig. 1；In sample phase, switch SP
It is closed with SN, node PX, that is, capacitance positive terminal PX and node NX, that is, capacitance reverse side NX meet VCM, in the first capacitor array 101
Single-pole three-throw switch all meet VINP, the single-pole three-throw switch in the second capacitor array 102 all connects VINN, differential input signal
VINP-VINN is sampled the weight capacitor array of the weight capacitor array and the second capacitor array 102 of the first capacitor array 101
On.
The control code DM< of calibration capacitance array 105;6:0>It is 1000000.
As shown in figure 3, being the highest order conversion stage circuit figure of circuit of the embodiment of the present invention shown in Fig. 1；After starting conversion,
Switch SP and SN is disconnected, and the single-pole three-throw switch SPM6 of the first capacitor array 101 is met VREF by control logic circuit 104, and first
Remaining single-pole three-throw switch of capacitor array 101 is all grounded, and can generate VCM- (VINP-1/2VREF) at the ends node PX in this way, together
When control logic circuit 104 the single-pole three-throw switch SNM6 ground connection of the second capacitor array 102, the second capacitor array 102 its
Remaining single-pole three-throw switch all meets VREF, can generate VCM- (VINN-1/2VREF) at the ends node NX in this way.
Calibrate the control code DM< of sub- DAC105;6:0>It is for DOS+DCM6,103 offset voltage of comparator and difference weight is electric
The error compensation for holding CPM6 and CNM6 is fallen.
The size at the comparator ends comparison node PX and the ends node NX, i.e. ,-(VIP-VIN) are greater than 0 and are also less than 0, and will
The output of comparator 103 is given to control logic circuit 104, namely obtains D12 code values.(VIP-VIN) VIP in formula indicates institute
It states the normal phase input end of comparator 103 namely the voltage of the capacitance positive terminal PX, VIN indicates the reverse phase of the comparator 103
The voltage of input terminal namely the capacitance reverse side NX.
If (VIP-VIN)s <0, D12=1 is obtained, single-pole three-throw switch SPM6 is met into VREF in next step, by single-pole three throw
Switch SNM6 ground connection, and single-pole three-throw switch SPM5 is met into VREF, single-pole three-throw switch SNM5 is grounded, i.e., the next change-over period
The ends node PX generate VCM- (VINP-1/2VREF), and the ends node NX generate VCM-VIN；
If (VIP-VIN)s >0, D12=0 is obtained, single-pole three-throw switch SPM6 is grounded in next step, single-pole three throw is opened
It closes SNM6 and meets VREF, and single-pole three-throw switch SPM5 is met into VREF, single-pole three-throw switch SNM5 is grounded, i.e., the next change-over period
The ends node PX generate VCM-VINP, and the ends node NX generate VCM- (VIN-1/2VREF).
Calibrate the control code DM< of sub- DAC105;6:0>For DOS+D12*DCM6+DCM5；
The size at comparator 103 ends comparison node PX and the ends node NX again, obtains D11 code values, as shown in Figure 4.
As shown in figure 4, and so on, comparator constantly compares input terminal, until completing difference weight position CPM1 and CNM1
Conversion, so far the code value of high position D12-D7 have determined that.
The least significant difference fraction obtained by differential mode weight position code value i.e. D7 is converted by capacitance CNM0 below and
The transition code value that CNM1 is indicated realizes the transition by differential-to-single-ended structure：
SPM1 is met VREF by next period；
If D7=1, single-pole three-throw switch SNM0 and SNM1 are met into GND, calibrate the control code DM< of sub- DAC105;6:0>For
DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+DCM1+DCNM0；
If D7=0, single-pole three-throw switch SNM0 and SNM1 are met into VREF, calibrate the control code DM< of sub- DAC105;6:0>
For DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+DCPM1；
Comparator 103 compares input terminal, obtains D6 code values, i.e. code value D6 is detected to obtain by single ended mode, as shown in Figure 5.
As shown in figure 5, single-pole three-throw switch SPN5 is met VREF by next period again
If D6=1, single-pole three-throw switch SPM1 is met into VREF, calibrates the control code DM< of sub- DAC105;6:0>For DOS+
D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7*(DCM1+DCNM0,DCPM1)+DCPN5；
If D6=0, single-pole three-throw switch SPM1 is met into GND, calibrates the control code DM< of sub- DAC105;6:0>For DOS+
D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7*(DCM1+DCNM0,DCPM1)-DCPM1+DCPN5。
Comparator compares input terminal, obtains D5 code values.
Single-pole three-throw switch SPN4 is met VREF by next period again；
If D5=1, single-pole three-throw switch SPN5 is met into VREF；
If D5=0, single-pole three-throw switch SPN5 is met into GND.
Calibrate the control code DM< of sub- DAC105;6:0>For：
DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7*(DCM1+DCNM0,DCPM1)+
D6*(0,-DCPM1)+D5*DCPN5+DCPN4；
Comparator 103 compares input terminal, obtains D4 code values.
And so on, the constantly comparison input terminal of comparator 103, the conversion until completing lowest weightings position CPN1, so far
The code value of D12-D1 is it has been determined that difference Approach by inchmeal analog-to-digital conversion is completed.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of capacitive gradually-appoximant analog-digital converter of pseudo-differential, which is characterized in that including the first capacitor array, the second capacitance
Array, calibration capacitance array and comparator；
The output end of first capacitor array is connected to the first input end of the comparator and by a switching switch connection
Output end to common mode electrical level, second capacitor array is connected to the second input terminal of the comparator and is opened by a switching
Connection is connected to common mode electrical level, the first input end of the comparator and the input terminal that the second input terminal is reverse phase each other, by described
First capacitor array and second capacitor array form pseudo-differential capacitor array；
First capacitor array include the first cross-talk capacitor array and more than one low level cross-talk capacitor array, described first
The digit of cross-talk capacitor array is all higher than each low level cross-talk capacitor array；
The first cross-talk capacitor array includes multidigit capacitance, and each low level cross-talk capacitor array includes multidigit capacitance, described
The capacitance digit of second capacitor array than the first cross-talk capacitor array capacitance digit more than one, second capacitor array
Highest order capacitance to time bit capacitor successively and group equal with the capacitance size of the first cross-talk capacitor array of identical bits
At difference weight position capacitance；The lowest order capacitance of second capacitor array and time bit capacitor are equal in magnitude；
In analog-digital conversion process, difference power by turn is carried out from the highest order of the first cross-talk capacitor array to lowest order first
Weight position analog-to-digital conversion, the first cross-talk capacitor array least significant difference fraction weight position convert after, by lowest order difference
Weight position code value is converted into transition code value；When least significant difference fraction weight position code value is 1, the transition code value makes described the
The secondary bit capacitor and lowest order capacitance of two capacitor arrays are all grounded；It is described when least significant difference fraction weight position code value is 0
Transition code value makes the secondary bit capacitor of second capacitor array and lowest order capacitance all connect reference voltage；
After the transition code value converts, by the lowest order capacitance of the first cross-talk capacitor array and low level cross-talk electricity
The capacitance for holding array forms single-ended weight bit pattern capacitor array and carries out the conversion of single-ended weight position；
The calibration capacitance array includes multidigit capacitance, the output end of the calibration capacitance array and second capacitor array
Output end is connected by coupled capacitor, the calibration capacitance array be used for the mismatch of the capacitance of the pseudo-differential capacitor array and
The offset of the comparator is calibrated.
2. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as described in claim 1, is characterized in that：The first cross-talk electricity
The top crown for holding every capacitance of array links together and as capacitance positive terminal, and the capacitance positive terminal is first electricity
Hold the output end of array, the bottom crown of every capacitance of the first cross-talk capacitor array passes through three throw switch of a knife respectively
One be connected in positive input voltage, reference voltage and ground；
The top crown of every capacitance of the same low level cross-talk capacitor array links together, the same low level cross-talk capacitance
The bottom crown of every capacitance of array is connected to positive input voltage, reference voltage and ground by three throw switch of a knife respectively
In one；
Everybody of the top crown of every capacitance of the first cross-talk capacitor array and the adjacent low level cross-talk capacitor array
The top crown of capacitance is connected by coupled capacitor, the top crown of every capacitance of adjacent each low level cross-talk capacitor array
It is connected by coupled capacitor；
The top crown of every capacitance of second capacitor array links together and as capacitance reverse side, the capacitance reverse phase
End is the output end of second capacitor array, and the bottom crown of every capacitance of second capacitor array passes through one one respectively
Three throw switch of knife is connected to one in reverse inter-input-ing voltage, reference voltage and ground；
The top crown of every capacitance of the calibration capacitance array links together and as the output of the calibration capacitance array
The bottom crown at end, every capacitance of the calibration capacitance array is connected to anti-phase input electricity by three throw switch of a knife respectively
One in pressure, reference voltage and ground.
3. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 2, is characterized in that：
The first input end of the comparator is normal phase input end, and the second input terminal of the comparator is inverting input；
The output end of the comparator is connected to control logic circuit, each three throw switch of a knife and each switching switch by
The control logic circuit control.
4. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 1 or 2, is characterized in that：The first segment
Sub- capacitor array includes 6 capacitances, includes altogether 6 there are one the low level cross-talk capacitor array and the low level cross-talk capacitor array
Position capacitance, the calibration capacitance array include 7 capacitances.
5. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 4, is characterized in that：The first cross-talk electricity
The size for holding highest order capacitance to the lowest order capacitance of array is followed successively by 32 times of specific capacitances, 16 times of specific capacitances, 8 times of unit electricity
Appearance, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance；
The size of highest order capacitance to the lowest order capacitance of the low level cross-talk capacitor array be followed successively by 16 times of specific capacitances, 8 times
Specific capacitance, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance；
The size of highest order capacitance to the lowest order capacitance of the calibration capacitance array is followed successively by 16 times of specific capacitances, 8 times of units
Capacitance, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance.
6. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 1 or 2, is characterized in that：The first segment
It is selectively provided with adjusting capacitance in sub- capacitor array, adjusting electricity is selectively provided in each low level cross-talk capacitor array
Hold, second capacitor array is selectively provided with adjusting capacitance, and the calibration capacitance array is provided with adjusting capacitance, each described
The top crown of the top crown and corresponding position capacitance that adjust capacitance links together, each bottom crown for adjusting capacitance and ground connect
It connects.
7. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as described in claim 1, is characterized in that：To pseudo-differential electricity
The calibration code storage that the mismatch of capacitance of appearance array and the offset of the comparator are calibrated is in memory.
8. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 7, is characterized in that：Each calibration code is logical
It crosses and carries out Approach by inchmeal measurement in the case where control logic circuit is to each three throw switch of a knife and each switching switch control and calculate
It obtains.
9. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 7, is characterized in that：The pseudo-differential capacitance
The calibration code corresponding to the mismatch of the capacitance of array includes：Every weight capacitance of the first cross-talk capacitor array corresponds to
Calibration code, the corresponding calibration code of every weight capacitance of second capacitor array, the first cross-talk capacitor array and institute
State the corresponding calibration code of difference weight capacitance of the correspondence position composition of the second capacitor array and the first cross-talk capacitor array phase
The highest order of adjacent low level cross-talk capacitor array calibration code corresponding with time weight capacitance of a high position.
10. the capacitive gradually-appoximant analog-digital converter of pseudo-differential as claimed in claim 8 or 9, is characterized in that：In analog-to-digital conversion
The control code of corresponding conversion position is obtained by multiple calibration codes in the process, and the control code by obtaining is to the calibration
Capacitor array carries out error compensation of the control formation to every analog-to-digital conversion.
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| CN106374930B (en) * | 2016-09-28 | 2019-09-03 | 东南大学 | Gradually-appoximant analog-digital converter and D conversion method based on digital calibration |
| CN106896283B (en) * | 2017-02-08 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | Measure the circuit structure and measurement method of capacitance mismatch characteristic |
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| CN109802674B (en) * | 2017-11-17 | 2021-07-16 | 比亚迪半导体股份有限公司 | Successive approximation analog-to-digital converter and digital calibration method and device thereof |
| CN109802678B (en) * | 2017-11-17 | 2020-11-20 | 比亚迪股份有限公司 | Successive approximation analog-to-digital converter and digital calibration method and device thereof |
| CN107888190B (en) * | 2017-12-01 | 2020-09-25 | 西安电子科技大学 | Successive approximation type analog-digital converter based on asymmetric differential capacitor array |
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| CN110535467B (en) * | 2019-07-26 | 2023-03-24 | 中国科学院上海微系统与信息技术研究所 | Capacitor array calibration method and device of stepwise approximation type analog-to-digital conversion device |
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| CN111934689B (en) * | 2020-09-23 | 2021-07-06 | 电子科技大学中山学院 | High-precision analog-to-digital converter and conversion method |
| CN112636757A (en) * | 2020-12-25 | 2021-04-09 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112764447A (en) * | 2021-04-07 | 2021-05-07 | 上海艾为微电子技术有限公司 | Dynamic offset calibration circuit, method, chip and electronic equipment |
| CN113839673B (en) * | 2021-09-14 | 2023-08-01 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
| CN113794475B (en) * | 2021-11-16 | 2022-03-15 | 杭州深谙微电子科技有限公司 | Calibration method of capacitor array type successive approximation analog-digital converter |
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