CN104124972A

CN104124972A - 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution

Info

Publication number: CN104124972A
Application number: CN201410390039.9A
Authority: CN
Inventors: 丁瑞雪; 刘建; 梁宇华; 朱樟明; 杨银堂
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2014-08-08
Filing date: 2014-08-08
Publication date: 2014-10-29
Anticipated expiration: 2034-08-08
Also published as: CN104124972B

Abstract

The invention provides a 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution. The analog-to-digital converter comprises a sampling network, a differential capacitor array, a comparator and a successive approximation control logic device; the differential capacitor array is connected with the sampling network, the comparator is connected with the differential capacitor array, and the successive approximation control logic device is connected with the comparator. The differential capacitor array includes a first capacitor array connected with a non-inverting input end of a comparator circuit and a second capacitor array connected with an inverting input end of the comparator circuit. Each of the first capacitor array and the second capacitor array consists of nine groups of capacitors which are of binary structures; bottom plates of all redundant capacitors are selectively connected with common-mode voltage or ground and the rest eight groups of capacitors are selectively connected with the common-mode voltage, power voltage or ground. An output end of the successive approximation control logic device controls switching of capacitor switches of the differential capacitor array to be connected with the voltage selectively. The first capacitor array and the second capacitor array sample input signals and input samples to the comparator, and a comparison result of the comparator is input to the successive approximation control logic device.

Description

10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation

Technical field

The present invention relates to hybrid digital-analog integrated circuit design field, relate in particular to the super low-power consumption gradual approaching A/D converter based on electric charge reallocation.

Background technology

Gradual approaching A/D converter (SAR ADC) is the analog to digital converter type of the medium sampling rate of a kind of medium accuracy, it have advantages of simple in structure, area is little, low in energy consumption, thereby be widely used in various medical treatment, portable electric appts and communication system.Because gradually-appoximant analog-digital converter need to be such as linear gain modules such as operational amplifiers, make SAR ADC can adapt to preferably the technique evolution trend that reduces with supply voltage of reducing of characteristic size.Along with the progress of technique, it is hundreds of million that the switching rate that SAR ADC can reach is also increased to, thereby can match in excellence or beauty with flow-line modulus converter, and have higher power consumption utilance.

Gradual approaching A/D converter is mainly comprised of digital-to-analogue (D/A) transducer, comparator and successive approximation register, and wherein D/A converter is generally binary system capacitance type structure.Simplification and high efficiency that charge redistribution type D/A converter is controlled due to its switch are widely applied.

For traditional gradual approaching A/D converter based on capacitor array, due to the relatively large area of capacitor array, caused the precision of conventional successive approach type analog to digital converter to accomplish very high, meanwhile, larger capacity area, can cause the increase of power consumption.

Summary of the invention

The object of the present invention is to provide 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation, solve traditional gradual approaching A/D converter based on capacitor array, due to the relatively large area of capacitor array, cause the precision of conventional successive approach type analog to digital converter to accomplish very high, and can cause the problem of the increase of power consumption.

In order to solve the problems of the technologies described above, 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation that the embodiment of the present invention provides, wherein, comprising: sampling network, the differential capacitance array being connected with described sampling network, the comparator being connected with described differential capacitance array, be connected with the output of described comparator successively approach control logic; Wherein

Described differential capacitance array comprises the first capacitor array that connects described comparator circuit normal phase input end and the second capacitor array that is connected described comparator circuit inverting input; Wherein

Described the first capacitor array and described the second capacitor array form by the electric capacity of 9 groups of binary structure, and the bottom crown of the redundant capacitor of wherein said the first capacitor array and the redundant capacitor of described the second capacitor array selects to be connected common-mode voltage V _cMor ground GND, remaining 8 groups of capacitance selection connects common-mode voltage V _cM, supply voltage V _rEFor ground GND;

The described output that successively approaches control logic is controlled the switching of the capacitance switch of described differential capacitance array and is selected to connect voltage;

Wherein, described the first capacitor array and described the second capacitor array are sampled to input signal, and sampled result is inputed to described comparator, and described in inputing to, the comparative result of described comparator successively approaches control logic, realize successively approaching input signal.

Further, the described control logic of successively approaching comprises: the shift register being connected with described comparator and be connected d type flip flop DFF with described shift register, the output output of described d type flip flop DFF converts signal EN.

Further, described shift register comprises 9 subelements that are connected in series,

The first input end of wherein said subelement is all connected with comparison settling signal Valid, and the first output of a upper subelement is all connected with the second input of next subelement;

The second input of first subelement and sampled clock signal Sample's is disconnected, the first input end of last subelement is connected in the first input end of described d type flip flop DFF, and the first output of last subelement is also connected in the second input connection of described d type flip flop DFF;

The second output of described subelement all with the first bottom crown switching signal (P _i) connect, the 3rd output of described subelement all with the second bottom crown switching signal (N _i) connect, wherein, the natural number that i is 1≤i≤9;

The 4th output of described subelement is all connected with comparator the first output signal Voutp, and the 5th output of described subelement is all connected with comparator the second output signal Voutn.

Further, the described subelement successively approaching in control logic comprises: the 18 MOS transistor M18, the 19 MOS transistor M19, the 20 MOS transistor M20, the 21 MOS transistor M21, the 22 MOS transistor M22, the 23 MOS transistor M23, the 24 MOS transistor M24, the 25 MOS transistor M25, the 26 MOS transistor M26, the 27 MOS transistor M27, the 28 MOS transistor M28, the 29 MOS transistor M29, the 30 MOS transistor M30;

The grid of described the 18 MOS transistor M18 is connected in the first port D; The grid of described the 18 MOS transistor M18 is also connected in the grid of described the 20 MOS transistor M20;

The source ground of described the 20 MOS transistor M20 connects, and the drain electrode of described the 20 MOS transistor M20 is connected in the source electrode of described the 19 MOS transistor M19;

The grid of described the 19 MOS transistor M19 is connected in described relatively settling signal Valid, the drain electrode of described the 19 MOS transistor M19 is connected in the drain electrode of described the 18 MOS transistor M18, and described the 18 source electrode of MOS transistor M18 and the source electrode of described the 21 MOS transistor M21 are connected in supply voltage V _rEF;

The grid of described the 21 MOS transistor M21 is connected in the drain electrode of described the 18 MOS transistor M18, and the drain electrode of described the 18 MOS transistor M18 produces the first clock signal clk _i;

The grid of described the 21 MOS transistor M21 is also connected in the grid of described the 23 MOS transistor M23, the source ground of described the 23 MOS transistor M23;

The drain electrode of described the 23 MOS transistor M23 is connected in the drain electrode of described the 22 MOS transistor M22, the grid of described the 22 MOS transistor M22 is connected in the grid of described the 19 MOS transistor M19, and the source electrode of described the 22 MOS transistor M22 is connected in the drain electrode of described the 21 MOS transistor M21;

The drain electrode of described the 22 MOS transistor M22 is connected in the grid of described the 27 MOS transistor M27, the grid that outputs signal to described the 27 MOS transistor M27 of the drain electrode of described the 22 MOS transistor M22, the drain electrode of described the 27 MOS transistor M27 is connected in the drain electrode of described the 29 MOS transistor M29, the source ground of described the 29 MOS transistor M29 connects, the grid of described the 29 MOS transistor M29 is connected in the drain electrode of described the 18 MOS transistor M18, the drain electrode of described the 29 MOS transistor M29 is also connected in described the second bottom crown switching signal N _i,

The source ground of described the 30 MOS transistor M30 connects, and the grid of described the 30 MOS transistor M30 is connected in the drain electrode of described the 18 MOS transistor M18, and the drain electrode of described the 30 MOS transistor M30 is connected in described the first bottom crown switching signal P _i, the drain electrode of described the 30 MOS transistor M30 is also connected in the drain electrode of described the 28 MOS transistor M28, and the grid of described the 28 MOS transistor M28 is also connected in the grid of described the 27 MOS transistor M27;

The source electrode of described the 27 MOS transistor M27 is connected in the drain electrode of described the 25 MOS transistor M25, and the grid of described the 25 MOS transistor M25 is connected in described comparator the first output signal Voutp;

The source electrode of described the 25 MOS transistor M25 is connected in the source electrode of described the 26 MOS transistor M26, the grid of described the 26 MOS transistor M26 is connected in described comparator the second output signal Voutn, and the drain electrode of described the 26 MOS transistor M26 is connected in the source electrode of described the 28 MOS transistor M28;

The source electrode of described the 26 MOS transistor M26 is also connected in the drain electrode of described the 24 MOS transistor M24, and the source electrode of described the 24 MOS transistor M24 is connected in described supply voltage V _rEF, the grid of described the 24 MOS transistor M24 is connected in the drain electrode of described the 18 MOS transistor M18, wherein, and the natural number that i is 1≤i≤9.

Further, described the first capacitor array comprises: the first top crown, the first bottom crown and be connected to described the first top crown and described the first bottom crown between the first to the 9th electric capacity being arranged side by side and the capacitance switch connecting one to one with the described first to the 9th electric capacity;

Described the second capacitor array comprises: the second top crown, the second bottom crown and be connected to described the second top crown and described the second bottom crown between the first to the 9th electric capacity being arranged side by side and the capacitance switch connecting one to one with the described first to the 9th electric capacity;

The electrode input end of described comparator is connected with described the first top crown, and negative input is connected with described the second top crown;

Described the first top crown also passes through the first bootstrapped switch K of described sampling network ₁connect positive difference analogue input signal V _p;

Described the second top crown also passes through the second bootstrapped switch K of described sampling network ₂connect anti-phase difference analogue input signal V _n;

Described first bottom crown of described the first capacitor array selects to connect common-mode voltage V by switch respectively _cMwith ground GND and except the redundant capacitor C of the first capacitor array ₀other outer electric capacity bottom crowns select to connect supply voltage V by switch _rEF;

Described second bottom crown of described the second capacitor array selects to connect common-mode voltage V by switch respectively _cMwith ground GND and except the redundant capacitor C of the second capacitor array ₀' other outer electric capacity bottom crowns select connection supply voltage V by switch _rEF.

Further, the first capacitor C of described the first capacitor array ₀capacitance be C, the second capacitor C ₁capacitance equal the first capacitor C ₀capacitance C, the 3rd capacitor C ₂to the 9th capacitor C ₈capacitance be C _i+1=2C _i, wherein, the natural number that i is 1≤i≤7;

The first capacitor C of described the second capacitor array ₀' capacitance be C, the second capacitor C ₁' capacitance equal the first capacitor C ₀' capacitance C, the 3rd capacitor C ₂' to the 9th capacitor C ₈' capacitance be C _i+1'=2C _i', wherein, the natural number that i is 1≤i≤7.

Further, the switching sequence of described the first capacitor array and described the second capacitor array comprises:

Described the second bootstrapped switch K ₂with the second bootstrapped switch K ₂align phase difference analogue input signal V _pwith anti-phase difference analogue input signal V _nsample, obtain positive phase input signal and rp input signal;

Repeatedly more described forward input signal and described rp input signal, when first described forward input signal is less than/is greater than described rp input signal, control the common-mode voltage V of bottom crown of one group of electric capacity of the maximum capacitor value of the first/the second capacitor array _cMswitch to supply voltage V _rEF, the common-mode voltage V of the bottom crown of one group of electric capacity of the maximum capacitor value of described the second/the first capacitor array _cMswitch to ground GND.

Further, the switching sequence of described the first capacitor array and described the second capacitor array also comprises:

If forward input signal is less than reverse input signal during first comparison phase, in so follow-up comparison procedure, if forward input signal is less than reverse input signal, the ground GND of the position electric capacity bottom crown that the first capacitor array is corresponding switches to supply voltage V _rEF; If forward input signal is greater than reverse input signal, the position electric capacity bottom crown connection that the second capacitor array is corresponding is constant, and the ground GND of the previous position electric capacity bottom crown of corresponding position electric capacity switches to common-mode voltage V _cM;

When first described forward input signal is greater than described rp input signal, follow-up relatively in, when if forward input signal is less than reverse input signal, the electric capacity bottom crown connection of the corresponding position of described the first capacitor array is constant, and the ground GND of the previous position electric capacity bottom crown of corresponding position switches to common-mode voltage V _cM; When if described forward input signal is greater than described reverse input signal, the ground GND of the position electric capacity bottom crown that the second capacitor array is corresponding switches to V _rEF;

While comparing the last time, if forward input signal is less than/is greater than reverse input signal, the ground GND of the redundant capacitor of the first/the second capacitor array switches common-mode voltage V _cM, the position electric capacity connection that the second/the first capacitor array is corresponding is constant;

Export the binary code relatively obtaining and convert signal.

Further, described comparator comprises: the first MOS transistor M1, the second MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 8th MOS transistor M8, the 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11, the 12 MOS transistor M12, the 13 MOS transistor M13, the 14 MOS transistor M14, the 15 MOS transistor M15, the 16 MOS transistor M16, the 17 MOS transistor M17, wherein

The drain electrode of described the first MOS transistor M1 is connected with the drain electrode of described the second MOS transistor M2, and the drain electrode of described the first MOS transistor M1 is connected in described comparator the first output signal Voutp;

The source electrode of described the first MOS transistor M1 is connected with the source electrode power supply of described the 3rd MOS transistor M3, the drain electrode of described the 3rd MOS transistor M3 is connected with the drain electrode of described the 4th MOS transistor M4, and the drain electrode of described the 4th MOS transistor M4 is also connected in the grid of described the first MOS transistor M1;

The grid of described the first MOS transistor M1 is connected with the grid of described the second MOS transistor M2, the source electrode of described the second MOS transistor M2 is connected with the source ground of described the 4th MOS transistor M4, and the grid of described the 4th MOS transistor M4 is connected with the grid of described the 3rd MOS transistor M3;

The grid of described the 4th MOS transistor M4 is also connected in the drain electrode of described the 7th MOS transistor M7, and the drain electrode of described the 7th MOS transistor M7 is also connected in the drain electrode of described the 6th MOS transistor M6 and the drain electrode of described the 5th MOS transistor M5;

The grid of described the 5th MOS transistor M5 is connected in comparator second clock control signal CLK, and the source electrode of described the 5th MOS transistor M5 is connected with the source electrode power supply of described the 6th MOS transistor M6;

The grid of described the 6th MOS transistor M6 is connected with the grid of described the 7th MOS transistor M7, and the source electrode of described the 7th MOS transistor M7 is connected with the drain electrode of described the 8th MOS transistor M8;

The grid of described the 8th MOS transistor M8 is connected in the second input VINN of comparator, the anti-phase difference analogue input signal of the second bottom crown V of the second input VINN of described comparator and described the second capacitor array _nbe connected, the source electrode of described the 8th MOS transistor M8 is connected with the source electrode of described the tenth MOS transistor M10, and the source electrode of described the tenth MOS transistor M10 is connected with the drain electrode of described the 9th MOS transistor M9;

The grid of described the 9th MOS transistor M9 is connected in described comparator second clock control signal CLK, and the grounded drain of described the 9th MOS transistor M9 connects;

The grid of described the tenth MOS transistor M10 is connected in the first input end VINP of comparator and the first bottom crown positive difference analogue input signal V of described the first capacitor array described in the first input end VINP of comparator _pbe connected, the drain electrode of described the tenth MOS transistor M10 is connected in the source electrode of described the 11 MOS transistor M11, the drain electrode of described the 11 MOS transistor M11 is connected in the drain electrode of described the 12 MOS transistor M12, the grid of described the 11 MOS transistor M11 is connected in the grid of described the 12 MOS transistor M12, and the grid of described the 12 MOS transistor M12 is connected in the drain electrode of described the 7th MOS transistor M7;

The drain electrode of described the 12 MOS transistor M12 is also connected in the grid of described the 7th MOS transistor M7, and the source electrode of described the 12 MOS transistor M12 is connected with the source electrode power supply of described the 13 MOS transistor M13;

The grid of described the 13 MOS transistor M13 is connected in described comparator second clock control signal CLK, and the drain electrode of described the 13 MOS transistor M13 is connected in the drain electrode of described the 12 MOS transistor M12;

The drain electrode of described the 12 MOS transistor M12 is also connected in the grid of described the 14 MOS transistor M14, and the grid of described the 14 MOS transistor M14 is connected with the grid of described the 15 MOS transistor M15, the source ground of described the 15 MOS transistor M15 connects;

The drain electrode of described the 15 MOS transistor M15 is connected with the drain electrode of described the 14 MOS transistor M14, and the drain electrode of described the 15 MOS transistor M15 is connected in the grid of described the 16 MOS transistor M16, the grid of described the 16 MOS transistor M16 is connected with the grid of described the 17 MOS transistor M17, and the source ground of described the 17 MOS transistor M17 connects;

The drain electrode of described the 17 MOS transistor M17 is connected with the drain electrode of described the 16 MOS transistor M16, and the drain electrode of described the 16 MOS transistor M16 is connected in described comparator the second output signal Voutn, and the source electrode of described the 16 MOS transistor M16 is connected with the source electrode power supply of described the 14 MOS transistor M14.

The beneficial effect of technique scheme of the present invention is as follows:

In the solution of the present invention, by adopting the electric capacity of 9 groups of binary structure to form 10 gradual approaching A/D converters, and last redundant capacitor has been applied to Binary Conversion, saved like this electric capacity of half, saved the area of capacitor array, simultaneously by successively approaching control logic, the switching of controlling the capacitance switch of differential capacitance array selects to connect the switching sequence of voltage, save greatly area and the power consumption of capacitor array, thereby realized the analog to digital converter of 10 super low-power consumptions based on electric charge reallocation.

Accompanying drawing explanation

10 the super low-power consumption gradual approaching A/D converter structured flowcharts of Fig. 1 based on electric charge reallocation;

Fig. 2 is the structure chart that successively approaches logic able to programme in the embodiment of the present invention;

Fig. 3 is the circuit diagram that successively approaches subelement in logic able to programme in the embodiment of the present invention;

Fig. 4 is the circuit diagram of difference capacitor array under 10 super low-power consumption gradual approaching A/D converter mode of operations based on electric charge reallocation;

Fig. 5 is the sequential chart that successively approaches subelement in logic able to programme in the embodiment of the present invention;

Fig. 6 is switching sequence circuit theory diagrams in the embodiment of the present invention;

Fig. 7 is the A part schematic diagram of the switching sequence circuit theory diagrams of Fig. 6;

Fig. 8 is the B part schematic diagram of the switching sequence circuit theory diagrams of Fig. 6;

Fig. 9 is the C part schematic diagram of the switching sequence circuit theory diagrams of Fig. 6;

Figure 10 is the D part schematic diagram of the switching sequence circuit theory diagrams of Fig. 6;

Figure 11 is the circuit diagram of comparator in the embodiment of the present invention.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The invention provides a kind of 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation, the switching of controlling the capacitance switch of described differential capacitance array by successively approaching the output of control logic selects to connect the switching sequence of voltage, area and the power consumption of capacitor array can have been saved greatly, can also pass through last redundant capacitor, be applied in analog-to-digital conversion, thereby saved the electric capacity of half.

As shown in Fig. 1 to 11, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation that the embodiment of the present invention provides, comprising: sampling network, the differential capacitance array being connected with described sampling network, the comparator being connected with described differential capacitance array, be connected with the output of described comparator successively approach control logic; Wherein

Wherein said V _rEFfor supply voltage, common-mode voltage V _cM=V _rEF/ 2, GND is ground voltage.

Wherein above-mentionedly successively approach comparative result and the comparison settling signal that control logic receives comparator, correspondingly switch successively respectively every group of position electric capacity of first, second capacitor array until complete successively approximate procedure, latch simultaneously and export each comparative result, and the bottom crown of all electric capacity is reset to initial value upper while once sampling.

As shown in Figure 1,10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation are by sampling network, differential capacitance array, and comparator, successively approaches control logic and output latch and forms.Above-mentioned sampling network is comprised of bootstrapped switch and differential capacitance array, and wherein said differential capacitance array consists of the capacitance group of full binary structure, and essence is a configurable capacitor type digital to analog converter; Described comparator amplifies latch cicuit by single-stage and forms, for comparing the magnitude of voltage of difference capacitor array, by comparing the voltage of the first capacitor array and the second capacitor array top crown, output comparative result and comparison settling signal; The described control logic of successively approaching, produces the successively approximate procedure that control signal completes analog to digital converter; Output latch latchs and exports and converts the digital output code obtaining, and described output latch unified latching after completing each time sample conversion aforementionedly successively approached the digital code of control logic and output to outside sheet.

For the redundant capacitor (namely last group specific capacitance) that does not participate in actual switching in traditional sequential is used, not only with respect to traditional sequential, saved the electric capacity quantity (area) of half, and saved power consumption.

As shown in Figure 2, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation of another embodiment of the present invention, the described control logic of successively approaching comprises: the shift register being connected with described comparator and be connected d type flip flop DFF with described shift register, the output output of described d type flip flop DFF converts signal EN.

9 sub-units in series connections have formed in fact a shift register, after relatively completing each time, triggering relatively settling signal Valid is uprised by low, and then subelement circuit is to comparator the first output signal Voutp, comparator the second output signal Voutn samples, and produces the first bottom crown switching signal P _i, the second bottom crown switch N _isignal (P _i, N _ithe signal of control capacitance array subordinate switching plate) the lower step control switch that is input to differential capacitance array completes the process of successively approaching.After whole converting, by one of DFF output, convert signal EN, trigger output latch data are latched.

As shown in Figure 2, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation of another embodiment of the present invention, described shift register comprises 9 subelements that are connected in series,

The 4th output of described subelement is all connected with comparator the first output signal Voutp, and the 5th output of described subelement is all connected with comparator the second output signal Voutn;

As shown in Figure 3, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation of another embodiment of the present invention, the described subelement successively approaching in control logic comprises: the 18 MOS transistor M18, the 19 MOS transistor M19, the 20 MOS transistor M20, the 21 MOS transistor M21, the 22 MOS transistor M22, the 23 MOS transistor M23, the 24 MOS transistor M24, the 25 MOS transistor M25, the 26 MOS transistor M26, the 27 MOS transistor M27, the 28 MOS transistor M28, the 29 MOS transistor M29, the 30 MOS transistor M30,

The connected mode that above-mentioned connected mode of approaching control logic just matches in order to realize the switching sequence of this programme, switching sequence of the present invention is to optimize area and the power consumption of capacitor array, and complete design is under control logic is controlled, to produce the sequential of design in side circuit work.For last group specific capacitance, under control logic is controlled, only have two kinds of switching states, be respectively common-mode voltage V _cMor ground GND, cause structure with front 8 groups different, so in order to complete the control of switching sequence of the present invention; it is not only the circuit that approaches control logic of this programme; any control circuit that can complete switching sequence of the present invention, all belongs to protection scope of the present invention, at this, differs one for example.

As shown in Figure 4, in order to improve the sampling linearity, differential capacitance array under the control of sampled signal Sample by bootstrapped switch to forward analog input signal V _pwith inverse analog input signal V _nsample, therefore in 10 moderate rate gradual approaching A/D converters based on electric charge reallocation of another embodiment of the present invention, described the first capacitor array comprises: the first top crown, the first bottom crown and be connected to described the first top crown and described the first bottom crown between the first to the 9th electric capacity being arranged side by side and the capacitance switch connecting one to one with the described first to the 9th electric capacity;

Described the first top crown also connects positive difference analogue input signal V by the first bootstrapped switch K1 of described sampling network _p;

Described the second top crown the second bootstrapped switch K2 by described sampling network connect anti-phase difference analogue input signal V _n;

The first electric capacity (C of wherein said the first capacitor array ₀) capacitance be C, the second electric capacity (C ₁) capacitance equal the first electric capacity (C ₀) capacitance C, the 3rd electric capacity (C ₂) to the 9th electric capacity (C ₈) capacitance be C _i+1=2C _i, wherein, the natural number that i is 1≤i≤7;

The first electric capacity (C of described the second capacitor array ₀') capacitance be C, the second electric capacity (C ₁') capacitance equal the first electric capacity (C ₀') capacitance C, the 3rd electric capacity (C ₂') to the 9th electric capacity (C ₈') capacitance be C _i+ 1 '=2C _i', wherein, the natural number that i is 1≤i≤7.

Under mode of operation, difference capacitor array is comprised of the first capacitor array and the second capacitor array, and first, second capacitor array is by the first capacitor C ₀to the 9th capacitor C ₈, the position electric capacity of totally 9 groups of binary structure forms, wherein the first capacitor C ₀, and the second capacitor C ₁for specific capacitance, the 9th capacitor C ₈to the second capacitor C ₁capacitance size between every group of position electric capacity is successively decreased successively according to the relation of 2 times, the second capacitor C ₁to the 9th capacitor C ₈the bottom crown of position electric capacity passes through inverter controlling by the output that successively approaches control logic.

As shown in Figure 5, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation of another embodiment of the present invention, the switching sequence of described the first capacitor array and described the second capacitor array comprises:

Described the second bootstrapped switch K2 and the second bootstrapped switch K2 align phase difference analogue input signal V _pwith anti-phase difference analogue input signal V _nsample, obtain positive phase input signal and rp input signal;

The switching sequence of described the first capacitor array and described the second capacitor array also comprises:

If forward input signal is less than reverse input signal during first comparison phase, in so follow-up comparison procedure, if forward input signal is less than reverse input signal, the ground (GND) of the position electric capacity bottom crown that the first capacitor array is corresponding switches to supply voltage (V _rEF); If forward input signal is greater than reverse input signal, the position electric capacity bottom crown connection that the second capacitor array is corresponding is constant, and the ground (GND) of the previous position electric capacity bottom crown of corresponding position electric capacity switches to common-mode voltage (V _cM);

When first described forward input signal is greater than described rp input signal, follow-up relatively in, when if forward input signal is less than reverse input signal, the electric capacity bottom crown connection of the corresponding position of described the first capacitor array is constant, and the ground (GND) of the previous position electric capacity bottom crown of corresponding position switches to common-mode voltage (V _cM); When if described forward input signal is greater than described reverse input signal, the ground (GND) of the position electric capacity bottom crown that the second capacitor array is corresponding switches to (V _rEF);

While comparing the last time, if forward input signal is less than/is greater than reverse input signal, the ground of the redundant capacitor of the first/the second capacitor array (GND) switches common-mode voltage (V _cM), the position electric capacity connection that the second/the first capacitor array is corresponding is constant;

Export the binary code relatively obtaining and convert signal.

When sample phase, the signal first bottom crown switching signal P of control capacitance array subordinate switching plate _i, the second bottom crown switching signal N _iand Q (Q is an output port, and Q output signal is to the D input of next electronic circuit) all resets to ground.Current subelement working stage, D node is charged to supply voltage V _rEFthereby the first clock signal clk _ipull down to ground.As comparator the first output signal Voutp, comparator the second output signal Voutn is when effective, and Output rusults is by the first bottom crown switching signal P _i, the second bottom crown switching signal N _inode sample, relatively settling signal Valid uprises simultaneously, and a compare cycle completes.

The performing step of specific embodiments of the invention is as follows.

Described successively approximate procedure mainly comprised as the next stage: sample phase: the bottom crown of differential capacitance array resets to initial value.

The bottom crown of one group of position electric capacity of maximum of first, second capacitor array all meets V _cMthe bottom crown that remains all positions electric capacity meets GND, the top crown of the first capacitor array is sampled to the forward signal of differential input signal by a bootstrapped switch, and the top crown of the second capacitor array is sampled to the reverse signal of differential input signal by another bootstrapped switch;

In first comparison phase: the top crown disconnection of electric capacity is connected with forward, inverse analog input signal, and when forward input signal is less than reverse input signal, one group of position electric capacity bottom crown of the maximum of the first capacitor array is by meeting common-mode voltage V _cMswitch to and meet supply voltage V _rEF, one group of position electric capacity of maximum of the second capacitor array is by meeting common-mode voltage V _cMswitch to ground connection GND; When forward input signal is greater than reverse input signal, one group of position electric capacity bottom crown of the maximum of the second capacitor array is by meeting common-mode voltage V _cMswitch to and meet supply voltage V _rEF, one group of position electric capacity of maximum of the first capacitor array is by meeting common-mode voltage V _cMswitch to ground connection GND;

In follow-up comparison procedure: if forward input signal is less than reverse input signal during first comparison phase, in so follow-up comparison procedure, if forward input signal is less than reverse input signal, the position electric capacity bottom crown that the first capacitor array is corresponding switches to supply voltage V by ground GND _rEF, the position electric capacity connection that the second capacitor array is corresponding is constant; If forward input signal is greater than reverse input signal, the position electric capacity connection that the first capacitor array is corresponding is constant, and the position electric capacity bottom crown connection that the second capacitor array is corresponding is constant, and the previous position electric capacity bottom crown of corresponding position electric capacity switches to common-mode voltage V by ground GND _cM, by that analogy, while comparing the last time, if forward input signal is less than reverse input signal, last specific capacitance of the first capacitor array switches to common-mode voltage V by ground connection GND _cM, the position electric capacity connection that the second capacitor array is corresponding is constant; If forward input signal is greater than reverse input signal, the position electric capacity connection that the first capacitor array is corresponding is constant, and last specific capacitance of the second capacitor array switches to common-mode voltage V by ground connection GND _cM;

If forward input signal is greater than reverse input signal during first comparison phase, in so follow-up comparison procedure, if forward input signal is less than reverse input signal, the position electric capacity bottom crown connection that the first capacitor array is corresponding is constant, and the previous position electric capacity bottom crown of corresponding position electric capacity switches to common-mode voltage V by ground GND _cM, the position electric capacity connection that the second capacitor array is corresponding is constant; If forward input signal is greater than reverse input signal, the position electric capacity connection that the first capacitor array is corresponding is constant, and the position electric capacity bottom crown that the second capacitor array is corresponding switches to supply voltage V by ground GND _rEF, by that analogy, while comparing the last time, if forward input signal is less than reverse input signal, last specific capacitance of the first capacitor array switches to common-mode voltage V by ground connection GND _cM, the position electric capacity connection that the second capacitor array is corresponding is constant; If forward input signal is greater than reverse input signal, the position electric capacity connection that the first capacitor array is corresponding is constant, and last specific capacitance of the second capacitor array switches to common-mode voltage V by ground connection GND _cM;

Complete once successively after approximate procedure, the binary code that output relatively obtains and convert signal, waits for conversion next time.

As shown in Fig. 6 to 10, the realization of specific embodiments of the invention be take 4 bit switch sequential as example explanation, and 4 are successively approached comparison four times.

As shown in Figure 6, the voltage that successively approaches for the first time the connection of comparison the first capacitor array and the second capacitor array does not change, successively approaching for the second time comparison Vip and whether be greater than Vin, is to be greater than if successively approach for the second time comparative result, the 3rd capacitor C of the first capacitor array ₂by common-mode voltage V _cMswitch to ground GND, the 3rd capacitor C of the second capacitor array ₂' by common-mode voltage V _cMswitch to supply voltage V _rEF; If successively approaching for the second time comparative result is to be less than, the 3rd capacitor C of the first capacitor array ₂by common-mode voltage V _cMswitch to supply voltage V _rEF, the 3rd capacitor C of the second capacitor array ₂' by common-mode voltage V _cMswitch to ground GND;

If for the second time successively relatively in Vip be greater than Vin, in successively approaching for the third time relatively, judge whether Vip is greater than 1/2V _rEFwith Vin and, if successively approach for the third time comparative result, be to be greater than, as shown in Figure 7, the second capacitor C of the second capacitor array ₁' by ground GND, switch to supply voltage V _rEF, and follow-up the 4th time relatively in, judge whether Vip is greater than 3/4V _rEFwith Vin and, if successively approach comparative result the 4th time, be to be greater than, the first capacitor C of the second capacitor array ₀' by ground GND, switch to common-mode voltage V _cM; If the 4th time is successively approached comparative result is to be less than, the first capacitor C of the first capacitor array ₀by ground GND, switch to common-mode voltage V _cM;

If for the second time successively relatively in, Vip is greater than Vin, in successively approaching for the third time relatively, judges whether Vip is greater than 1/2V _rEFwith Vin and, if successively approach for the third time comparative result, be to be less than, as shown in Figure 8, the 3rd capacitor C of the first capacitor array ₂by ground GND, switch to common-mode voltage V _cM, at follow-up the 4th time, successively approach in comparative result, judge whether Vip is greater than Vin and 1/4V _eRFand, if successively approach comparative result the 4th time, be to be greater than, the first capacitor C of the second capacitor array ₀' by ground GND, switch to common-mode voltage V _cM; If the 4th time is successively approached comparative result is to be less than, the first electric capacity (C of the first capacitor array ₀) by ground GND, switch to common-mode voltage V _cM;

If for the second time successively relatively in, Vip is less than Vin, in successively approaching for the third time relatively, judges whether Vip is greater than Vin and 1/2V _rEFpoor, if successively approach for the third time comparative result, be to be greater than, as shown in Figure 9, the 3rd capacitor C of the second capacitor array ₂' by ground GND, switch to common-mode voltage V _cM, follow-up the 4th time relatively in, judge whether Vip is greater than Vin and 1/4V _rEFpoor, if successively approach comparative result the 4th time, be to be greater than, the first capacitor C of the second capacitor array ₀' ground GND switch to common-mode voltage V _cM; If the 4th time is successively approached comparative result is to be less than, the first capacitor C of the first capacitor array ₀ground GND switch to common-mode voltage V _cM;

If for the second time successively relatively in, Vip is less than Vin, in successively approaching for the third time relatively, judges whether Vip is greater than Vin and 1/2V _rEFpoor, if successively approach for the third time comparative result, be to be less than, as shown in figure 10, the second capacitor C of the first capacitor array ₁by ground GND, switch to supply voltage V _rEFif, follow-up the 4th time successively relatively in, whether Vip is greater than Vin and 3/4V _rEFpoor, if successively approach comparative result the 4th time, be to be greater than, the first capacitor C of the second capacitor array ₀' by ground GND, switch to common-mode voltage V _cM; If the 4th time is successively approached comparative result is to be less than, the first capacitor C of the first capacitor array ₀by ground GND, switch to common-mode voltage V _cM.

As shown in figure 11, in 10 super low-power consumption gradual approaching A/D converters based on electric charge reallocation, described comparator comprises: the first MOS transistor M1, the second MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 8th MOS transistor M8, the 9th MOS transistor M9, the tenth MOS transistor M10, the 11 MOS transistor M11, the 12 MOS transistor M12, the 13 MOS transistor M13, the 14 MOS transistor M14, the 15 MOS transistor M15, the 16 MOS transistor M16, the 17 MOS transistor M17, wherein

The present invention adopts simple low-power latch-type comparator, and in order to improve the linearity, amplifier section adopts the biasing of constant current tail current source, and by second clock control signal CLK, when comparator is not worked, power cutoff arrives the path on ground, thereby has reduced quiescent dissipation.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. 10 super low-power consumption gradual approaching A/D converters of reallocating based on electric charge, it is characterized in that, comprising: sampling network, the differential capacitance array being connected with described sampling network, the comparator being connected with described differential capacitance array, be connected with the output of described comparator successively approach control logic; Wherein

Described the first capacitor array and described the second capacitor array form by the electric capacity of 9 groups of binary structure, and the bottom crown of the redundant capacitor of wherein said the first capacitor array and the redundant capacitor of described the second capacitor array selects to be connected common-mode voltage (V _cM) or ground (GND), remaining 8 groups of capacitance selection connects common-mode voltage (V _cM), supply voltage (V _rEF) or ground (GND);

2. 10 super low-power consumption gradual approaching A/D converters according to claim 1, it is characterized in that, the described control logic of successively approaching comprises: the shift register being connected with described comparator and be connected d type flip flop (DFF) with described shift register, the output output of described d type flip flop (DFF) converts signal (EN).

3. 10 super low-power consumption gradual approaching A/D converters according to claim 2, its tagged word is, described shift register comprises 9 subelements that are connected in series, the first input end of wherein said subelement is all connected with comparison settling signal (Valid), and the first output of a upper subelement is all connected with the second input of next subelement;

The second input of first subelement and sampled clock signal (Sample) disconnected, the first input end of last subelement is connected in the first input end of described d type flip flop (DFF), and the first output of last subelement is also connected in the second input connection of described d type flip flop (DFF);

The 4th output of described subelement is all connected with comparator the first output signal (Voutp), and the 5th output of described subelement is all connected with comparator the second output signal (Voutn).

4. 10 super low-power consumption gradual approaching A/D converters according to claim 3, its tagged word is, the described subelement successively approaching in control logic comprises: the 18 MOS transistor (M18), the 19 MOS transistor (M19), the 20 MOS transistor (M20), the 21 MOS transistor (M21), the 22 MOS transistor (M22), the 23 MOS transistor (M23), the 24 MOS transistor (M24), the 25 MOS transistor (M25), the 26 MOS transistor (M26), the 27 MOS transistor (M27), the 28 MOS transistor (M28), the 29 MOS transistor (M29), the 30 MOS transistor (M30),

The grid of described the 18 MOS transistor (M18) is connected in the first port (D); The grid of described the 18 MOS transistor (M18) is also connected in the grid of described the 20 MOS transistor (M20);

The source ground of described the 20 MOS transistor (M20) connects, and the drain electrode of described the 20 MOS transistor (M20) is connected in the source electrode of described the 19 MOS transistor (M19);

The grid of described the 19 MOS transistor (M19) is connected in described relatively settling signal (Valid), the drain electrode of described the 19 MOS transistor (M19) is connected in the drain electrode of described the 18 MOS transistor (M18), and described the 18 source electrode of MOS transistor (M18) and the source electrode of described the 21 MOS transistor (M21) are connected in supply voltage (V _rEF);

The grid of described the 21 MOS transistor (M21) is connected in the drain electrode of described the 18 MOS transistor (M18), and the drain electrode of described the 18 MOS transistor (M18) produces the first clock signal (CLK _i);

The grid of described the 21 MOS transistor (M21) is also connected in the grid of described the 23 MOS transistor (M23), the source ground of described the 23 MOS transistor (M23);

The drain electrode of described the 23 MOS transistor (M23) is connected in the drain electrode of described the 22 MOS transistor (M22), the grid of described the 22 MOS transistor (M22) is connected in the grid of described the 19 MOS transistor (M19), and the source electrode of described the 22 MOS transistor (M22) is connected in the drain electrode of described the 21 MOS transistor (M21);

The drain electrode of described the 22 MOS transistor (M22) is connected in the grid of described the 27 MOS transistor (M27), the grid that outputs signal to described the 27 MOS transistor (M27) of the drain electrode of described the 22 MOS transistor (M22), the drain electrode of described the 27 MOS transistor (M27) is connected in the drain electrode of described the 29 MOS transistor (M29), the source ground of described the 29 MOS transistor (M29) connects, the grid of described the 29 MOS transistor (M29) is connected in the drain electrode of described the 18 MOS transistor (M18), the drain electrode of described the 29 MOS transistor (M29) is also connected in described the second bottom crown switching signal (N _i),

The source ground of described the 30 MOS transistor (M30) connects, the grid of described the 30 MOS transistor (M30) is connected in the drain electrode of described the 18 MOS transistor (M18), and the drain electrode of described the 30 MOS transistor (M30) is connected in described the first bottom crown switching signal (P _i), the drain electrode of described the 30 MOS transistor (M30) is also connected in the drain electrode of described the 28 MOS transistor (M28), and the grid of described the 28 MOS transistor (M28) is also connected in the grid of described the 27 MOS transistor (M27);

The source electrode of described the 27 MOS transistor (M27) is connected in the drain electrode of described the 25 MOS transistor (M25), and the grid of described the 25 MOS transistor (M25) is connected in described comparator the first output signal (Voutp);

The source electrode of described the 25 MOS transistor (M25) is connected in the source electrode of described the 26 MOS transistor (M26), the grid of described the 26 MOS transistor (M26) is connected in described comparator the second output signal (Voutn), and the drain electrode of described the 26 MOS transistor (M26) is connected in the source electrode of described the 28 MOS transistor (M28);

The source electrode of described the 26 MOS transistor (M26) is also connected in the drain electrode of described the 24 MOS transistor (M24), and the source electrode of described the 24 MOS transistor (M24) is connected in described supply voltage (V _rEF), the grid of described the 24 MOS transistor (M24) is connected in the drain electrode of described the 18 MOS transistor (M18), wherein, and the natural number that i is 1≤i≤9.

5. 10 moderate rate gradual approaching A/D converters according to claim 4, it is characterized in that, described the first capacitor array comprises: the first top crown, the first bottom crown and be connected to described the first top crown and described the first bottom crown between the first to the 9th electric capacity being arranged side by side and the capacitance switch connecting one to one with the described first to the 9th electric capacity;

Described the first top crown also passes through the first bootstrapped switch (K of described sampling network ₁) connection positive difference analogue input signal (V _p);

Described the second top crown also passes through the second bootstrapped switch (K of described sampling network ₂) connect anti-phase difference analogue input signal (V _n);

Described first bottom crown of described the first capacitor array selects to connect common-mode voltage (V by switch respectively _cM) and ground (GND) and except the redundant capacitor (C of the first capacitor array ₀) other outer electric capacity bottom crowns select connection supply voltage (V by switch _rEF);

Described second bottom crown of described the second capacitor array selects to connect common-mode voltage (V by switch respectively _cM) and ground (GND) and except the redundant capacitor (C of the second capacitor array ₀') other outer electric capacity bottom crowns select connection supply voltage (V by switch _rEF).

6. 10 moderate rate gradual approaching A/D converters according to claim 5, is characterized in that, the first electric capacity (C of described the first capacitor array ₀) capacitance be C, the second electric capacity (C ₁) capacitance equal the first electric capacity (C ₀) capacitance C, the 3rd electric capacity (C ₂) to the 9th electric capacity (C ₈) capacitance be C _i+1=2C _i, wherein, the natural number that i is 1≤i≤7;

The first electric capacity (C of described the second capacitor array ₀') capacitance be C, the second electric capacity (C ₁') capacitance equal the first electric capacity (C ₀') capacitance C, the 3rd electric capacity (C ₂') to the 9th electric capacity (C ₈') capacitance be C _i+1'=2C _i', wherein, the natural number that i is 1≤i≤7.

7. 10 super low-power consumption gradual approaching A/D converters according to claim 6, is characterized in that, the switching sequence of described the first capacitor array and described the second capacitor array comprises:

Described the second bootstrapped switch (K ₂) and the second bootstrapped switch (K ₂) align phase difference analogue input signal (V _p) and anti-phase difference analogue input signal (V _n) sample, obtain positive phase input signal and rp input signal;

Repeatedly more described forward input signal and described rp input signal, when first described forward input signal is less than/is greater than described rp input signal, control the common-mode voltage (V of bottom crown of one group of electric capacity of the maximum capacitor value of the first/the second capacitor array _cM) switch to supply voltage (V _rEF), the common-mode voltage (V of the bottom crown of one group of electric capacity of the maximum capacitor value of described the second/the first capacitor array _cM) switch to (GND).

8. 10 super low-power consumption gradual approaching A/D converters according to claim 7, is characterized in that, the switching sequence of described the first capacitor array and described the second capacitor array also comprises:

Export the binary code relatively obtaining and convert signal.

9. 10 super low-power consumption gradual approaching A/D converters according to claim 6, it is characterized in that, described comparator comprises: the first MOS transistor (M1), the second MOS transistor (M2), the 3rd MOS transistor (M3), the 4th MOS transistor (M4), the 5th MOS transistor (M5), the 6th MOS transistor (M6), the 7th MOS transistor (M7), the 8th MOS transistor (M8), the 9th MOS transistor (M9), the tenth MOS transistor (M10), the 11 MOS transistor (M11), the 12 MOS transistor (M12), the 13 MOS transistor (M13), the 14 MOS transistor (M14), the 15 MOS transistor (M15), the 16 MOS transistor (M16), the 17 MOS transistor (M17), wherein

The drain electrode of described the first MOS transistor (M1) is connected with the drain electrode of described the second MOS transistor (M2), and the drain electrode of described the first MOS transistor (M1) is connected in described comparator the first output signal (Voutp);

The source electrode of described the first MOS transistor (M1) is connected with the source electrode power supply of described the 3rd MOS transistor (M3), the drain electrode of described the 3rd MOS transistor (M3) is connected with the drain electrode of described the 4th MOS transistor (M4), and the drain electrode of described the 4th MOS transistor (M4) is also connected in the grid of described the first MOS transistor (M1);

The grid of described the first MOS transistor (M1) is connected with the grid of described the second MOS transistor (M2), the source electrode of described the second MOS transistor (M2) is connected with the source ground of described the 4th MOS transistor (M4), and the grid of described the 4th MOS transistor (M4) is connected with the grid of described the 3rd MOS transistor (M3);

The grid of described the 4th MOS transistor (M4) is also connected in the drain electrode of described the 7th MOS transistor (M7), and the drain electrode of described the 7th MOS transistor (M7) is also connected in the drain electrode of described the 6th MOS transistor (M6) and the drain electrode of described the 5th MOS transistor (M5);

The grid of described the 5th MOS transistor (M5) is connected in comparator second clock control signal (CLK), and the source electrode of described the 5th MOS transistor (M5) is connected with the source electrode power supply of described the 6th MOS transistor (M6);

The grid of described the 6th MOS transistor (M6) is connected with the grid of described the 7th MOS transistor (M7), and the source electrode of described the 7th MOS transistor (M7) is connected with the drain electrode of described the 8th MOS transistor (M8);

The grid of described the 8th MOS transistor (M8) is connected in second input (VINN) of comparator, the anti-phase difference analogue input signal of the second bottom crown (V of second input (VINN) of described comparator and described the second capacitor array _n) be connected, the source electrode of described the 8th MOS transistor (M8) is connected with the source electrode of described the tenth MOS transistor (M10), and the source electrode of described the tenth MOS transistor (M10) is connected with the drain electrode of described the 9th MOS transistor (M9);

The grid of described the 9th MOS transistor (M9) is connected in described comparator second clock control signal (CLK), and the grounded drain of described the 9th MOS transistor (M9) connects;

The grid of described the tenth MOS transistor (M10) is connected in the first input end (VINP) of the described comparator of first input end (VINP) and the first bottom crown positive difference analogue input signal (V of described the first capacitor array of comparator _p) be connected, the drain electrode of described the tenth MOS transistor (M10) is connected in the source electrode of described the 11 MOS transistor (M11), the drain electrode of described the 11 MOS transistor (M11) is connected in the drain electrode of described the 12 MOS transistor (M12), the grid of described the 11 MOS transistor (M11) is connected in the grid of described the 12 MOS transistor (M12), and the grid of described the 12 MOS transistor (M12) is connected in the drain electrode of described the 7th MOS transistor (M7);

The drain electrode of described the 12 MOS transistor (M12) is also connected in the grid of described the 7th MOS transistor (M7), and the source electrode of described the 12 MOS transistor (M12) is connected with the source electrode power supply of described the 13 MOS transistor (M13);

The grid of described the 13 MOS transistor (M13) is connected in described comparator second clock control signal (CLK), and the drain electrode of described the 13 MOS transistor (M13) is connected in the drain electrode of described the 12 MOS transistor (M12);

The drain electrode of described the 12 MOS transistor (M12) is also connected in the grid of described the 14 MOS transistor (M14), and the grid of described the 14 MOS transistor (M14) is connected with the grid of described the 15 MOS transistor (M15), the source ground of described the 15 MOS transistor (M15) connects;

The drain electrode of described the 15 MOS transistor (M15) is connected with the drain electrode of described the 14 MOS transistor (M14), and the drain electrode of described the 15 MOS transistor (M15) is connected in the grid of described the 16 MOS transistor (M16), the grid of described the 16 MOS transistor (M16) is connected with the grid of described the 17 MOS transistor (M17), and the source ground of described the 17 MOS transistor (M17) connects;

The drain electrode of described the 17 MOS transistor (M17) is connected with the drain electrode of described the 16 MOS transistor (M16), and the drain electrode of described the 16 MOS transistor (M16) is connected in described comparator the second output signal (Voutn), the source electrode of described the 16 MOS transistor (M16) is connected with the source electrode power supply of described the 14 MOS transistor (M14).