CN105375925A - Pseudo-differential capacitive successive approximation register analog-digital converter - Google Patents
Pseudo-differential capacitive successive approximation register analog-digital converter Download PDFInfo
- Publication number
- CN105375925A CN105375925A CN201510853946.7A CN201510853946A CN105375925A CN 105375925 A CN105375925 A CN 105375925A CN 201510853946 A CN201510853946 A CN 201510853946A CN 105375925 A CN105375925 A CN 105375925A
- Authority
- CN
- China
- Prior art keywords
- capacitor array
- electric capacity
- talk
- capacitor
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a pseudo-differential capacitive successive approximation register analog-digital converter. The analog-digital converter comprises a first capacitor array, a second capacitor array, a calibration capacitor array and a comparator, wherein lower-bit-segment sub-capacitor arrays of the first capacitor array keep single-end structures; a higher-bit first-segment sub-capacitor array of the first capacitor array and the second capacitor array construct a differential structure; and the first capacitor array and the second capacitor array construct a pseudo-differential capacitor array in which single ends are combined with the differential structure. In an analog-digital conversion process, a transition code value is formed after completion of a least-significant differential weight bit, thereby realizing differential-single end transition. An output end of the calibration capacitor array is connected with an output end of the second capacitor array through a coupling capacitor, and the calibration capacitor array is used for calibrating mismatch of capacitors in the pseudo-differential capacitor array and the offset of the comparator. Through adoption of the analog-digital converter, the chip area can be saved; self-calibration can be performed; and the conversion accuracy is increased.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of pseudo-differential capacitor type gradually-appoximant analog-digital converter.
Background technology
Gradually-appoximant analog-digital converter (SARADC) is widely used in the fields such as Medical Devices, high-speed data acquistion system, Digital Signal Processing, spectrum analysis, industrial equipment, communication and engine.
Wherein with the important component part of precision and velocity correlation--digital to analog converter (DAC) plays the key effect carrying out two points with reference to voltage (Vref).Pure capacitor type analog to digital converter (CDAC), because its noise is little, makes precision high, and is widely used.
In some in high-precision SARADC application, design generally adopts bridge joint capacitance structure, and object reduces total specific capacitance number and the size of CDAC in SARADC further.
Differential signal has the advantage such as better noise resisting ability, larger dynamic range than single-ended signal, and is used in high-performance analog to digital converter.Existing differential capacitance type gradually-appoximant analog-digital converter has larger area.
The dead resistance of various device and cabling and parasitic capacitance, and the error in industrial manufacturing process, make two times of relations between the electric capacity of CDAC adjacent bit accurate not, significantly limit the raising of SARADC precision.In order to improve CDAC adjacent bit further electric capacity between two times of relations, to realize more high-precision requirement, just need to calibrate it.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of pseudo-differential capacitor type gradually-appoximant analog-digital converter, energy saving chip area, can carry out self calibration, improve conversion accuracy.
For solving the problems of the technologies described above, pseudo-differential capacitor type gradually-appoximant analog-digital converter provided by the invention comprises the first capacitor array, the second capacitor array, calibration capacitance array and comparator.
The output of described first capacitor array is connected to the first input end of described comparator and is connected to common mode electrical level by a diverter switch, the output of described second capacitor array is connected to the second input of described comparator and is connected to common mode electrical level by a diverter switch, the first input end of described comparator and the second input are input anti-phase each other, form pseudo-differential capacitor array by described first capacitor array and described second capacitor array.
Described first capacitor array comprises the first cross-talk capacitor array and more than one low level cross-talk capacitor array, and described first cross-talk capacitor array is that figure place is all higher than each described low level cross-talk capacitor array.
Described first cross-talk capacitor array comprises multidigit electric capacity, each described low level cross-talk capacitor array comprises multidigit electric capacity, the electric capacity figure place of described second capacitor array is than many one of the electric capacity figure place of described first cross-talk capacitor array, and the highest order electric capacity of described second capacitor array is equal with the capacitance size of the described first cross-talk capacitor array of identical bits successively and form difference weight position electric capacity to time bit capacitor; The lowest order electric capacity of described second capacitor array and time bit capacitor equal and opposite in direction.
In analog-digital conversion process, first the analog-to-digital conversion of difference weight position is by turn carried out from the highest order of described first cross-talk capacitor array to lowest order, after the least significant difference point weight position of described first cross-talk capacitor array converts, convert a described least significant difference point weight bit code value to transition code value; When a described least significant difference point weight bit code value is 1, described transition code value makes secondary bit capacitor and lowest order electric capacity all ground connection of described second capacitor array; When a described least significant difference point weight bit code value is 0, described transition code value makes the secondary bit capacitor of described second capacitor array and lowest order electric capacity all connect reference voltage.
After described transition code value converts, formed single-ended weight bit pattern capacitor array by the lowest order electric capacity of described first cross-talk capacitor array and the electric capacity of described low level cross-talk capacitor array and carried out the conversion of single-ended weight position.
Described calibration capacitance array comprises multidigit electric capacity, the output of described calibration capacitance array is connected by coupling capacitance with the output of described second capacitor array, and described calibration capacitance array is used for calibrating the mismatch of the electric capacity of described pseudo-differential capacitor array and the skew of described comparator.
Further improvement is, the top crown of every electric capacity of described first cross-talk capacitor array links together and as electric capacity positive terminal, described electric capacity positive terminal is the output of described first capacitor array, and the bottom crown of every electric capacity of described first cross-talk capacitor array is connected to one in positive input voltage, reference voltage and ground respectively by cutter three throw switch; The top crown of every electric capacity of same described low level cross-talk capacitor array links together, and the bottom crown of every electric capacity of same described low level cross-talk capacitor array is connected to one in positive input voltage, reference voltage and ground respectively by cutter three throw switch; The top crown of every electric capacity of described first cross-talk capacitor array is connected by coupling capacitance with the top crown of every electric capacity of adjacent described low level cross-talk capacitor array, and the top crown of every electric capacity of adjacent each described low level cross-talk capacitor array is also connected by coupling capacitance; The top crown of every electric capacity of described second capacitor array links together and as electric capacity end of oppisite phase, described electric capacity end of oppisite phase is the output of described second capacitor array, and the bottom crown of every electric capacity of described second capacitor array is connected to one in reverse inter-input-ing voltage, reference voltage and ground respectively by cutter three throw switch; The top crown of every electric capacity of described calibration capacitance array links together and as the output of described calibration capacitance array, the bottom crown of every electric capacity of described calibration capacitance array is connected to one in reverse inter-input-ing voltage, reference voltage and ground respectively by cutter three throw switch.
Further improvement is, the first input end of described comparator is normal phase input end, and the second input of described comparator is inverting input; The output of described comparator is connected to control logic circuit, and each described cutter three throw switch and each described diverter switch are controlled by described control logic circuit.
Further improvement is, described first cross-talk capacitor array comprises 6 electric capacity, has a described low level cross-talk capacitor array and described low level cross-talk capacitor array comprises 6 electric capacity, and described calibration capacitance array comprises 7 electric capacity.
Further improvement is, the highest order electric capacity of described first cross-talk capacitor array is followed successively by 32 times of specific capacitances, 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance to the size of lowest order electric capacity; The highest order electric capacity of described low level cross-talk capacitor array is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance to the size of lowest order electric capacity; The highest order electric capacity of described calibration capacitance array is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance to the size of lowest order electric capacity.
Further improvement is, in described first cross-talk capacitor array, selectivity is provided with control capacittance, in each described low level cross-talk capacitor array, selectivity is provided with control capacittance, described second capacitor array selectivity is provided with control capacittance, described calibration capacitance array is provided with control capacittance, and the top crown of each described control capacittance links together with the top crown of corresponding position electric capacity, the bottom crown of each described control capacittance is connected with ground.
Further improvement is, stores in memory the calibration code that the mismatch of the electric capacity of described pseudo-differential capacitor array and the skew of described comparator are calibrated.
Further improvement is, each described calibration code by carrying out Approach by inchmeal measurement and calculating under described control logic circuit is to each described cutter three throw switch and each described diverter switch control.
Further improvement is, described calibration code corresponding to the mismatch of the electric capacity of described pseudo-differential capacitor array comprises: the calibration code that every weight electric capacity of described first cross-talk capacitor array is corresponding, the calibration code that every weight electric capacity of described second capacitor array is corresponding, the calibration code that the difference weight electric capacity of the corresponding position composition of described first cross-talk capacitor array and described second capacitor array is corresponding, and the highest order of the adjacent described low level cross-talk capacitor array of described first cross-talk capacitor array and calibration code corresponding to time high-order weight electric capacity.
Further improvement is, is obtained the control code of corresponding conversion position in analog-digital conversion process by multiple described calibration code, and carries out control formation to everybody analog-to-digital error compensation by the described control code obtained to described calibration capacitance array.
The first cross-talk capacitor array being in highest order of the present invention second capacitor array only with the first capacitor array forms difference analog-to-digital conversion structure, more than the first cross-talk capacitor array one that the electric capacity figure place of the second capacitor array is designed simultaneously, the electric capacity had more is utilized to convert the least significant difference of a first cross-talk capacitor array point weight bit code value to transition code value, by adopting transition code value, identical weight is worth to the lowest order of the second capacitor array and time control realization of bit capacitor and a least significant difference point weight bit code for the first cross-talk capacitor array, thus make the electric capacity of the lowest order lowest order electric capacity of the first cross-talk capacitor array energy and low level cross-talk capacitor array form single-ended weight bit pattern capacitor array and carry out the analog-to-digital conversion of single-ended weight position, so the present invention can realize the transition of difference modes to single-ended mode, be not adopt fully differential structure, relative to fully differential capacitor type gradually-appoximant analog-digital converter, energy saving chip area of the present invention.
High-order section of the present invention adopts differential type structure simultaneously, and can retain the advantage that fully differential capacitor type gradually-appoximant analog-digital converter has, namely the present invention can keep good noise resisting ability and larger dynamic range too.
In addition, the present invention is by arranging calibration capacitance array, can calibrate the mismatch of electric capacity of the difference weight electric capacity of the every single-ended weight electric capacity of the first capacitor array and the second capacitor array and the first capacitor array and the second capacitor array composition and the skew of comparator, two times of relations between analog to digital converter adjacent bit electric capacity can be made more accurate, improve the precision of analog to digital converter.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention pseudo-differential capacitor type gradually-appoximant analog-digital converter circuit diagram;
Fig. 2 is the sample phase circuit diagram of the circuit of the embodiment of the present invention shown in Fig. 1;
Fig. 3 is the highest order translate phase circuit diagram of the circuit of the embodiment of the present invention shown in Fig. 1;
Fig. 4 is high 6 translate phase circuit diagrams of the circuit of the embodiment of the present invention shown in Fig. 1;
Fig. 5 is low 6 translate phase circuit diagrams of the circuit of the embodiment of the present invention shown in Fig. 1.
Embodiment
As shown in Figure 1, be embodiment of the present invention pseudo-differential capacitor type gradually-appoximant analog-digital converter circuit diagram; Embodiment of the present invention pseudo-differential capacitor type gradually-appoximant analog-digital converter comprises the first capacitor array 101, second capacitor array 102, calibration capacitance array 105, comparator (COMP) 103, control logic circuit (SAR & CALLogic) 104 and memory (CALMemory) 106.
The output PX of described first capacitor array 101 is connected to the first input end of described comparator 103 and is connected to common mode electrical level VCM by a switching switch S P, the output NX of described second capacitor array 102 is connected to the second input of described comparator 103 and is connected to common mode electrical level VCM by a switching switch S N, forms pseudo-differential capacitor array by described first capacitor array 101 and described second capacitor array 102.
Described first capacitor array 101 comprises the first cross-talk capacitor array and more than one low level cross-talk capacitor array, and described first cross-talk capacitor array is that figure place is all higher than each described low level cross-talk capacitor array.
Described first cross-talk capacitor array comprises multidigit electric capacity, each described low level cross-talk capacitor array comprises multidigit electric capacity, the electric capacity figure place of described second capacitor array 102 is than many one of the electric capacity figure place of described first cross-talk capacitor array, and the highest order electric capacity of described second capacitor array 102 is equal with the capacitance size of the described first cross-talk capacitor array of identical bits successively and form difference weight position electric capacity to time bit capacitor; The lowest order electric capacity of described second capacitor array 102 and time bit capacitor equal and opposite in direction.
In analog-digital conversion process, first the analog-to-digital conversion of difference weight position is by turn carried out from the highest order of described first cross-talk capacitor array to lowest order, after the least significant difference point weight position of described first cross-talk capacitor array converts, convert a described least significant difference point weight bit code value to transition code value; When a described least significant difference point weight bit code value is 1, described transition code value makes secondary bit capacitor and lowest order electric capacity all ground connection of described second capacitor array 102; When a described least significant difference point weight bit code value is 0, described transition code value makes the secondary bit capacitor of described second capacitor array 102 and lowest order electric capacity all meet reference voltage VREF.
After described transition code value converts, formed single-ended weight bit pattern capacitor array by the lowest order electric capacity of described first cross-talk capacitor array and the electric capacity of described low level cross-talk capacitor array and carried out the conversion of single-ended weight position.
Described calibration capacitance array 105 comprises multidigit electric capacity, the output of described calibration capacitance array 105 is connected by coupling capacitance CNS with the output of described second capacitor array 102, and described calibration capacitance array 105 is calibrated for the mismatch of the electric capacity to described pseudo-differential capacitor array and the skew of described comparator 103.
In the embodiment of the present invention, the top crown of every electric capacity of described first cross-talk capacitor array links together and as electric capacity positive terminal PX, described electric capacity positive terminal PX is the output PX of described first capacitor array 101, and the bottom crown of every electric capacity of described first cross-talk capacitor array is connected to one in positive input voltage VINP, reference voltage VREF and ground respectively by cutter three throw switch.
The top crown of every electric capacity of same described low level cross-talk capacitor array links together, and the bottom crown of every electric capacity of same described low level cross-talk capacitor array is connected to one in positive input voltage VINP, reference voltage VREF and ground respectively by cutter three throw switch; The top crown of every electric capacity of described first cross-talk capacitor array is connected by coupling capacitance CPS with the top crown of every electric capacity of adjacent described low level cross-talk capacitor array, and the top crown of every electric capacity of adjacent each described low level cross-talk capacitor array is also connected by coupling capacitance.
The top crown of every electric capacity of described second capacitor array 102 links together and as electric capacity end of oppisite phase NX, described electric capacity end of oppisite phase NX is the output of described second capacitor array 102, and the bottom crown of every electric capacity of described second capacitor array 102 is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground respectively by cutter three throw switch.
The top crown of every electric capacity of described calibration capacitance array 105 links together and as the output of described calibration capacitance array 105, the bottom crown of every electric capacity of described calibration capacitance array 105 is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground respectively by cutter three throw switch.
The first input end of described comparator 103 is normal phase input end, and the second input of described comparator 103 is inverting input; The output of described comparator 103 is connected to control logic circuit 104, and each described cutter three throw switch and each described diverter switch are controlled by described control logic circuit 104.
In example shown in Fig. 1, described first cross-talk capacitor array comprises 6 electric capacity, be respectively electric capacity CPM6, CPM5, CPM4, CPM3, CPM2 and CPM1, the bottom crown of each electric capacity is connected to one in positive input voltage VINP, reference voltage VREF and ground respectively by cutter three throw switch SPM6, SPM5, SPM4, SPM3, SPM2 and a SPM1.Described first cross-talk capacitor array is also provided with control capacittance CPM0, and the top crown of control capacittance CPM0 connects output PX, bottom crown ground connection.
Have a described low level cross-talk capacitor array and described low level cross-talk capacitor array comprises 6 electric capacity, be respectively electric capacity CPN5, CPN4, CPN3, CPN2, CPN1 and CPN0, the bottom crown of each electric capacity is connected to one in positive input voltage VINP, reference voltage VREF and ground respectively by cutter three throw switch SPN5, SPN4, SPN3, SPN2, SPN1 and a SPN0.
Described second capacitor array 102 includes 7 electric capacity, be respectively electric capacity CNM6, CNM5, CNM4, CNM3, CNM2, CNM1 and CNM0, the bottom crown of each electric capacity is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground respectively by cutter three throw switch SNM6, SNM5, SNM4, SNM3, SNM2, SNM1 and a SNM1.
Described calibration capacitance array comprises 7 electric capacity, be respectively electric capacity CNN5, CNN4, CNN3, CNN2, CNN1, CNC and CNB, the bottom crown of each electric capacity is connected to one in reverse inter-input-ing voltage VINN, reference voltage VREF and ground respectively by cutter three throw switch SNN5, SNN4, SNN3, SNN2, SNN1, SNC and a SNB.Described calibration capacitance array is also provided with control capacittance CNA, and the top crown of control capacittance CNA connects output, the bottom crown ground connection of described calibration capacitance array 105.
The highest order electric capacity of described first cross-talk capacitor array is followed successively by 32 times of specific capacitances (C) i.e. 32C, 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance to the size of lowest order electric capacity, and control capacittance CPM0 is 1 times of specific capacitance;
The highest order electric capacity of described low level cross-talk capacitor array is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance to the size of lowest order electric capacity.
The highest order electric capacity of described calibration capacitance array 105 is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance to the size of lowest order electric capacity, and control capacittance CNA is 1/4 times of specific capacitance.
Coupling capacitance CPS is 32/31 times of specific capacitance, and coupling capacitance CNS is 32/31 times of specific capacitance.
The calibration code that the mismatch of the electric capacity of described pseudo-differential capacitor array and the skew of described comparator 103 are calibrated is stored in memory 106.
Each described calibration code by carrying out Approach by inchmeal measurement and calculating under described control logic circuit 104 is to each described cutter three throw switch and each described diverter switch control.
Described calibration code corresponding to the mismatch of the electric capacity of described pseudo-differential capacitor array comprises: the calibration code that every weight electric capacity of described first cross-talk capacitor array is corresponding, the calibration code that every weight electric capacity of described second capacitor array 102 is corresponding, the calibration code that the difference weight electric capacity of the corresponding position composition of described first cross-talk capacitor array and described second capacitor array 102 is corresponding, and the highest order of the adjacent described low level cross-talk capacitor array of described first cross-talk capacitor array and calibration code corresponding to time high-order weight electric capacity.
In analog-digital conversion process, obtained the control code of corresponding conversion position by multiple described calibration code, and by the described control code obtained, control formation is carried out to everybody analog-to-digital error compensation to described calibration capacitance array 105.
The following describes the course of work of embodiment of the present invention circuit:
The sub-SARADC of calibration of calibration capacitance array 105, comparator 103 and control logic circuit 104 composition, first measure the input offset voltage (OS) of comparator 103, be converted into calibration code DOS with the coded system of bipolarity offset binary, be kept in memory 106.
Regard total sampling capacitance of electric capacity positive terminal PX and electric capacity end of oppisite phase NX as there is no error value Cptot and Cntot respectively, so the specific capacitance ideal value of electric capacity positive terminal PX and electric capacity end of oppisite phase NX is respectively Cptot/64 and Cntot/64, and the ideal value of each weight electric capacity is 2 of specific capacitance ideal value
idoubly (i=-5 ,-4 ..., 5), there is error between each weight electric capacity and its ideal value, all weight capacitance errors and be zero.
Control logic circuit 104 controls SP3T switch i.e. cutter three throw switch in diverter switch SP, SN, described first capacitor array 101 and described second capacitor array 102, produce the voltage signal containing weight electric capacity CPM6 mismatch error information, the sub-SARADC of calibration of calibration capacitance array 105, comparator 103 and control logic circuit 104 composition, measure this voltage again, obtain the coded system measured value DMPM6 with bipolarity offset binary.Calculate the calibration code DCPM6=(DMPM6-DOS)/2 of weight electric capacity CPM6 again, by it stored in memory 106.
Control logic circuit 104 controls the SP3T switch in diverter switch SP, SN, described first capacitor array 101 and described second capacitor array 102, produce the voltage signal containing weight electric capacity CPM5 mismatch error information again, the sub-SARADC of calibration of calibration capacitance array 105, comparator 103 and control logic circuit 104 composition, measure this voltage again, obtain the coded system measured value DMPM5 with bipolarity offset binary.Calculate the calibration code DCPM5=(DMPM5-DOS-DCPM6)/2 of weight electric capacity CPM5 again, by it stored in memory 106.
By that analogy, the code that calibrates for error of weight electric capacity CPM6-CPM1, CPN5, CNM6-CNM1 is obtained successively:
DCPM6＝(DMPM6-DOS)/2
DCPM5＝(DMPM5-DOS-DCPM6)/2
DCPM4＝(DMPM4-DOS-DCPM6-DCPM5)/2
DCPM3＝(DMPM3-DOS-DCPM6-DCPM5-DCPM4)/2
DCPM2＝(DMPM2-DOS-DCPM6-DCPM5-DCPM4-DCPM3)/2
DCPM1＝(DMPM1-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2)/2
DCPN5＝(DMPN5-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2-DCPM1)/2
DCPN4＝(DMPN5-DOS-DCPM6-DCPM5-DCPM4-DCPM3-DCPM2-DCPM1-DCPN4)/2
DCNM6＝(DMNM6-DOS)/2
DCNM5＝(DMNM5-DOS-DCNM6)/2
DCNM4＝(DMNM4-DOS-DCNM6-DCNM5)/2
DCNM3＝(DMNM3-DOS-DCNM6-DCNM5-DCNM4)/2
DCNM2＝(DMNM2-DOS-DCNM6-DCNM5-DCNM4-DCNM3)/2
DCNM1＝(DMNM1-DOS-DCNM6-DCNM5-DCNM4-DCNM3-DCNM2)/2
Calculate the calibration code DCNM0=0-DCNM6-DCNM5-DCNM4-DCNM3-DCNM2-DCNM1 of CNM0
Calculate the calibration code of high 6 potential differences point weight electric capacity:
DCM6＝DCPM6+DCNM6
DCM5＝DCPM5+DCNM5
DCM4＝DCPM4+DCNM4
DCM3＝DCPM3+DCNM3
DCM2＝DCPM2+DCNM2
DCM1＝DCPM1+DCNM1
By calibration code DCM6-DCM1, DCPM1, DCPN5, DCPN4 and DCNM0 stored in memory 106.
As shown in Figure 2, be the sample phase circuit diagram of the circuit of the embodiment of the present invention shown in Fig. 1; In sample phase, switch S P and SN closes, node PX and electric capacity positive terminal PX and node NX and electric capacity end of oppisite phase NX meets VCM, SP3T switch in first capacitor array 101 all meets VINP, SP3T switch in second capacitor array 102 all meets VINN, and differential input signal VINP-VINN is sampled on the weight capacitor array of the first capacitor array 101 and the weight capacitor array of the second capacitor array 102.
The control code DM<6:0> of calibration capacitance array 105 is 1000000.
As shown in Figure 3, be the highest order translate phase circuit diagram of the circuit of the embodiment of the present invention shown in Fig. 1; After starting conversion, switch S P and SN disconnects, control logic circuit 104 meets VREF the SP3T switch S PM6 of the first capacitor array 101, all the other SP3T switches all ground connection of the first capacitor array 101, such meeting is held at node PX and is produced VCM-(VINP-1/2VREF), control logic circuit 104 is the SP3T switch S NM6 ground connection of the second capacitor array 102 simultaneously, all the other SP3T switches of second capacitor array 102 all meet VREF, can hold like this produce VCM-(VINN-1/2VREF) at node NX.
The control code DM<6:0> calibrating sub-DAC105 is DOS+DCM6, the error compensation of comparator 103 offset voltage and difference weight electric capacity CPM6 and CNM6 is fallen.
Comparator comparison node PX holds and the size of node NX end, and namely-(VIP-VIN) is greater than 0 or be less than 0, and the output of comparator 103 is given to control logic circuit 104, also namely obtains D12 code value.
If-(VIP-VIN) be <0, obtain D12=1, SP3T switch S PM6 is met VREF by next step, by SP3T switch S NM6 ground connection, and SP3T switch S PM5 is met VREF, by SP3T switch S NM5 ground connection, namely next change-over period node PX holds and produces VCM-(VINP-1/2VREF), and node NX holds and produces VCM-VIN;
If-(VIP-VIN) be >0, obtain D12=0, next step is by SP3T switch S PM6 ground connection, SP3T switch S NM6 is met VREF, and SP3T switch S PM5 is met VREF, by SP3T switch S NM5 ground connection, namely next change-over period node PX holds and produces VCM-VINP, node NX end generation VCM-(VIN-1/2VREF).
The control code DM<6:0> calibrating sub-DAC105 is DOS+D12*DCM6+DCM5;
Comparator 103 size that comparison node PX holds and node NX holds again, obtains D11 code value, as shown in Figure 4.
As shown in Figure 4, by that analogy, comparator constantly contrasts input, until complete the conversion of difference weight position CPM1 and CNM1, so far the code value of high-order D12-D7 is determined all.
Convert the described least significant difference obtained by differential mode point weight bit code value and D7 to represented by electric capacity CNM0 and CNM1 transition code value below, realize by the transition of differential-to-single-ended structure:
SPM1 is met VREF by next cycle;
If D7=1, SP3T switch S NM0 and SNM1 is met GND, the control code DM<6:0> calibrating sub-DAC105 is DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+DCM1+DCNM 0;
If D7=0, SP3T switch S NM0 and SNM1 is met VREF, the control code DM<6:0> calibrating sub-DAC105 is DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+DCPM1;
Comparator 103 compares input, obtains D6 code value, and namely code value D6 is detected by single ended mode and obtains, as shown in Figure 5.
As shown in Figure 5, then next cycle SP3T switch S PN5 is met VREF
If D6=1, SP3T switch S PM1 is met VREF, the control code DM<6:0> calibrating sub-DAC105 is DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7* (DCM1+DCNM0, DCPM1)+DCPN5;
If D6=0, SP3T switch S PM1 is met GND, the control code DM<6:0> calibrating sub-DAC105 is DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7* (DCM1+DCNM0, DCPM1)-DCPM1+DCPN5.
Comparator compares input, obtains D5 code value.
SP3T switch S PN4 is met VREF by next cycle again;
If D5=1, SP3T switch S PN5 is met VREF;
If D5=0, SP3T switch S PN5 is met GND.
The control code DM<6:0> calibrating sub-DAC105 is:
DOS+D12*DCM6+D11*DCM5+D10*DCM4+D9*DCM3+D8*DCM2+D7*(DCM1+DCNM0,DCPM1)+D6*(0,-DCPM1)+D5*DCPN5+DCPN4；
Comparator 103 compares input, obtains D4 code value.
By that analogy, comparator 103 constantly contrasts input, until complete the conversion of lowest weightings position CPN1, so far the code value of D12-D1 is determined all, and difference Approach by inchmeal analog-to-digital conversion completes.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a pseudo-differential capacitor type gradually-appoximant analog-digital converter, is characterized in that, comprises the first capacitor array, the second capacitor array, calibration capacitance array and comparator;
The output of described first capacitor array is connected to the first input end of described comparator and is connected to common mode electrical level by a diverter switch, the output of described second capacitor array is connected to the second input of described comparator and is connected to common mode electrical level by a diverter switch, the first input end of described comparator and the second input are input anti-phase each other, form pseudo-differential capacitor array by described first capacitor array and described second capacitor array;
Described first capacitor array comprises the first cross-talk capacitor array and more than one low level cross-talk capacitor array, and described first cross-talk capacitor array is that figure place is all higher than each described low level cross-talk capacitor array;
Described first cross-talk capacitor array comprises multidigit electric capacity, each described low level cross-talk capacitor array comprises multidigit electric capacity, the electric capacity figure place of described second capacitor array is than many one of the electric capacity figure place of described first cross-talk capacitor array, and the highest order electric capacity of described second capacitor array is equal with the capacitance size of the described first cross-talk capacitor array of identical bits successively and form difference weight position electric capacity to time bit capacitor; The lowest order electric capacity of described second capacitor array and time bit capacitor equal and opposite in direction;
In analog-digital conversion process, first the analog-to-digital conversion of difference weight position is by turn carried out from the highest order of described first cross-talk capacitor array to lowest order, after the least significant difference point weight position of described first cross-talk capacitor array converts, convert a described least significant difference point weight bit code value to transition code value; When a described least significant difference point weight bit code value is 1, described transition code value makes secondary bit capacitor and lowest order electric capacity all ground connection of described second capacitor array; When a described least significant difference point weight bit code value is 0, described transition code value makes the secondary bit capacitor of described second capacitor array and lowest order electric capacity all connect reference voltage;
After described transition code value converts, formed single-ended weight bit pattern capacitor array by the lowest order electric capacity of described first cross-talk capacitor array and the electric capacity of described low level cross-talk capacitor array and carried out the conversion of single-ended weight position;
Described calibration capacitance array comprises multidigit electric capacity, the output of described calibration capacitance array is connected by coupling capacitance with the output of described second capacitor array, and described calibration capacitance array is used for calibrating the mismatch of the electric capacity of described pseudo-differential capacitor array and the skew of described comparator.
2. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 1, be characterised in that: the top crown of every electric capacity of described first cross-talk capacitor array links together and as electric capacity positive terminal, described electric capacity positive terminal is the output of described first capacitor array, and the bottom crown of every electric capacity of described first cross-talk capacitor array is connected to one in positive input voltage, reference voltage and ground respectively by cutter three throw switch;
The top crown of every electric capacity of same described low level cross-talk capacitor array links together, and the bottom crown of every electric capacity of same described low level cross-talk capacitor array is connected to one in positive input voltage, reference voltage and ground respectively by cutter three throw switch;
The top crown of every electric capacity of described first cross-talk capacitor array is connected by coupling capacitance with the top crown of every electric capacity of adjacent described low level cross-talk capacitor array, and the top crown of every electric capacity of adjacent each described low level cross-talk capacitor array is also connected by coupling capacitance;
The top crown of every electric capacity of described second capacitor array links together and as electric capacity end of oppisite phase, described electric capacity end of oppisite phase is the output of described second capacitor array, and the bottom crown of every electric capacity of described second capacitor array is connected to one in reverse inter-input-ing voltage, reference voltage and ground respectively by cutter three throw switch;
The top crown of every electric capacity of described calibration capacitance array links together and as the output of described calibration capacitance array, the bottom crown of every electric capacity of described calibration capacitance array is connected to one in reverse inter-input-ing voltage, reference voltage and ground respectively by cutter three throw switch.
3. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 2, is characterised in that:
The first input end of described comparator is normal phase input end, and the second input of described comparator is inverting input;
The output of described comparator is connected to control logic circuit, and each described cutter three throw switch and each described diverter switch are controlled by described control logic circuit.
4. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 1 or 2, be characterised in that: described first cross-talk capacitor array comprises 6 electric capacity, have a described low level cross-talk capacitor array and described low level cross-talk capacitor array comprises 6 electric capacity, described calibration capacitance array comprises 7 electric capacity.
5. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 4, is characterised in that: the highest order electric capacity of described first cross-talk capacitor array is followed successively by 32 times of specific capacitances, 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances and 1 times of specific capacitance to the size of lowest order electric capacity;
The highest order electric capacity of described low level cross-talk capacitor array is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance and 1 times of specific capacitance to the size of lowest order electric capacity;
The highest order electric capacity of described calibration capacitance array is followed successively by 16 times of specific capacitances, 8 times of specific capacitances, 4 times of specific capacitances, 2 times of specific capacitances, 1 times of specific capacitance, 1/2 times of specific capacitance and 1/4 times of specific capacitance to the size of lowest order electric capacity.
6. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 1 or 2, be characterised in that: in described first cross-talk capacitor array, selectivity is provided with control capacittance, in each described low level cross-talk capacitor array, selectivity is provided with control capacittance, described second capacitor array selectivity is provided with control capacittance, described calibration capacitance array is provided with control capacittance, and the top crown of each described control capacittance links together with the top crown of corresponding position electric capacity, the bottom crown of each described control capacittance is connected with ground.
7. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 1, is characterised in that: store in memory the calibration code that the mismatch of the electric capacity of described pseudo-differential capacitor array and the skew of described comparator are calibrated.
8. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 7, is characterised in that: each described calibration code by carrying out Approach by inchmeal measurement and calculating under described control logic circuit is to each described cutter three throw switch and each described diverter switch control.
9. pseudo-differential capacitor type gradually-appoximant analog-digital converter as claimed in claim 7, be characterised in that: the described calibration code corresponding to the mismatch of the electric capacity of described pseudo-differential capacitor array comprises: the calibration code that every weight electric capacity of described first cross-talk capacitor array is corresponding, the calibration code that every weight electric capacity of described second capacitor array is corresponding, the calibration code that the difference weight electric capacity of the corresponding position composition of described first cross-talk capacitor array and described second capacitor array is corresponding, the highest order of the described low level cross-talk capacitor array adjacent with described first cross-talk capacitor array and calibration code corresponding to time high-order weight electric capacity.
10. the pseudo-differential capacitor type gradually-appoximant analog-digital converter as described in claim 1 or 8 or 9, be characterised in that: the control code being obtained corresponding conversion position in analog-digital conversion process by multiple described calibration code, and by the described control code obtained, control formation carried out to everybody analog-to-digital error compensation to described calibration capacitance array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510853946.7A CN105375925B (en) | 2015-11-30 | 2015-11-30 | The capacitive gradually-appoximant analog-digital converter of pseudo-differential |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510853946.7A CN105375925B (en) | 2015-11-30 | 2015-11-30 | The capacitive gradually-appoximant analog-digital converter of pseudo-differential |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105375925A true CN105375925A (en) | 2016-03-02 |
| CN105375925B CN105375925B (en) | 2018-10-26 |
Family
ID=55377779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510853946.7A Active CN105375925B (en) | 2015-11-30 | 2015-11-30 | The capacitive gradually-appoximant analog-digital converter of pseudo-differential |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105375925B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374930A (en) * | 2016-09-28 | 2017-02-01 | 东南大学 | Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting |
| CN106896283A (en) * | 2017-02-08 | 2017-06-27 | 上海华虹宏力半导体制造有限公司 | Measure the circuit structure and measuring method of capacitance mismatch characteristic |
| CN107491136A (en) * | 2017-07-06 | 2017-12-19 | 复旦大学 | A kind of difference type capacity regulator for digital calibration |
| CN107888190A (en) * | 2017-12-01 | 2018-04-06 | 西安电子科技大学 | Gradual approaching A/D converter based on asymmetric differential capacitance array |
| CN108599763A (en) * | 2018-05-11 | 2018-09-28 | 成都华微电子科技有限公司 | SAR types ADC is with active amplifier type capacitance redistribution array |
| CN109361392A (en) * | 2018-12-13 | 2019-02-19 | 南京南瑞微电子技术有限公司 | Gradual approaching A/D converter and its weight calibration method |
| CN109802678A (en) * | 2017-11-17 | 2019-05-24 | 比亚迪股份有限公司 | Gradually-appoximant analog-digital converter and its digital calibrating method and device |
| CN109802674A (en) * | 2017-11-17 | 2019-05-24 | 比亚迪股份有限公司 | Gradually-appoximant analog-digital converter and its digital calibrating method and device |
| CN110535467A (en) * | 2019-07-26 | 2019-12-03 | 中国科学院上海微系统与信息技术研究所 | The capacitor array calibration method and device of Step wise approximation pattern analog-to-digital conversion apparatus |
| CN111934689A (en) * | 2020-09-23 | 2020-11-13 | 电子科技大学中山学院 | High-precision analog-to-digital converter and conversion method |
| CN112636757A (en) * | 2020-12-25 | 2021-04-09 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112764447A (en) * | 2021-04-07 | 2021-05-07 | 上海艾为微电子技术有限公司 | Dynamic offset calibration circuit, method, chip and electronic equipment |
| CN113556127A (en) * | 2020-04-23 | 2021-10-26 | 瑞昱半导体股份有限公司 | Digital slope analog-to-digital converter device and signal conversion method |
| CN113794475A (en) * | 2021-11-16 | 2021-12-14 | 杭州深谙微电子科技有限公司 | Calibration method of capacitor array type successive approximation analog-digital converter |
| CN113839673A (en) * | 2021-09-14 | 2021-12-24 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
| WO2023115634A1 (en) * | 2021-12-22 | 2023-06-29 | 重庆吉芯科技有限公司 | Successive-approximation analog-to-digital converter, and comparison method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7532684B2 (en) * | 2005-01-26 | 2009-05-12 | Lockheed Martin Corporation | Direct RF complex analog to digital converter |
| CN101807923A (en) * | 2009-06-12 | 2010-08-18 | 香港应用科技研究院有限公司 | Mixed analog to digital converter (ADC) with binary weighted capacitor sampling array and sub sampling charge distributing array |
| CN104124972A (en) * | 2014-08-08 | 2014-10-29 | 西安电子科技大学 | 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution |
| CN104579348A (en) * | 2015-01-15 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Successive approximation type ADC structure and algorithm |
-
2015
- 2015-11-30 CN CN201510853946.7A patent/CN105375925B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7532684B2 (en) * | 2005-01-26 | 2009-05-12 | Lockheed Martin Corporation | Direct RF complex analog to digital converter |
| CN101807923A (en) * | 2009-06-12 | 2010-08-18 | 香港应用科技研究院有限公司 | Mixed analog to digital converter (ADC) with binary weighted capacitor sampling array and sub sampling charge distributing array |
| CN104124972A (en) * | 2014-08-08 | 2014-10-29 | 西安电子科技大学 | 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution |
| CN104579348A (en) * | 2015-01-15 | 2015-04-29 | 北京华强智连微电子有限责任公司 | Successive approximation type ADC structure and algorithm |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374930B (en) * | 2016-09-28 | 2019-09-03 | 东南大学 | Gradually-appoximant analog-digital converter and D conversion method based on digital calibration |
| CN106374930A (en) * | 2016-09-28 | 2017-02-01 | 东南大学 | Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting |
| CN106896283A (en) * | 2017-02-08 | 2017-06-27 | 上海华虹宏力半导体制造有限公司 | Measure the circuit structure and measuring method of capacitance mismatch characteristic |
| CN106896283B (en) * | 2017-02-08 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | Measure the circuit structure and measurement method of capacitance mismatch characteristic |
| CN107491136A (en) * | 2017-07-06 | 2017-12-19 | 复旦大学 | A kind of difference type capacity regulator for digital calibration |
| CN107491136B (en) * | 2017-07-06 | 2019-10-15 | 复旦大学 | A kind of difference type capacity regulator for digital calibration |
| CN109802678A (en) * | 2017-11-17 | 2019-05-24 | 比亚迪股份有限公司 | Gradually-appoximant analog-digital converter and its digital calibrating method and device |
| CN109802674A (en) * | 2017-11-17 | 2019-05-24 | 比亚迪股份有限公司 | Gradually-appoximant analog-digital converter and its digital calibrating method and device |
| CN107888190B (en) * | 2017-12-01 | 2020-09-25 | 西安电子科技大学 | Successive approximation type analog-digital converter based on asymmetric differential capacitor array |
| CN107888190A (en) * | 2017-12-01 | 2018-04-06 | 西安电子科技大学 | Gradual approaching A/D converter based on asymmetric differential capacitance array |
| CN108599763A (en) * | 2018-05-11 | 2018-09-28 | 成都华微电子科技有限公司 | SAR types ADC is with active amplifier type capacitance redistribution array |
| CN108599763B (en) * | 2018-05-11 | 2022-04-15 | 成都华微电子科技股份有限公司 | SAR type ADC has source operational amplifier type capacitance redistribution array |
| CN109361392A (en) * | 2018-12-13 | 2019-02-19 | 南京南瑞微电子技术有限公司 | Gradual approaching A/D converter and its weight calibration method |
| CN109361392B (en) * | 2018-12-13 | 2022-05-03 | 江苏芯云电子科技有限公司 | Successive approximation type analog-to-digital converter and weight calibration method thereof |
| CN110535467A (en) * | 2019-07-26 | 2019-12-03 | 中国科学院上海微系统与信息技术研究所 | The capacitor array calibration method and device of Step wise approximation pattern analog-to-digital conversion apparatus |
| CN110535467B (en) * | 2019-07-26 | 2023-03-24 | 中国科学院上海微系统与信息技术研究所 | Capacitor array calibration method and device of stepwise approximation type analog-to-digital conversion device |
| CN113556127A (en) * | 2020-04-23 | 2021-10-26 | 瑞昱半导体股份有限公司 | Digital slope analog-to-digital converter device and signal conversion method |
| CN113556127B (en) * | 2020-04-23 | 2024-03-12 | 瑞昱半导体股份有限公司 | Digital slope type analog-digital converter device and signal conversion method |
| CN111934689B (en) * | 2020-09-23 | 2021-07-06 | 电子科技大学中山学院 | High-precision analog-to-digital converter and conversion method |
| CN111934689A (en) * | 2020-09-23 | 2020-11-13 | 电子科技大学中山学院 | High-precision analog-to-digital converter and conversion method |
| CN112636757A (en) * | 2020-12-25 | 2021-04-09 | 上海东软载波微电子有限公司 | Successive approximation type analog-to-digital converter and offset compensation method thereof |
| CN112764447A (en) * | 2021-04-07 | 2021-05-07 | 上海艾为微电子技术有限公司 | Dynamic offset calibration circuit, method, chip and electronic equipment |
| CN113839673A (en) * | 2021-09-14 | 2021-12-24 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
| CN113839673B (en) * | 2021-09-14 | 2023-08-01 | 无锡英迪芯微电子科技股份有限公司 | Novel digital domain self-calibration successive approximation analog-to-digital converter |
| CN113794475A (en) * | 2021-11-16 | 2021-12-14 | 杭州深谙微电子科技有限公司 | Calibration method of capacitor array type successive approximation analog-digital converter |
| WO2023115634A1 (en) * | 2021-12-22 | 2023-06-29 | 重庆吉芯科技有限公司 | Successive-approximation analog-to-digital converter, and comparison method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105375925B (en) | 2018-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105375925A (en) | Pseudo-differential capacitive successive approximation register analog-digital converter | |
| CN104079298A (en) | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure | |
| CN105959006B (en) | Gradual approaching A/D converter calibrates circuit | |
| US4709225A (en) | Self-calibration method for capacitors in a monolithic integrated circuit | |
| US8665125B2 (en) | Electronic device and method for measuring differential non-linearity (DNL) of an SAR ADC | |
| KR101927272B1 (en) | Successive approximation register analog-to-digital converter | |
| CN108574487B (en) | Successive approximation register analog-to-digital converter | |
| US10084470B2 (en) | Analogue-digital converter of non-binary capacitor array with redundant bit and its chip | |
| US8659459B2 (en) | Digital-to-analog converter, analog-to-digital converter including same, and semiconductor device | |
| JP6372102B2 (en) | Analog-digital conversion circuit | |
| CN105375923A (en) | Digital self-calibration circuit and method of successive approximation analog to digital converter | |
| CN108476024B (en) | DAC capacitor array, SAR analog-to-digital converter and method for reducing power consumption | |
| CN101977058A (en) | Sequential approximation analog to digital converter with digital correction and processing method thereof | |
| CN102098048B (en) | Switched-capacitor input circuit and analog-to-digital converter including the same | |
| CN107346975B (en) | SAR type ADC's high accuracy calibrating device | |
| CN104158546A (en) | ADC (Analog to Digital Converter) circuit adopting single-ended conversion successive approximation structure | |
| CN111711453B (en) | Successive approximation type analog-to-digital converter | |
| CN105827245A (en) | Successive approximation type analog-to-digital converter structure | |
| CN105375926A (en) | Pseudo-differential capacitive successive approximation register analog-digital converter | |
| CN109802678B (en) | Successive approximation analog-to-digital converter and digital calibration method and device thereof | |
| CN1671054B (en) | Device and method for low non linearity A-D converter | |
| CN110890889B (en) | SAR ADC dual-comparator offset mismatch calibration method and circuit based on statistics | |
| Chung et al. | A 24μW 12b 1MS/s 68.3 dB SNDR SAR ADC with two-step decision DAC switching | |
| US8576106B2 (en) | Analog-digital converter | |
| CN114614821B (en) | SAR ADC offset error correction method and circuit based on differential structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |