CN115296672B - Sigma delta modulator based on unipolar transistor - Google Patents

Sigma delta modulator based on unipolar transistor Download PDF

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CN115296672B
CN115296672B CN202210938669.XA CN202210938669A CN115296672B CN 115296672 B CN115296672 B CN 115296672B CN 202210938669 A CN202210938669 A CN 202210938669A CN 115296672 B CN115296672 B CN 115296672B
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nmos transistor
pmos transistor
transistor
common point
differential amplifier
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CN115296672A (en
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尹雪梅
徐煜明
严毓培
刘湘君
蒋本福
马维旻
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Zhuhai City Polytechnic
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a sigma delta modulator based on a unipolar transistor, which relates to the technical field of semiconductors and provides a scheme aiming at the sigma delta modulator without the unipolar transistor in the prior art. The sigma delta modulator with the pure NMOS tube or the PMOS tube has the advantages that the sigma delta modulator with the pure NMOS tube or the pure PMOS tube can be manufactured through a plurality of special processes such as a thin film transistor, a gallium nitride process and the like, and the sigma delta modulator meets the design requirements of modern CMOS circuits.

Description

Sigma delta modulator based on unipolar transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a sigma delta modulator based on a unipolar transistor.
Background
Silicon-based complementary metal oxide semiconductor, CMOS, technology is currently the dominant technology and driving force in the integrated circuit industry. Sigma delta modulators are an important circuit block that is widely used in a variety of functional circuits, including the construction of analog-to-digital converters. In the prior art, the sigma delta modulator is provided with an NMOS tube and a PMOS tube at the same time, and a unipolar transistor is not provided. And some special processes such as thin film transistors, gallium nitride processes, etc. are often unipolar transistors, i.e., NMOS or PMOS transistors. For these processes, conventional CMOS circuit design techniques are no longer applicable.
Disclosure of Invention
The present invention is directed to a sigma delta modulator based on unipolar transistors to solve the above-mentioned problems of the prior art.
The invention relates to a sigma delta modulator based on a unipolar transistor, which comprises: the integrator module and the comparator module are electrically connected in sequence, and each of the integrator module and the comparator module comprises a unipolar transistor; the integrator module is used for integrating signals, the comparator module comprises a plurality of differential amplifiers, the differential amplifiers are composed of two stages of circuits, the first stage of circuits are used as main amplifying stages, and the second stage of circuits are used as output buffer stages.
The integrator module comprises eight NMOS transistors, four capacitors and a differential amplifier; the source electrode of the first NMOS transistor is used as a voltage first input end, and the drain electrode of the fourth NMOS transistor is used as a voltage second input end; the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected with a first clock signal phi 1, and the gates of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are connected with a second clock signal phi 2; the source electrode of the sixth NMOS transistor and the drain electrode of the seventh NMOS transistor are grounded at the same point; the common point of the drain electrodes of the first NMOS transistor and the sixth NMOS transistor is connected with the common point of the source electrodes of the fifth NMOS transistor and the second NMOS transistor through a first capacitor, and the common point of the source electrodes of the seventh NMOS transistor and the fourth NMOS transistor is connected with the common point of the drain electrodes of the third NMOS transistor and the eighth NMOS transistor through a second capacitor; the drain electrode of the fifth NMOS transistor is connected with the first input end of the first differential amplifier, and the source electrode of the eighth NMOS transistor is connected with the second input end of the first differential amplifier;
the comparator module comprises three cascaded differential amplifiers, namely a second differential amplifier, a third differential amplifier and a fourth differential amplifier; the drain electrode of the fifth NMOS transistor is in common point with the first output end of the first differential amplifier through the third capacitor and is used as the first input end of the second differential amplifier, and the source electrode of the eighth NMOS transistor is in common point with the second output end of the first differential amplifier through the fourth capacitor and is used as the second input end of the second differential amplifier; the common point of the drain electrode of the second NMOS transistor and the second output end of the fourth differential amplifier is used as a voltage second output end, and the common point of the drain electrode of the third NMOS transistor and the first output end of the fourth differential amplifier is used as a voltage first output end.
The differential amplifier is composed of fourteen NMOS transistors; the grid electrode of the tenth NMOS transistor is used as a third input end of voltage, the drain electrode of the tenth NMOS transistor is connected with the common point of the source electrode of the eleventh NMOS transistor, the grid electrode of the twelfth NMOS transistor and the grid electrode of the twenty-first NMOS transistor, and the source electrode of the tenth NMOS transistor is connected with the common point of the source electrode of the seventeenth NMOS transistor and the drain electrode of the ninth NMOS transistor; the grid electrode of the seventeenth NMOS transistor is connected with the fourth input end of the voltage, and the drain electrode of the seventeenth NMOS transistor is connected with the common point of the source electrode of the nineteenth NMOS transistor, the grid electrode of the twentieth NMOS transistor and the grid electrode of the fourteenth NMOS transistor; the grid electrode of the ninth NMOS transistor is connected with the common point of the grid electrode of the sixteenth NMOS transistor and the input end of the Vb1 interface, and the source electrode of the ninth NMOS transistor is connected with the ground; the drain electrode of the sixteenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor and the source electrode of the twentieth NMOS transistor at the same point, and the source electrode of the sixteenth NMOS transistor is grounded; the drain electrode of the twelfth NMOS transistor and the grid electrode of the nineteenth NMOS transistor are connected with the source electrode of the thirteenth NMOS transistor in a common mode, and the drain electrode of the twentieth NMOS transistor and the grid electrode of the eleventh NMOS transistor are connected with the source electrode of the eighteenth NMOS transistor in a common mode; drain co-points of the fourteenth NMOS transistor and the twenty-first NMOS transistor are connected with drain co-points of the eleventh NMOS transistor and the nineteenth NMOS transistor, are also connected with drain co-points of the thirteenth NMOS transistor and the eighteenth NMOS transistor, and are also connected with grid co-points of the thirteenth NMOS transistor and the eighteenth NMOS transistor; the source electrode of the twenty-first NMOS transistor and the drain electrode of the twenty-second NMOS transistor are connected with a third output end of voltage in a common point manner, and the source electrode of the fourteenth NMOS transistor and the drain electrode of the fifteenth NMOS transistor are connected with a fourth output end of voltage in a common point manner; the grid electrode of the twenty-second NMOS transistor and the grid electrode of the fifteenth NMOS transistor are connected with the input end of the Vb2 interface in a common point manner; the twenty-second NMOS transistor source is grounded, and the fifteenth NMOS transistor source is grounded.
The integrator module comprises eight PMOS transistors, four capacitors and a differential amplifier; the drain electrode of the first PMOS transistor is used as a fifth input end of the voltage, and the source electrode of the fourth PMOS transistor is used as a sixth input end of the voltage; the gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are connected with a third clock signal phi 3, and the gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are connected with a fourth clock signal phi 4; the common point of the drain electrode of the sixth PMOS transistor and the source electrode of the seventh PMOS transistor is grounded; the common point of the sources of the first PMOS transistor and the sixth PMOS transistor is connected with the common point of the drains of the fifth PMOS transistor and the second PMOS transistor through a fifth capacitor, and the common point of the drains of the seventh PMOS transistor and the fourth PMOS transistor is connected with the common point of the sources of the third PMOS transistor and the eighth PMOS transistor through a sixth capacitor; the source electrode of the fifth PMOS transistor is connected with the first input end of the fifth differential amplifier, and the drain electrode of the eighth PMOS transistor is connected with the second input end of the fifth differential amplifier;
the comparator module comprises three cascaded differential amplifiers, namely a sixth differential amplifier, a seventh differential amplifier and an eighth differential amplifier; the source electrode of the fifth PMOS transistor is in common point with the first output end of the fifth differential amplifier through the seventh capacitor and is used as the first input end of the sixth differential amplifier, and the drain electrode of the eighth PMOS transistor is in common point with the second output end of the fifth differential amplifier through the eighth capacitor and is used as the second input end of the sixth differential amplifier; the common point of the source of the second PMOS transistor and the second output terminal of the eighth differential amplifier is used as the sixth output terminal of the voltage, and the common point of the drain of the third PMOS transistor and the first output terminal of the eighth differential amplifier is used as the fifth output terminal of the voltage.
The differential amplifier is composed of fourteen PMOS transistors; the grid electrode of the tenth PMOS transistor is used as a seventh voltage input end, the source electrode of the tenth PMOS transistor is connected with the drain electrode of the eleventh PMOS transistor, the grid electrode of the twelfth PMOS transistor and the grid electrode of the twenty-first PMOS transistor at the same point, and the drain electrode of the tenth PMOS transistor is connected with the drain electrode of the seventeenth PMOS transistor and the source electrode of the ninth PMOS transistor at the same point; a seventeenth PMOS transistor gate is connected to the eighth voltage input terminal, and its source is connected to the common point of the nineteenth PMOS transistor drain, the twentieth PMOS transistor gate and the fourteenth PMOS transistor gate; the grid electrode of the ninth PMOS transistor is connected with the common point of the grid electrode of the sixteenth PMOS transistor and the input end of the Vb3 interface, and the drain electrode of the ninth PMOS transistor is connected with the ground; the source electrode of the sixteenth PMOS transistor is connected with the drain electrode of the twelfth PMOS transistor and the drain electrode of the twentieth PMOS transistor at the same point, and the drain electrode of the sixteenth PMOS transistor is grounded; the source electrode of the twelfth PMOS transistor and the grid electrode of the nineteenth PMOS transistor are connected with the drain electrode of the thirteenth PMOS transistor in a common point manner, and the source electrode of the twentieth PMOS transistor and the grid electrode of the eleventh PMOS transistor are connected with the drain electrode of the eighteenth PMOS transistor in a common point manner; the source common point of the fourteenth PMOS transistor and the twenty-first PMOS transistor is connected with the source common point of the eleventh PMOS transistor and the nineteenth PMOS transistor, is also connected with the source common point of the thirteenth PMOS transistor and the eighteenth PMOS transistor, and is also connected with the grid common point of the thirteenth PMOS transistor and the eighteenth PMOS transistor; the drain electrode of the twenty-first PMOS transistor and the source electrode of the twenty-second PMOS transistor are connected with the seventh output end of the voltage in a common point manner, and the drain electrode of the fourteenth PMOS transistor and the source electrode of the fifteenth PMOS transistor are connected with the eighth output end of the voltage in a common point manner; the grid electrode of the twenty-second PMOS transistor and the grid electrode of the fifteenth PMOS transistor are connected with the input end of the Vb4 interface in a common point manner; the drain of the twenty-second PMOS transistor is grounded, and the drain of the fifteenth PMOS transistor is grounded.
The circuit structure of the differential amplifier is a symmetrical structure.
The sigma delta modulator based on the unipolar transistor has the advantages that the sigma delta modulator of the pure NMOS tube or the PMOS tube can be manufactured through a plurality of special processes such as a thin film transistor, a gallium nitride process and the like, and meets the design requirements of modern CMOS circuits.
Drawings
FIG. 1 is a schematic diagram of a pure n-type circuit of a sigma delta modulator of the present invention;
FIG. 2 is a schematic diagram of a purely n-type circuit of a differential amplifier;
FIG. 3 is a schematic diagram of a pure p-type circuit of the sigma delta modulator of the present invention;
FIG. 4 is a schematic diagram of a purely p-type circuit of a differential amplifier;
fig. 5 is a simplified single-ended equivalent circuit diagram of the integrator module in a second stage.
Detailed Description
As shown in fig. 1, the ΣΔ modulator based on the unipolar transistor according to the present invention includes an integrator module and a comparator module electrically connected in sequence. The present embodiment takes an NMOS transistor as an example. The integrator module comprises eight NMOS transistors, four capacitors and a differential amplifier; the source electrode of the first NMOS transistor T14 is used as a first voltage input end, and the drain electrode of the fourth NMOS transistor T15 is used as a second voltage input end; the gates of the first NMOS transistor T14, the second NMOS transistor T16, the third NMOS transistor T17 and the fourth NMOS transistor T15 are connected with a first clock signal phi 1, and the gates of the fifth NMOS transistor T18, the sixth NMOS transistor T19, the seventh NMOS transistor T20 and the eighth NMOS transistor T21 are connected with a second clock signal phi 2; the source electrode of the sixth NMOS transistor T19 and the drain electrode of the seventh NMOS transistor T20 are grounded at the same point; the common point of the drains of the first NMOS transistor T14 and the sixth NMOS transistor T19 is connected with the common point of the sources of the fifth NMOS transistor T18 and the second NMOS transistor T16 through a first capacitor C11, and the common point of the sources of the seventh NMOS transistor T20 and the fourth NMOS transistor T15 is connected with the common point of the drains of the third NMOS transistor T17 and the eighth NMOS transistor T21 through a second capacitor C12; the drain of the fifth NMOS transistor T18 is connected to the first input terminal of the first differential amplifier DA1, and the source of the eighth NMOS transistor T21 is connected to the second input terminal of the first differential amplifier DA 1. Both the first clock signal Φ1 and the second clock signal Φ2 are two-phase non-overlapping clock signals.
The comparator module comprises three cascaded differential amplifiers, namely a second differential amplifier DA2, a third differential amplifier DA3 and a fourth differential amplifier DA4; the drain electrode of the fifth NMOS transistor T18 is in common point with the first output end of the first differential amplifier DA1 through the third capacitor C21 to serve as a first input end of the second differential amplifier DA2, and the source electrode of the eighth NMOS transistor T21 is in common point with the second output end of the first differential amplifier DA1 through the fourth capacitor C22 to serve as a second input end of the second differential amplifier DA 2; the common point of the drain of the second NMOS transistor T16 and the second output terminal of the fourth differential amplifier DA4 serves as a voltage second output terminal, and the common point of the drain of the third NMOS transistor T17 and the first output terminal of the fourth differential amplifier DA4 serves as a voltage first output terminal.
In operation, the method is divided into two stages. In the first stage, the input Φ1 is at a high level, the input Φ2 is at a low level, the first NMOS transistor T14, the fourth NMOS transistor T15, the second NMOS transistor T16, and the third NMOS transistor T17 are turned on, the fifth NMOS transistor T18, the sixth NMOS transistor T19, the seventh NMOS transistor T20, and the eighth NMOS transistor T21 are turned off, the first capacitor C11 and the second capacitor C12 perform a difference between the input signal and the output signal, and the outputs of the first differential amplifier DA1 and the comparator module are held. In the second stage, the input Φ1 is low, the input Φ2 is high, the fifth NMOS transistor T18, the sixth NMOS transistor T19, the seventh NMOS transistor T20, and the eighth NMOS transistor T21 are turned on, the first NMOS transistor T14, the fourth NMOS transistor T15, the second NMOS transistor T16, and the third NMOS transistor T17 are turned off, and the first differential amplifier DA1 and the comparator module operate to generate new output signals. When the first capacitor C11, the second capacitor C12, the third capacitor C21 and the fourth capacitor C22 have the same value, the input 1 of the first differential amplifier DA1 is made: 1 is added to the output. The response time of the switching circuit is much smaller than the response time of the integrator and the comparator, so that the highest operating rate of the circuit is approximately determined by the delay of the second differential amplifier DA1 and the comparator block.
The differential amplifier is composed of fourteen NMOS transistors. The grid electrode of the tenth NMOS transistor T1 is used as a third input end of voltage, the drain electrode of the tenth NMOS transistor T1 is connected with the common point of the grid electrode of the eleventh NMOS transistor T2, the grid electrode of the twelfth NMOS transistor T3 and the grid electrode of the twenty-first NMOS transistor T12, and the source electrode of the tenth NMOS transistor T8 is connected with the common point of the drain electrode of the ninth NMOS transistor T0; the grid electrode of the seventeenth NMOS transistor T8 is connected with a fourth input end of the voltage, and the drain electrode of the seventeenth NMOS transistor T8 is connected with the common point of the source electrode of the nineteenth NMOS transistor T10, the grid electrode of the twentieth NMOS transistor T11 and the grid electrode of the fourteenth NMOS transistor T5; the grid electrode of the ninth NMOS transistor T0 is connected with the grid electrode of the sixteenth NMOS transistor T7 and the input end of the Vb1 interface at the same point, and the source electrode of the ninth NMOS transistor T0 is connected with the ground; the drain electrode of the sixteenth NMOS transistor T7 is connected with the common point of the source electrode of the twelfth NMOS transistor T3 and the source electrode of the twentieth NMOS transistor T11, and the source electrode is grounded; the drain electrode of the twelfth NMOS transistor T3 and the grid electrode of the nineteenth NMOS transistor T10 are connected with the source electrode of the thirteenth NMOS transistor T4 in a common mode, and the drain electrode of the twentieth NMOS transistor T11 and the grid electrode of the eleventh NMOS transistor T2 are connected with the source electrode of the eighteenth NMOS transistor T9 in a common mode; the drain of the fourteenth NMOS transistor T5 and the twenty-first NMOS transistor T12 are connected to the drain of the eleventh NMOS transistor T2 and the nineteenth NMOS transistor T10 at the same point, are also connected to the drain of the thirteenth NMOS transistor T4 and the eighteenth NMOS transistor T9 at the same point, and are also connected to the gate of the thirteenth NMOS transistor T4 and the eighteenth NMOS transistor T9 at the same point; the source electrode of the twenty-first NMOS transistor T12 and the drain electrode of the twenty-second NMOS transistor T13 are connected with a third output end of voltage in a common point manner, and the source electrode of the fourteenth NMOS transistor T5 and the drain electrode of the fifteenth NMOS transistor T6 are connected with a fourth output end of voltage in a common point manner; the grid electrode of the twenty-second NMOS transistor T13 and the grid electrode of the fifteenth NMOS transistor T6 are connected with the input end of the Vb2 interface at the same point; the source of the twenty-second NMOS transistor T13 is grounded, and the source of the fifteenth NMOS transistor T6 is grounded.
The differential amplifier is composed of two stages of circuits, wherein the first stage of circuit is used as a main amplifying stage and adopts a positive feedback structure. The second stage circuit acts as an output buffer stage and adjusts the output common mode level. First stage circuit gain A 1 The method comprises the following steps:
Figure GDA0004146469390000061
the tenth and eleventh NMOS transistors T1 and T2 are sized larger and biased at a lower overdrive voltage to maximize gm1, thereby improving gain. g m1 Transconductance g for tenth NMOS transistor T1 m2 Is the eleventh NMOS transistor T2 transconductance, r o1 Is the output impedance, r, of the tenth NMOS transistor T1 o2 Is the output impedance of the eleventh NMOS transistor T2.
When the twelfth NMOS transistor T3 and the thirteenth NMOS transistor T4 are the same in size, W/L is the same.
Figure GDA0004146469390000062
Obtaining feedback coefficient A f ＝1。
The second stage circuit gain is:
Figure GDA0004146469390000063
g m5 transconductance g of fourteenth NMOS transistor T5 m6 Transconductance r for fifteenth NMOS transistor T6 o5 Is the output impedance, r, of the fourteenth NMOS transistor T5 o6 Is the output impedance of the fifteenth NMOS transistor T6. SelectingThe output level can be adjusted to VDD/2 by selecting the appropriate device size and inputting the Vb2 value at the Vb2 interface. The second stage circuit may reduce output impedance and may also act as an output buffer. The second stage circuit has a pole frequency much higher than the first stage circuit because its output impedance is much smaller than that of the first stage circuit. Thus, a single pole approximation can be made for the differential amplifier, i.e., the main pole is located at the first stage circuit output node.
The bandwidth BW of the differential amplifier is determined by the RC constant of the first stage circuit output node X, according to the single-pole approximation:
Figure GDA0004146469390000064
wherein C is X Representing the total equivalent capacitance of the X node. The unity gain bandwidth/gain-bandwidth product GBW of the amplifier is:
Figure GDA0004146469390000065
since the second stage circuit acts as an output buffer, the bias current is much greater than that of the first stage circuit, so the slew rate SR of the differential amplifier is approximately determined by the first stage circuit:
Figure GDA0004146469390000071
wherein I is VDD1 Representing the bias current of the first stage.
Fig. 5 is a simplified single-ended equivalent circuit diagram of the integrator module in a second stage.
The closed loop gain is: 1/β= (c11+c21)/C21
Wherein, beta is a feedback coefficient. Therefore, the small signal bandwidth of the integrator module is:
BW int，small ＝GBW×β
since c11=c21 is taken, BW int,small ＝GBW/2。
The large signal bandwidth of the integrator module is:
Figure GDA0004146469390000072
SW is the output swing of the differential amplifier.
Small signal bandwidth of comparator module:
Figure GDA0004146469390000073
where BW is the 3dB bandwidth of a single stage differential amplifier. The following steps are obtained:
BW comp,small ＝0.51BW
the large signal bandwidth of the comparator module is:
Figure GDA0004146469390000074
wherein the former term of the denominator represents the response of the first two stages and the latter term represents the response of the third stage.
Therefore, the highest operating frequency of the ΣΔ modulator is:
Figure GDA0004146469390000075
further, the ΣΔ modulator bandwidth may be calculated as:
Figure GDA0004146469390000076
where OSR is the oversampling rate.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.

Claims (4)

1. A unipolar transistor based ΣΔ modulator comprising: the device comprises an integrator module and a comparator module which are electrically connected in sequence, and is characterized in that the integrator module and the comparator module comprise unipolar transistors; the integrator module is used for integrating signals, the comparator module comprises a plurality of differential amplifiers, the differential amplifiers are composed of two stages of circuits, the first stage of circuits are used as main amplifying stages, and the second stage of circuits are used as output buffer stages;
the integrator module comprises eight NMOS transistors, four capacitors and a differential amplifier; the source electrode of the first NMOS transistor (T14) is used as a voltage first input end, and the drain electrode of the fourth NMOS transistor (T15) is used as a voltage second input end; the gates of the first NMOS transistor (T14), the second NMOS transistor (T16), the third NMOS transistor (T17) and the fourth NMOS transistor (T15) are connected with a first clock signal phi 1, and the gates of the fifth NMOS transistor (T18), the sixth NMOS transistor (T19), the seventh NMOS transistor (T20) and the eighth NMOS transistor (T21) are connected with a second clock signal phi 2; the source of the sixth NMOS transistor (T19) and the drain of the seventh NMOS transistor (T20) are grounded at the same point; the common point of the drains of the first NMOS transistor (T14) and the sixth NMOS transistor (T19) is connected with the common point of the sources of the fifth NMOS transistor (T18) and the second NMOS transistor (T16) through a first capacitor (C11), and the common point of the sources of the seventh NMOS transistor (T20) and the fourth NMOS transistor (T15) is connected with the common point of the drains of the third NMOS transistor (T17) and the eighth NMOS transistor (T21) through a second capacitor (C12); the drain electrode of the fifth NMOS transistor (T18) is connected with the first input end of the first differential amplifier (DA 1), and the source electrode of the eighth NMOS transistor (T21) is connected with the second input end of the first differential amplifier (DA 1);
the comparator module comprises three cascaded differential amplifiers, namely a second differential amplifier (DA 2), a third differential amplifier (DA 3) and a fourth differential amplifier (DA 4); the drain electrode of the fifth NMOS transistor (T18) is used as a first input end of the second differential amplifier (DA 2) through the common point of the third capacitor (C21) and the first output end of the first differential amplifier (DA 1), and the source electrode of the eighth NMOS transistor (T21) is used as a second input end of the second differential amplifier (DA 2) through the common point of the fourth capacitor (C22) and the second output end of the first differential amplifier (DA 1); the common point of the drain electrode of the second NMOS transistor (T16) and the second output end of the fourth differential amplifier (DA 4) is used as a voltage second output end, and the common point of the drain electrode of the third NMOS transistor (T17) and the first output end of the fourth differential amplifier (DA 4) is used as a voltage first output end;
the differential amplifier is composed of fourteen NMOS transistors; a grid electrode of the tenth NMOS transistor (T1) is used as a third input end of voltage, a drain electrode of the tenth NMOS transistor is connected with a common point of a source electrode of the eleventh NMOS transistor (T2), a grid electrode of the twelfth NMOS transistor (T3) and a grid electrode of the twenty-first NMOS transistor (T12), and a source electrode of the tenth NMOS transistor (T8) is connected with a drain electrode common point of the ninth NMOS transistor (T0); a seventeenth NMOS transistor (T8) has a gate connected to the fourth input terminal of the voltage, and a drain connected to a common point of the source of the nineteenth NMOS transistor (T10), the gate of the twentieth NMOS transistor (T11), and the gate of the fourteenth NMOS transistor (T5); the grid electrode of the ninth NMOS transistor (T0) is connected with the grid electrode of the sixteenth NMOS transistor (T7) and the input end of the Vb1 interface at the same point, and the source electrode of the ninth NMOS transistor is connected with the ground; the drain electrode of the sixteenth NMOS transistor (T7) is connected with the common point of the source electrode of the twelfth NMOS transistor (T3) and the source electrode of the twentieth NMOS transistor (T11), and the source electrode of the sixteenth NMOS transistor is grounded; the drain electrode of the twelfth NMOS transistor (T3) and the grid electrode of the nineteenth NMOS transistor (T10) are connected with the source electrode of the thirteenth NMOS transistor (T4) in a common mode, and the drain electrode of the twentieth NMOS transistor (T11) and the grid electrode of the eleventh NMOS transistor (T2) are connected with the source electrode of the eighteenth NMOS transistor (T9) in a common mode; the drain of the fourteenth NMOS transistor (T5) and the drain of the twenty-first NMOS transistor (T12) are connected with the drain common point of the eleventh NMOS transistor (T2) and the nineteenth NMOS transistor (T10), are also connected with the drain common point of the thirteenth NMOS transistor (T4) and the eighteenth NMOS transistor (T9), and are also connected with the grid common point of the thirteenth NMOS transistor (T4) and the eighteenth NMOS transistor (T9); the source electrode of the twenty-first NMOS transistor (T12) and the drain electrode of the twenty-second NMOS transistor (T13) are connected with a third output end of voltage in a common point manner, and the source electrode of the fourteenth NMOS transistor (T5) and the drain electrode of the fifteenth NMOS transistor (T6) are connected with a fourth output end of voltage in a common point manner; the grid electrode of the twenty-second NMOS transistor (T13) and the grid electrode of the fifteenth NMOS transistor (T6) are connected with the input end of the Vb2 interface at the same point; the source of the twenty-second NMOS transistor (T13) is grounded, and the source of the fifteenth NMOS transistor (T6) is grounded.
2. The delta sigma modulator of claim 1 wherein the differential amplifier circuit is symmetrical.
3. A unipolar transistor based ΣΔ modulator comprising: the device comprises an integrator module and a comparator module which are electrically connected in sequence, and is characterized in that the integrator module and the comparator module comprise unipolar transistors; the integrator module is used for integrating signals, the comparator module comprises a plurality of differential amplifiers, the differential amplifiers are composed of two stages of circuits, the first stage of circuits are used as main amplifying stages, and the second stage of circuits are used as output buffer stages;
the integrator module comprises eight PMOS transistors, four capacitors and a differential amplifier; the drain electrode of the first PMOS transistor (T22) is used as a fifth input end of the voltage, and the source electrode of the fourth PMOS transistor (T23) is used as a sixth input end of the voltage; the gates of the first PMOS transistor (T22), the second PMOS transistor (T24), the third PMOS transistor (T25) and the fourth PMOS transistor (T23) are connected with a third clock signal phi 3, and the gates of the fifth PMOS transistor (T26), the sixth PMOS transistor (T27), the seventh PMOS transistor (T28) and the eighth PMOS transistor (T29) are connected with a fourth clock signal phi 4; the common point of the drain electrode of the sixth PMOS transistor (T27) and the source electrode of the seventh PMOS transistor (T28) is grounded; the common point of the sources of the first PMOS transistor (T22) and the sixth PMOS transistor (T27) is connected with the common point of the drains of the fifth PMOS transistor (T26) and the second PMOS transistor (T24) through a fifth capacitor (C13), and the common point of the drains of the seventh PMOS transistor (T28) and the fourth PMOS transistor (T23) is connected with the common point of the sources of the third PMOS transistor (T25) and the eighth PMOS transistor (T29) through a sixth capacitor (C14); a source electrode of the fifth PMOS transistor (T26) is connected with a first input end of the fifth differential amplifier (DA 5), and a drain electrode of the eighth PMOS transistor (T29) is connected with a second input end of the fifth differential amplifier (DA 5);
the comparator module comprises three cascaded differential amplifiers, namely a sixth differential amplifier (DA 6), a seventh differential amplifier (DA 7) and an eighth differential amplifier (DA 8); the source electrode of the fifth PMOS transistor (T26) is used as the first input end of the sixth differential amplifier (DA 6) through the common point of the seventh capacitor (C23) and the first output end of the fifth differential amplifier (DA 5), and the drain electrode of the eighth PMOS transistor (T29) is used as the second input end of the sixth differential amplifier (DA 6) through the common point of the eighth capacitor (C24) and the second output end of the fifth differential amplifier (DA 5); a common point of the source of the second PMOS transistor (T24) and the second output end of the eighth differential amplifier (DA 8) is used as a voltage sixth output end, and a common point of the drain of the third PMOS transistor (T25) and the first output end of the eighth differential amplifier (DA 8) is used as a voltage fifth output end;
the differential amplifier is composed of fourteen PMOS transistors; a grid electrode of the tenth PMOS transistor (T31) is used as a seventh input end of voltage, a source electrode of the tenth PMOS transistor is connected with a drain electrode of the eleventh PMOS transistor (T32), a grid electrode of the twelfth PMOS transistor (T33) and a grid electrode of the twenty-first PMOS transistor (T41) at the same point, and a drain electrode of the tenth PMOS transistor is connected with a drain electrode of the seventeenth PMOS transistor (T40) and a source electrode of the ninth PMOS transistor (T38) at the same point; a seventeenth PMOS transistor (T40) has a gate connected to the eighth input terminal of the voltage and a source connected to the common point of the drain of the nineteenth PMOS transistor (T39), the gate of the twentieth PMOS transistor (T35) and the gate of the fourteenth PMOS transistor (T43); a grid electrode of the ninth PMOS transistor (T38) is connected with a grid electrode of the sixteenth PMOS transistor (T37) and an input end of the Vb3 interface at the same point, and a drain electrode of the ninth PMOS transistor is connected with the ground; a source electrode of the sixteenth PMOS transistor (T37) is connected with a drain electrode of the twelfth PMOS transistor (T33) and a drain electrode of the twentieth PMOS transistor (T35) in a common point, and a drain electrode of the sixteenth PMOS transistor is grounded; a source electrode of the twelfth PMOS transistor (T33) and a grid electrode of the nineteenth PMOS transistor (T39) are connected with a drain electrode of the thirteenth PMOS transistor (T34) in a common point manner, and a source electrode of the twentieth PMOS transistor (T35) and a grid electrode of the eleventh PMOS transistor (T32) are connected with a drain electrode of the eighteenth PMOS transistor (T36) in a common point manner; the source common point of the fourteenth PMOS transistor (T43) and the twenty-first PMOS transistor (T41) is connected with the source common point of the eleventh PMOS transistor (T32) and the nineteenth PMOS transistor (T39), is also connected with the source common point of the thirteenth PMOS transistor (T34) and the eighteenth PMOS transistor (T36), and is also connected with the grid common point of the thirteenth PMOS transistor (T34) and the eighteenth PMOS transistor (T36); the drain electrode of the twenty-first PMOS transistor (T41) and the source electrode of the twenty-second PMOS transistor (T42) are connected with a voltage seventh output end in a common point manner, and the drain electrode of the fourteenth PMOS transistor (T43) and the source electrode of the fifteenth PMOS transistor (T44) are connected with a voltage eighth output end in a common point manner; the grid electrode of the twenty-second PMOS transistor (T42) and the grid electrode of the fifteenth PMOS transistor (T44) are connected with the input end of the Vb4 interface at the same point; the drain of the twenty-second PMOS transistor (T42) is grounded, and the drain of the fifteenth PMOS transistor (T44) is grounded.
4. The delta sigma modulator of claim 2 wherein the differential amplifier circuit is symmetrical.
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