CN106941345A - D type flip flop and asynchronous gradual approaching A/D converter - Google Patents
D type flip flop and asynchronous gradual approaching A/D converter Download PDFInfo
- Publication number
- CN106941345A CN106941345A CN201710160382.8A CN201710160382A CN106941345A CN 106941345 A CN106941345 A CN 106941345A CN 201710160382 A CN201710160382 A CN 201710160382A CN 106941345 A CN106941345 A CN 106941345A
- Authority
- CN
- China
- Prior art keywords
- signal
- input
- type flip
- flip flop
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
Abstract
The present invention provides a kind of d type flip flop and asynchronous gradual approaching A/D converter, the d type flip flop, including reset terminal f, clock end CK, signal input part D and signal output part Q, wherein d type flip flop is resetted when reset terminal f is effective, clock end CK is invalid, after reset state is exited, when clock end CK occurs for the first time effectively, the signal input part D signals inputted are latched, so that the signal of signal output part Q outputs remains identical with the signal latched, until d type flip flop is resetted again.Asynchronous gradual approaching A/D converter is by using d type flip flop of the present invention in the present invention, the design difficulty of logic switch controller can be reduced, the area of chip is saved, the switching rate of gradual approaching A/D converter is improved, it is to avoid the problem of electric capacity sets up unstable occur.
Description
Technical field
The invention belongs to modulus hybrid-intergated-circuit technique field, and in particular to a kind of d type flip flop and asynchronous Approach by inchmeal
Pattern number converter.
Background technology
It is high-effect, low with the development of the systems such as radio sensing network, portable set, wearable medical monitoring equipment
The demand of power consumption analog-digital converter is increasing.Gradual approaching A/D converter is because its is simple in construction, low in energy consumption, digitlization journey
The advantages of spending high, has been widely used in low-power consumption field.But traditional gradual approaching A/D converter is gradually forced because of it
Nearly register is by d type flip flop tandem working, therefore the time delay caused have compressed building for Charge scaling type digital analog converter
Between immediately, the overall performance of analog-digital converter have impact on so that further improving conventional successive approach type analog-digital converter becomes
It is difficult.
At present, the structured flowchart of traditional gradual approaching A/D converter is as shown in Figure 1.Its Approach by inchmeal shift LD
Device is mainly composed in series by two row's d type flip flops, and the d type flip flop DFF1 of first row is used to realize phase shift function, and second row D is touched
Sending out device DFF2 is used for latched digital output signal.D type flip flop DFF1 r ends are reset terminal, when r terminal voltages are high level, signal
Output end Q voltages set is into low level；When r terminal voltages are low level, the d type flip flop DFF1 clocks end CK is receiving rising
Along when, input a signal into end D level be latched into signal output part Q.D type flip flop DFF2 r ends are reset terminal, when r terminal voltages
For high level, signal output part Q voltages set is into low level；When r terminal voltages are low level, the d type flip flop DFF2 clocks end
The level that CK inputs a signal into end D when receiving rising edge, equally is latched into output end Q.First row d type flip flop DFF1's is defeated
Go out end with second row d type flip flop DFF2 clock end to be connected.
Fig. 2 is the overall timing diagram of conventional successive approach type analog-digital converter.When sampled signal Cks is high level, input
Signal Vin and Vip are sampled capacitor type digital analog converter.Meanwhile, first row d type flip flop DFF1 reset, signal output part Q according to
The phase shift signal clkN to clk1 of secondary generation is changed into low level；Second row d type flip flop DFF2 resets, signal output part Q productions
Raw digital output signal DNTo D1It is changed into low level.Sampled signal Cks is changed into low level, and sampling terminates, meanwhile, all D triggerings
Device exits reset state.Now, nor gate NOR three inputs are all low level, the enable signal EN_ of its output end output
Comp is changed into high level, and comparator starts to compare for the first time after the enable signal EN_Comp of high level is received.The ratio
After completing first time relatively compared with device, compare completion signal Rdy and high level is changed into from low level, phase shift signal clkN is by low electricity
It is flat to become high level.The comparative result Op of d type flip flop DFF2 inputs is latched into output by phase shift signal clkN rising edges
Hold as digital output results DN.Compare completion signal Rdy to be changed into after high level, comparator enables signal EN_Comp and is changed into low electricity
Flat, comparator resets, and compares completion signal Rdy and becomes low level again.Signal EN_Comp, which is enabled, in comparator is changed into low electricity again
Before flat, digital output results DNTo D1Control logic switch controller produces capacitance control signal, turns electric capacity reallocation type digital-to-analogue
Parallel operation is according to capacitance control signal, and producing Approach by inchmeal analog signal is used to compare for the second time.Carried out by this rule after n times, the
Two row's d type flip flop DFF2 latch output digital output signal DNTo D1.Phase shift signal clk1 is changed into high level from low level,
The comparator enters reset state and is always maintained at.When sampled signal Cks is changed into high level again, start to turn next time
Change.
By upper analysis, the schematic diagram of the single compares cycle of conventional successive approach type analog-digital converter is as shown in Figure 3.Its loop
Time is：
Tloop=Tcomp+Tnand+Tdff1+Tdff2+Tswitch+TDAC (1)
Wherein TcompRepresent comparator delay, TnandRepresent nor gate delay, Tdff1The delay of first row d type flip flop is represented,
Tdff2Represent the delay of second row d type flip flop, TswitchRepresent logic switch delaying time of controller, TDACRepresent digital analog converter delay；
Its successive approximation register is delayed：
TSAR=Tdff1+Tdff2 (2)
By the analysis to conventional successive approach type analog-digital converter operation principle and delay, at least there is following two lack
Point：
1. often approach one, successive approximation register delay TSAR.For N successive approximation registers, it is necessary to time delay
For N × TSAR.Reduce the switching rate of whole analog-digital converter.
2. for high speed gradual approaching A/D converter, in successive approximation register delay TSARLarger situation
Under, keep for the setup time T of electric capacity reallocation type digital analog converterDACIt is shorter.Particularly in first compares cycle, most
Setup time wretched insufficiency needed for high-order electric capacity change state.Therefore, when comparator works, easily there is electric capacity reallocation
Type digital analog converter sets up incomplete situation, so that the result of comparator output error.
The content of the invention
The present invention provides a kind of d type flip flop and asynchronous gradual approaching A/D converter, to solve current successive approximation
The problem of conversion speed that analog-digital converter is present is relatively low.
There is provided a kind of d type flip flop, including reset terminal f, clock end CK, signal for first aspect according to embodiments of the present invention
Input D and signal output part Q, wherein the d type flip flop is resetted when reset terminal f is effective, clock end CK is invalid, is being moved back
Go out after reset state, when clock end CK is occurred for the first time effectively, the signal input part D signals inputted are latched, with
The signal for exporting signal output part Q remains identical with the signal of the latch, until the d type flip flop is answered again
Position.
In a kind of optional implementation, end F also is completed including latching, its signal lock inputted in signal input part D
After the completion of depositing, delay output latch completes signal.
In another optional implementation, the d type flip flop includes clock-reset circuit, latches completion signal output
Circuit and signal output apparatus, the first input end connection reset terminal f of the clock-reset circuit, the second input connection clock
CK is held, the connection of the first output end is described to latch the input for completing signal output apparatus, and it is defeated that the second output end connects the signal
Go out the first input end of circuit, completion end F is latched in the output end connection that the latch completes signal output apparatus, and the signal is defeated
Go out the second input connection signal input part D of circuit, output end connection signal output part Q, and control end correspondence connection is described
Latch the first end for completing signal output apparatus and the second end.
In another optional implementation, the clock-reset circuit includes the first PMOS, the second PMOS, the
Three PMOSs and NMOS tube, the source electrode of first PMOS connect its substrate and connect power vd D, grid connection reset terminal f,
The source electrode of drain electrode the second PMOS of connection, the grid connection clock end CK of second PMOS, substrate connection power vd D, leakage
Pole connects the drain electrode of NMOS tube, and the grid connection clock end CK of the NMOS tube, source ground simultaneously connects its substrate, the NMOS
The drain electrode of pipe is also connected with the input for latching and completing signal output apparatus；
The source electrode of 3rd PMOS connects its substrate and connects power vd D, grid connection reset terminal f, drain electrode connection
The first input end of the signal output apparatus.
In another optional implementation, the completion signal output apparatus that latches includes the first phase inverter and delay
Device, the input of first phase inverter connects the first output end of the clock-reset circuit, and output end connects the delay
The input of device, the output end connection of the delayer, which is latched, completes end F, the input and output end pair of first phase inverter
The control end of the signal output apparatus should be connected.
In another optional implementation, the signal output apparatus is opened including first switch, second switch, the 3rd
Pass, the second phase inverter, the 3rd phase inverter and the 4th phase inverter, one end connection signal input part D of the first switch, the other end
Connect the input of the second phase inverter, one end of the output end connection second switch of second phase inverter and the 3rd phase inverter
Input, the other end of second switch connects the input of the 4th phase inverter, the output end connection the 3rd of the 3rd phase inverter
One end of switch, the other end of the 3rd switch connects the input of second phase inverter, the 4th phase inverter it is defeated
Enter the second output end of the end connection clock-reset circuit, output end connection signal output part Q；
Described latch of control end correspondence connection of the first switch, second switch and the 3rd switch completes signal output electricity
The first end on road and the second end, the second switch and the 3rd switch on-off that state is identical, and logical with the first switch
Disconnected state is different.
There is provided a kind of asynchronous gradual approaching A/D converter, including digital-to-analogue for second aspect according to embodiments of the present invention
Converter, comparator, logic switch controller and high-speed asynchronous logic circuit, the digital analog converter are used to obtain in input
First analog signal, and the capacitance control signal provided according to the logic switch controller produces the second simulation of Approach by inchmeal
Signal；The comparator is used to the first analog signal and the second analog signal of the acquisition being compared, and knot is compared in generation
Fruit signal and compare and complete signal；The high-speed asynchronous logic circuit is used for complete according to the comparative result signal and the comparison
Into signal, generation digital output signal number and enable signal；The logic switch controller is used to be believed according to the numeral output
Number generation capacitance control signal；The comparator is after the enable signal is received by first analog signal and the second mould
Intend signal to be compared, the high-speed asynchronous logic circuit includes the D triggerings described in any one in multiple claims 1 to 6
Device, the reset terminal f of the d type flip flop is used to input reset signal, and signal input part D is used to input the comparative result signal,
The latch that clock end CK is used to receive d type flip flop latch completion end F delay outputs completes signal, wherein first D is triggered
The clock end CK of device be used for input it is described compare complete signal；The latch of last d type flip flop completes end F connection nor gates
First end, the second end input of the nor gate is described to compare and completes signal, and exports the enable signal.
In a kind of optional implementation, the high-speed asynchronous logic circuit also includes and door, the output with door
The clock end CK connections with corresponding d type flip flop are held, two inputs are respectively used to input a d type flip flop on the d type flip flop
Latch complete end F delay output latch complete signal and it is described compare complete signal.
In another optional implementation, the 3rd end input sample signal of the nor gate, the sampled signal
For the inversion signal of the reset signal.
The beneficial effects of the invention are as follows：
1. the d type flip flop DFF provided by using the present invention, devises a kind of fusion phase shift function and latch is compared
As a result the Approach by inchmeal shift register of function, compared with traditional structure, the new Approach by inchmeal shift register is used
Less device, so as to save the area of chip.
2. by using novel high speed successive approximation register, in first compares cycle, successive approximation register delay
Time is TSAR1=Tdff；In remaining compares cycle, successive approximation register time delay is TSAR2=Tand+Tdff.Due to TAnd ＜
Tdff, it therefore reduces successive approximation register time delay, improves the switching rate of gradual approaching A/D converter.
3. by using novel high speed successive approximation register, less TSAR1It is reserved for highest order electric capacity transition state
More setup times.Therefore, efficiently solve in background technology, in first compares cycle, electric capacity sets up unstable ask
Topic, reduces the design difficulty of logic switch controller.
Brief description of the drawings
Fig. 1 is the loop principle figure of asynchronous gradual approaching A/D converter in conventional art；
Fig. 2 is the overall timing diagram of asynchronous gradual approaching A/D converter in conventional art；
Fig. 3 is the asynchronous single compares cycle loop principle figure of gradual approaching A/D converter in conventional art；
Fig. 4 is Approach by inchmeal shift register time delay schematic diagram in conventional art.
Fig. 5 is the structural representation of the asynchronous gradual approaching A/D converter of the present invention；
Fig. 6 is the d type flip flop DFF schematic diagrams that use in the present invention；
Fig. 7 is the d type flip flop DFF working timing figures that use in the present invention；
The asynchronous gradual approaching A/D converter entirety timing diagram that Fig. 8 provides for the present invention；
The Approach by inchmeal shift register time delay schematic diagram that Fig. 9 provides for the present invention.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the embodiment of the present invention, and make of the invention real
Applying the above-mentioned purpose of example, feature and advantage can be more obvious understandable, below in conjunction with the accompanying drawings to technical side in the embodiment of the present invention
Case is described in further detail.
In the description of the invention, unless otherwise prescribed with restriction, it is necessary to which explanation, term " connection " should do broad sense reason
Solution, for example, it may be mechanically connecting or electrical connection or the connection of two element internals, can be joined directly together, also may be used
To be indirectly connected to by intermediary, for the ordinary skill in the art, it can understand above-mentioned as the case may be
The concrete meaning of term.
It is one embodiment circuit block diagram of asynchronous gradual approaching A/D converter of the invention referring to Fig. 5.This is asynchronous
Gradual approaching A/D converter can include digital analog converter (such as capacitor type digital analog converter) 1, comparator 2, high-speed asynchronous
Logic circuit 3 and logic switch controller 4, the digital analog converter 1 are used in input the first analog signal of acquisition, and according to
The capacitance control signal that the logic switch controller 4 is provided produces the second analog signal of Approach by inchmeal；The comparator 2 is used
It is compared in by the first analog signal and the second analog signal of the acquisition, generates comparative result signal Op and compare completion
Signal Rdy；The high-speed asynchronous logic circuit 3 be used for according to the comparative result signal Op and it is described compare completion signal Rdy,
Generate digital output signal D1 to DN and enable signal EN_Comp；The logic switch controller 4 is used for defeated according to the numeral
Go out signal D1 to DN generation capacitance control signals；The comparator 1, will be described after the enable signal EN_Comp is received
First analog signal and the second analog signal are compared.
In order to improve the conversion speed of gradual approaching A/D converter, the present invention is replaced using high-speed asynchronous logic circuit
Successive approximation register in conventional successive approach type analog-digital converter.It is directed in the high-speed asynchronous logic circuit of the present embodiment
Traditional d type flip flop is redesigned, and the d type flip flop can include reset terminal f, clock end CK, signal input part D, letter
Number output end Q and latch and complete end F, wherein the d type flip flop reset terminal f effectively, clock end CK it is invalid when resetted,
Exit after reset state, when clock end CK is occurred for the first time effectively, the signal input part D signals inputted latched,
So that the signal of signal output part Q outputs remains identical with the signal of the latch, until the d type flip flop is carried out again
Reset, latch and complete end F after the completion of the signal latch that signal input part D is inputted, delay output latch completes signal.To reset
Hold f low levels effectively, clock end CK occur rising edge it is effective exemplified by, when reset terminal f and clock end CK is low level 0, D is touched
Signal output part Q and latch in hair device complete end F and are reset to 0；When reset terminal f is that (i.e. d type flip flop exits reset to high level 1
State), when clock end CK rising edge occurs for the first time, the signal that d type flip flop inputs a signal into end D inputs is latched, and from
Signal output part Q is exported, i.e. Q=D.Then, no matter there is trailing edge in clock end CK, still occurs rising edge again, signal is defeated
The signal for going out to hold Q to export remains constant, until d type flip flop reset terminal f and clock end CK is changed into low level again.
In a kind of optional implementation, the circuit theory diagrams of the high-speed asynchronous logic circuit can with as shown in fig. 6, its
Clock-reset circuit 601 can be included, completion signal output apparatus 602 and signal output apparatus 602, the clock-reset is latched
The first input end connection reset terminal f of circuit 601, the second input connection clock end CK, the connection of the first output end is described to latch
The input of signal output apparatus 602 is completed, the second output end connects the first input end of the signal output apparatus 603, institute
State and latch the output end connection latch completion end F for completing signal output apparatus 602, the second of the signal output apparatus 603 is defeated
Enter to hold and connect signal input part D, output end connection signal output part Q, and the control end correspondence connection latch completion signal is defeated
Go out first end and the second end of circuit 602.
The clock-reset circuit 601 can be with the first PMOS (P-Metal-Oxide-Semiconductor, p-type metal oxygen
Compound semiconductor) pipe M1, the second PMOS M2, the 3rd PMOS M3 and NMOS (N-Metal-Oxide-Semiconductor, N
Type metal oxide semiconductor) pipe M4, the source electrode of the first PMOS M1 connects its substrate and connects power vd D, and grid connects
Meet reset terminal f, the second PMOS M2 of drain electrode connection source electrode, the grid connection clock end CK of the second PMOS M2, substrate
Power vd D is connected, drain electrode connection NMOS tube M4 drain electrode, the grid of the NMOS tube M4 connects clock end CK, and source ground is simultaneously
Its substrate is connected, the drain electrode of the NMOS tube M4 is also connected with the input for latching and completing signal output apparatus 602, i.e. Fig. 6
In the first phase inverter INV1 input.The source electrode of the 3rd PMOS M3 connects its substrate and connects power vd D, and grid connects
Connect the input of the 4th phase inverter INV4 in reset terminal f, the first input end of the drain electrode connection signal output apparatus 603, i.e. Fig. 6
End.
Described latch completes signal output apparatus 602 and can include the first phase inverter INV1 and delayer Delayer, described
First phase inverter INV1 input connects the first output end (i.e. NMOS tube M4 leakage in Fig. 6 of the clock-reset circuit 601
Pole), output end connects the input of the delayer Delayer, and the output end connection of the delayer Delayer, which is latched, to be completed
Hold F, the input of first phase inverterThe control end of the connection signal output apparatus 603 corresponding with output end φ is (i.e.
First switch S1, second switch S2 and the 3rd switch S3 control end in Fig. 6).
The signal output apparatus 603 can include first switch S1, second switch S2, the 3rd switch S3, second anti-phase
Device INV2, the 3rd phase inverter INV3 and the 4th phase inverter INV4, one end connection signal input part D of the first switch S1, separately
One end connects the second phase inverter INV2 input, the output end connection second switch S2 of the second phase inverter INV2 one end
With the 3rd phase inverter INV3 input, the second switch S2 other end connects the 4th phase inverter INV4 input, and described the
Three phase inverter INV3 output end connection the 3rd switchs S3 one end, and the other end connection described second of the 3rd switch S3 is anti-
Phase device INV2 input, the input of the 4th phase inverter INV4 connects the second output end of the clock-reset circuit
(i.e. the 3rd PMOS M3 drain electrode in Fig. 6), the output end connection signal output part Q of the 4th phase inverter INV4.Described
One switch S1, the switches of second switch S2 and the 3rd S3 described latch of control end correspondence connection complete signal output apparatus 602
First end and the second end (i.e. the first phase inverter INV1 input in Fig. 6With output end φ), the second switch S2 and the 3rd
The on off operating mode for switching S3 is identical, and the on off operating mode of the first switch S1 is different.Wherein, when the first phase inverter INV1 input
EndFor high level, when output end φ is low level, first switch S1 conductings, the switches of second switch S2 and the 3rd S3 disconnects；When
One phase inverter INV1 inputFor low level, when output end φ is high level, first switch S1 disconnects, second switch S2 and
3rd switch S3 conductings.
The working timing figure of d type flip flop with reference to shown in Fig. 7, below the operation principle to d type flip flop be described in detail：When
When reset terminal f and clock end CK are low level, the first PMOS M1, the second PMOS M2 and the 3rd PMOS M3 conductings,
NMOS tube M4 disconnects, now the first phase inverter INV1 inputInput high level, the first phase inverter INV1 output end φ
Low level is exported, the low level completes end F delay outputs by delayer Delayer from latching.Due to the first phase inverter INV1
InputFor high level, output end φ is first switch S1 conductings in low level, therefore signal output apparatus 603, and second opens
Close the switches of S2 and the 3rd S3 to disconnect, thus input a signal into end D and signal output part Q and keep apart.Due to the 3rd PMOS M3
Conducting, therefore the signal of the 4th phase inverter INV4 inputs is high level, the signal of output is low level, defeated from signal output part Q
The signal gone out is also low level.It can be seen that, when reset terminal f and clock end CK is low level, latches and complete end F and signal output part
Q is reset to low level.
When reset terminal f is high level, and clock end CK rising edge occurs for the first time, the first PMOS M1, the second PMOS
M2 and the 3rd PMOS M3 disconnects, NMOS tube M4 conductings, now the first phase inverter INV1 inputInput low level, first
Phase inverter INV1 output end φ output high level, the high level is by delayer Delayer, and from latching, completion end F delays are defeated
Go out；Due to the first phase inverter INV1 inputInput low level, the first phase inverter INV1 output end φ output high level,
Therefore first switch S1 disconnects in signal output apparatus 603, the switch S3 conductings of second switch S2 and the 3rd, now signal output electricity
Road 603 is latched to the signal input part D signals inputted, and the signal of latch is exported from signal output part Q.It can be seen that, when
Reset terminal f is high level, when clock end CK rising edge occurs for the first time, and locking completes end F output high level, signal output part Q
Relation between output signal and signal input part D input signals is：Q=D.
When reset terminal f is high level, clock end CK is become by high level after rising edge occurs in first time and turns to low level
When, the signal of signal output part Q and locking completion end F outputs keeps constant.When reset terminal f is high level, clock end CK is the
When once occurring rising edge occur again after rising edge, similarly, signal output part Q and locking complete the signal guarantor that end F is exported
Hold constant.
When above-mentioned d type flip flop is applied in the high-speed asynchronous logic circuit of gradual approaching A/D converter, with reference to
Shown in Fig. 5, the high-speed asynchronous logic circuit 3 can include multiple d type flip flops, and the reset terminal f of the d type flip flop is used to input
Reset signal (such as sampled signal Cks inversion signal), signal input part D is used to input the comparative result signal OP,
Clock end CK be used for receive correspondence with door 31 according to a upper d type flip flop latch complete end F delay output latch complete signal and
It is described to compare the phase shift signal for completing signal Rdy generations, wherein the clock end CK of first d type flip flop is described for inputting
Compare completion signal Rdy；The latch of last d type flip flop completes the first end of end F connections nor gate 32, the nor gate
The input of second end is described to compare completion signal OP, and the 3rd end inputs inversion signal (such as sampled signal of the reset signal
Cks), and the enable signal EN_Comp is exported.
With reference to shown in Fig. 7 and Fig. 8, when sampled signal Cks is high level, sampling switch conducting, signal Vin and Vip quilt
Sample in digital analog converter 1, asynchronous gradual approaching A/D converter enters reseting stage.Specifically, sampled signal Cks is passed through
Low level reset signal is formed after inverter, the reset signal is provided to each D in high-speed asynchronous logic circuit 3 and touched
The reset terminal f of device is sent out, because the reset terminal f low levels of d type flip flop are effective, and now on each d type flip flop clock end CK
For low level, therefore each d type flip flop is resetted, and it, which is locked, completes end F and signal output part Q and be set to low level respectively.By
It is used for input sample signal Cks in the input of nor gate 32, compares and complete the latch of signal Rdy and last d type flip flop
The locking for completing end F outputs completes signal F1, therefore when sampled signal Cks is high level, nor gate 32 is supplied to comparator 2
Enable signal EN_Comp be low level, comparator 2 resetted, and its comparison exported completes signal Rdy and comparative result is believed
Number OP is low level.In addition, the digital output signal D1 to DN that high-speed asynchronous logic circuit 3 is exported is low level, logic
The capacitance control signal that switch controller 4 is produced according to digital output signal D1 to DN, can control digital analog converter 1 to carry out
Reset.
When sampled signal Cks is low level, sampling switch disconnects, and inputs to each d type flip flop reset terminal f reset and believes
High level number is set to, the enable signal EN_Comp that nor gate 32 is exported is set to high level.Comparator 2 is receiving high level
Enable after signal EN_Comp, two analog signals that digital analog converter 1 is provided and the first analog signal obtained are compared,
And after the completion of comparing, the comparison of output high level completes signal Rdy and the first comparative result signal OP.
Then, asynchronous gradual approaching A/D converter enters compares cycle, for first d type flip flop, because it is multiple
Position end f is high level, and when first rising edge occurs in its clock end CK, its signal output part Q exports the first comparative result letter
Number OP, locking completes end F delay output high level, and the signal output part Q of other d type flip flops and locking complete end F and export low electricity
It is flat.Logic switch control is transferred to by each d type flip flop signal output part Q output signals DN~D1 digital output signals constituted
Device 1 processed, hereafter logic switch controller 1 capacitance control signal is generated according to digital output signal, and by the capacitance control signal
It is supplied to digital analog converter 1, digital analog converter 1 produces the analog signal of Approach by inchmeal according to capacitance control signal, and by the mould
The analog signal intended signal and be sampled and transformed into is sent to comparator 2.
Signal Rdy is completed for high level due to comparing, and sampled signal Cks and locking completion signal F1 are low level, because
The enable signal EN_Comp of this nor gate 32 output is low level, and comparator 2 is receiving low level enable signal EN_
Resetted after Comp, compare completion signal Rdy and comparative result signal OP and be set to low level.Put when comparing completion signal Rdy
After low level, the enable signal EN_Comp that nor gate 32 is exported is high level, and the analog signal of 2 pairs of inputs of comparator is carried out
Compare, and produce the comparison of high level and complete signal Rdy and the second comparative result signal OP.
Now, for first d type flip flop, because its reset terminal is high level, clock end CK is high level, therefore it is believed
Number output end Q remains in that output high level.For second d type flip flop, it is proper that now first d type flip flop locking completes end F
The phase shift signal FN of high level is exported well to corresponding with door 31, is compared due to being respectively used to input with door 31 and completes signal
Rdy and locking complete signal FN, therefore when comparing completion signal Rdy and locking completion signal FN is high level, are carried with door
Clock end CK for high level to second d type flip flop.Because the reset terminal of second d type flip flop is high level, clock end CK
There is first rising edge, therefore its signal output part exports the second comparative result signal OP, it is high that locking completes end F delay outputs
Level, the signal output part Q of other d type flip flops and locking complete end F output low levels.By that analogy, high-speed asynchronous logic electricity
Road 3 can realize that each d type flip flop signal output part Q and locking complete the Approach by inchmeal set at end.
As seen from the above-described embodiment, high speed asynchronous loogical circuit of the present invention is in first compares cycle, when it postpones
Between be TSAR1=Tdf, its interior time delay of remaining compares cycle is TSAR2=Tand+Tdf, due to Tand＜ Tdf, therefore the present invention is logical
Cross using having merged phase shift function and having latched the modified d type flip flop of comparative result function, high-speed asynchronous patrol can be reduced
The time delay of circuit is collected, the conversion efficiency of asynchronous gradual approaching A/D converter, and high-speed asynchronous logic circuit is improved
Less time delay TSAR1More setup times have been reserved for highest order electric capacity transition state, therefore existing skill can have been solved
The problem of electric capacity sets up unstable in first compares cycle in art, so that the design for reducing logic switch controller is difficult
Degree, modified d type flip flop is compared to traditional d type flip flop in addition, and the device used is less, thus can save the face of chip
Product.
It should be noted that：It is designed by the time delay to delayer in d type flip flop, can be to more all every time
The number of the d type flip flop of set is adjusted respectively in phase, so as to improve the flexibility compared.In addition, the present invention passes through
By a upper d type flip flop be delayed output locking complete signal and compared completion signal by with the result after computing, it is tactile as the D
The clock end input of device is sent out, a d type flip flop can be avoided to export locking too early and complete to cause d type flip flop signal output during signal
End Q set makes a mistake, so as to improve the degree of accuracy of high-speed asynchronous logic circuit work.The present invention is by by sampled signal
(i.e. the inversion signal of reset signal), compare the locking completion signal for completing signal and last d type flip flop as nor gate
Input signal, can user open sampling switch, sampled signal be high level when, immediately stop comparator comparison work
Make, so that the man-machine interaction of asynchronous gradual approaching A/D converter is more intelligent.
Fig. 9 show the Approach by inchmeal shift register time delay that the present invention is provided.Under 65nm CMOS technologies, this
The Approach by inchmeal shift register time delay that invention is provided is 91ps.As shown in figure 4, traditional structure is in 65nm CMOS technologies
Under time delay be 132ps.Therefore, the Approach by inchmeal shift register speed improves 1.45 times.
Those skilled in the art will readily occur to its of the present invention after considering specification and putting into practice invention disclosed herein
Its embodiment.The application be intended to the present invention any modification, purposes or adaptations, these modifications, purposes or
Person's adaptations follow the general principle of the present invention and including undocumented common knowledge in the art of the invention
Or conventional techniques.Description and embodiments are considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be appreciated that the invention is not limited in the precision architecture for being described above and being shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present invention is only limited by appended claim.
Claims (9)
1. a kind of d type flip flop, it is characterised in that including reset terminal f, clock end CK, signal input part D and signal output part Q, its
Described in d type flip flop reset terminal f effectively, clock end CK it is invalid when resetted, after reset state is exited, clock end CK goes out
When now effective for the first time, the signal input part D signals inputted are latched, so that the signal of signal output part Q outputs
Remain identical with the signal of the latch, until the d type flip flop is resetted again.
2. d type flip flop according to claim 1, it is characterised in that also complete end F including latching, it is in signal input part D
After the completion of the signal latch of input, delay output latch completes signal.
3. d type flip flop according to claim 2, it is characterised in that the d type flip flop includes clock-reset circuit, latched
Signal output apparatus and signal output apparatus are completed, the first input end of the clock-reset circuit connects reset terminal f, and second is defeated
Enter end connection clock end CK, the connection of the first output end is described to latch the input for completing signal output apparatus, and the second output end connects
The first input end of the signal output apparatus is connect, completion end is latched in the output end connection that the latch completes signal output apparatus
F, the second input connection signal input part D of the signal output apparatus, output end connection signal output part Q, and control end
Correspondence connection is described to latch the first end for completing signal output apparatus and the second end.
4. d type flip flop according to claim 3, it is characterised in that the clock-reset circuit includes the first PMOS, the
Two PMOSs, the 3rd PMOS and NMOS tube, the source electrode of first PMOS connect its substrate and connect power vd D, grid
Reset terminal f is connected, the source electrode of drain electrode the second PMOS of connection, the grid connection clock end CK of second PMOS, substrate connects
Power vd D is met, the drain electrode of drain electrode connection NMOS tube, the grid connection clock end CK of the NMOS tube, source ground simultaneously connects it
Substrate, the drain electrode of the NMOS tube is also connected with the input for latching and completing signal output apparatus；
The source electrode of 3rd PMOS connects its substrate and connects power vd D, and grid connection reset terminal f, drain electrode connection is described
The first input end of signal output apparatus.
5. d type flip flop according to claim 3, it is characterised in that the latch, which completes signal output apparatus, includes first
Phase inverter and delayer, the input of first phase inverter connect the first output end of the clock-reset circuit, output end
The input of the delayer is connected, the output end connection of the delayer, which is latched, completes end F, the input of first phase inverter
The control end of the end connection signal output apparatus corresponding with output end.
6. d type flip flop according to claim 3, it is characterised in that the signal output apparatus includes first switch, second
Switch, the 3rd switch, the second phase inverter, the 3rd phase inverter and the 4th phase inverter, one end connection signal of the first switch are defeated
Enter and hold D, the other end connect the second phase inverter input, second phase inverter output end connection second switch one end and
The input of 3rd phase inverter, the other end of second switch connects the input of the 4th phase inverter, the 3rd phase inverter it is defeated
Go out one end of the switch of end connection the 3rd, the other end of the 3rd switch connects the input of second phase inverter, described the
The input of four phase inverters connects the second output end of the clock-reset circuit, output end connection signal output part Q；
Described latch of control end correspondence connection of the first switch, second switch and the 3rd switch completes signal output apparatus
First end and the second end, the second switch and the 3rd switch on-off that state is identical, and with the break-make shape of the first switch
State is different.
7. a kind of asynchronous gradual approaching A/D converter, including digital analog converter, comparator, logic switch controller and high speed
Asynchronous loogical circuit, the digital analog converter is used to obtain the first analog signal by sampling switch in input, and according to institute
The capacitance control signal for stating the offer of logic switch controller produces the second analog signal of Approach by inchmeal；The comparator is used for will
The first analog signal and the second analog signal of the acquisition are compared, and generation comparative result signal and are compared and are completed signal；
The high-speed asynchronous logic circuit be used for according to the comparative result signal and it is described compare complete signal, generation numeral output letter
Number and enable signal；The logic switch controller is used to generate capacitance control signal according to the digital output signal；It is described
First analog signal and the second analog signal are compared by comparator after the enable signal is received, and its feature exists
In：
The high-speed asynchronous logic circuit includes the d type flip flop described in any one in multiple claims 1 to 6, the D triggerings
The reset terminal f of device is used to input reset signal, and signal input part D is used to input the comparative result signal, and clock end CK is used for
The latch for receiving upper d type flip flop latch completion end F delay outputs completes signal, wherein the clock end CK of first d type flip flop
For input it is described compare complete signal；The latch of last d type flip flop completes the first end of end F connection nor gates, described
The second end input of nor gate is described to compare and completes signal, and exports the enable signal.
8. asynchronous gradual approaching A/D converter according to claim 7, it is characterised in that the high-speed asynchronous logic
Circuit also includes using respectively with door, the clock end CK connections of the output end with door and corresponding d type flip flop, two inputs
In input the d type flip flop on a d type flip flop latch complete end F delay output latch complete signal and it is described compare completion letter
Number.
9. asynchronous gradual approaching A/D converter according to claim 7, it is characterised in that the 3rd of the nor gate
Input sample signal is held, the sampled signal is the inversion signal of the reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710160382.8A CN106941345B (en) | 2017-03-17 | 2017-03-17 | D trigger and asynchronous successive approximation type analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710160382.8A CN106941345B (en) | 2017-03-17 | 2017-03-17 | D trigger and asynchronous successive approximation type analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106941345A true CN106941345A (en) | 2017-07-11 |
| CN106941345B CN106941345B (en) | 2020-03-10 |
Family
ID=59469595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710160382.8A Active CN106941345B (en) | 2017-03-17 | 2017-03-17 | D trigger and asynchronous successive approximation type analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106941345B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107769785A (en) * | 2017-11-27 | 2018-03-06 | 北京华大九天软件有限公司 | A kind of sequential control circuit suitable for high-speed AD converter |
| CN107907173A (en) * | 2017-12-14 | 2018-04-13 | 湖北天禹环保科技有限公司 | A kind of analog-digital converter for ultrasonic gas flowmeter |
| CN108649939A (en) * | 2018-04-16 | 2018-10-12 | 芯原微电子(上海)有限公司 | Power sense circuit and method |
| CN109412565A (en) * | 2017-08-18 | 2019-03-01 | 深圳指芯智能科技有限公司 | A kind of multiple signals selection control circuit |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN109995371A (en) * | 2019-04-11 | 2019-07-09 | 成都盛芯微科技有限公司 | The automatic adjusument circuit and method of asynchronous SAR analog-digital converter evaluation phase duration |
| CN114172494A (en) * | 2022-02-11 | 2022-03-11 | 山东兆通微电子有限公司 | Clock signal delay circuit |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
| CN104124972A (en) * | 2014-08-08 | 2014-10-29 | 西安电子科技大学 | 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN104702289A (en) * | 2015-03-12 | 2015-06-10 | 中国电子科技集团公司第二十四研究所 | Successive approximation analog-digital converter and capacitance compensation circuit of comparator input tube thereof |
| CN104821804A (en) * | 2015-05-27 | 2015-08-05 | 中国电子科技集团公司第四十七研究所 | Delay flip-flop with reset terminal |
| CN105049043A (en) * | 2015-06-30 | 2015-11-11 | 北京时代民芯科技有限公司 | High-speed comparator with offset correction function |
| CN105070318A (en) * | 2015-08-06 | 2015-11-18 | 中国电子科技集团公司第二十四研究所 | High-speed shift register applied to successive approximation type analog-to-digital converter |
| JP2015220637A (en) * | 2014-05-19 | 2015-12-07 | 株式会社デンソー | Ad conversion apparatus |
| US20170012636A1 (en) * | 2015-07-08 | 2017-01-12 | Marvell World Trade Ltd. | Hybrid charge-sharing charge-redistribution dac for successive approximation analog-to-digital converters |
-
2017
- 2017-03-17 CN CN201710160382.8A patent/CN106941345B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684437A (en) * | 2013-02-04 | 2014-03-26 | 中国科学院电子学研究所 | A time-delay chain control code self-adaptive rapid delay lock loop |
| JP2015220637A (en) * | 2014-05-19 | 2015-12-07 | 株式会社デンソー | Ad conversion apparatus |
| CN104124972A (en) * | 2014-08-08 | 2014-10-29 | 西安电子科技大学 | 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution |
| CN104617957A (en) * | 2015-01-30 | 2015-05-13 | 中国电子科技集团公司第二十四研究所 | Asynchronous successive approximation type A/D (analog to digital) converter |
| CN104702289A (en) * | 2015-03-12 | 2015-06-10 | 中国电子科技集团公司第二十四研究所 | Successive approximation analog-digital converter and capacitance compensation circuit of comparator input tube thereof |
| CN104821804A (en) * | 2015-05-27 | 2015-08-05 | 中国电子科技集团公司第四十七研究所 | Delay flip-flop with reset terminal |
| CN105049043A (en) * | 2015-06-30 | 2015-11-11 | 北京时代民芯科技有限公司 | High-speed comparator with offset correction function |
| US20170012636A1 (en) * | 2015-07-08 | 2017-01-12 | Marvell World Trade Ltd. | Hybrid charge-sharing charge-redistribution dac for successive approximation analog-to-digital converters |
| CN105070318A (en) * | 2015-08-06 | 2015-11-18 | 中国电子科技集团公司第二十四研究所 | High-speed shift register applied to successive approximation type analog-to-digital converter |
Non-Patent Citations (2)
| Title |
|---|
| EBRAHIM ABIRI,ET AL: "The optimum design of a master-slave D-flip flap (M/S-DFF) based on the modified GDI (m-GDI) method using Non-dominated Sorting Genetic Algorithm II (NSGA-II)", 《2016 24TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE)》 * |
| 王伦耀: "低功耗触发器研究", 《中国优秀博硕士学位论文全文数据库 (硕士)信息科技辑》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109412565A (en) * | 2017-08-18 | 2019-03-01 | 深圳指芯智能科技有限公司 | A kind of multiple signals selection control circuit |
| CN107769785A (en) * | 2017-11-27 | 2018-03-06 | 北京华大九天软件有限公司 | A kind of sequential control circuit suitable for high-speed AD converter |
| CN107769785B (en) * | 2017-11-27 | 2020-04-07 | 北京华大九天软件有限公司 | Time sequence control circuit suitable for high-speed analog-to-digital converter |
| CN107907173A (en) * | 2017-12-14 | 2018-04-13 | 湖北天禹环保科技有限公司 | A kind of analog-digital converter for ultrasonic gas flowmeter |
| CN108649939A (en) * | 2018-04-16 | 2018-10-12 | 芯原微电子(上海)有限公司 | Power sense circuit and method |
| CN108649939B (en) * | 2018-04-16 | 2022-07-29 | 芯原微电子(上海)股份有限公司 | Power supply detection circuit and method |
| CN109687872A (en) * | 2019-02-26 | 2019-04-26 | 中国电子科技集团公司第二十四研究所 | High-speed digital logic circuit and sampling adjustment method for SAR_ADC |
| CN109995371A (en) * | 2019-04-11 | 2019-07-09 | 成都盛芯微科技有限公司 | The automatic adjusument circuit and method of asynchronous SAR analog-digital converter evaluation phase duration |
| CN109995371B (en) * | 2019-04-11 | 2023-03-24 | 成都盛芯微科技有限公司 | Self-adaptive adjusting circuit and method for calculating value duration of asynchronous SAR analog-to-digital converter |
| CN110535470B (en) * | 2019-08-26 | 2022-06-14 | 中国电子科技集团公司第二十四研究所 | Comparator clock generation circuit and high-speed successive approximation type analog-to-digital converter |
| CN114172494A (en) * | 2022-02-11 | 2022-03-11 | 山东兆通微电子有限公司 | Clock signal delay circuit |
| CN114172494B (en) * | 2022-02-11 | 2022-05-17 | 山东兆通微电子有限公司 | Clock signal delay circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106941345B (en) | 2020-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106941345A (en) | D type flip flop and asynchronous gradual approaching A/D converter | |
| CN104617957B (en) | Asynchronous gradual approaching A/D converter | |
| CN103546125B (en) | A kind of multiselect one burr-free clock switching circuit | |
| CN104113303B (en) | 50% duty ratio clock generation circuit | |
| WO2020173225A1 (en) | High-speed digital logic circuit for sar_adc, and sampling adjustment method | |
| CN107835021A (en) | A kind of asynchronous sequential control circuit of Variable delay and control method | |
| CN104253613B (en) | A kind of low pressure ultra-low-power high-precision comparator of SAR ADC | |
| US20080069292A1 (en) | Gated ring oscillator for a time-to-digital converter with shaped quantization noise | |
| CN101860353B (en) | Clock circuit control device in digital-analog mixed chip and method thereof | |
| CN103152050B (en) | A kind of high speed gradual approaching A/D converter | |
| CN107017889A (en) | A kind of successive approximation analog-digital converter | |
| CN101320975A (en) | Ultra-low power consumption comparer based on time domain | |
| CN106067817A (en) | 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter | |
| CN103197728A (en) | Method for realizing burr-free clock switching circuit in different clock domains as well as circuit | |
| CN106972861A (en) | A kind of analog-digital converter | |
| CN107947792A (en) | A kind of low-power consumption SAR ADC control logic circuits | |
| CN103199864B (en) | A kind of gradual approaching A/D converter | |
| CN101593221B (en) | Method and circuit for preventing different zone clocks from burr during dynamic switching | |
| CN106877868A (en) | A kind of high speed gradual approaching A/D converter | |
| CN105070318B (en) | A kind of high speed shift register applied to gradual approaching A/D converter | |
| CN110474623A (en) | A kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter | |
| CN110518912A (en) | The comparator clock generation circuit and high speed gradual approaching A/D converter of SAR ADC | |
| CN108599770A (en) | A kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC | |
| CN110247664A (en) | A kind of high-speed digital logic circuit module and analog-digital converter and electronic equipment | |
| CN104883188B (en) | A kind of Flash ADC of full digital starting |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221219 Address after: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee after: CETC Chip Technology (Group) Co.,Ltd. Address before: 400060 Chongqing Nanping Nan'an District No. 14 Huayuan Road Patentee before: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY Group Corp. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230426 Address after: Room 2-2, No. 2, Linxie Family Courtyard Group, Zaojeshu Village, Fenghuang Town, Shapingba District, Chongqing, 401334 Patentee after: Chongqing Jixin Technology Co.,Ltd. Address before: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee before: CETC Chip Technology (Group) Co.,Ltd. |
|
| TR01 | Transfer of patent right |