CN108599770A - A kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC - Google Patents
A kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC Download PDFInfo
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- CN108599770A CN108599770A CN201810436097.9A CN201810436097A CN108599770A CN 108599770 A CN108599770 A CN 108599770A CN 201810436097 A CN201810436097 A CN 201810436097A CN 108599770 A CN108599770 A CN 108599770A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The present invention discloses a kind of asynchronous clock generation circuit being suitable for 2 bit per cycle SAR ADC, marking signal, which is converted, including comparator generates unit, gate-control signal generation unit, middle comparator judgement complement mark signal generation unit and comparator asynchronous clock generation unit, wherein, comparator converts marking signal and generates input signal of the output signal of unit with change over clock Conv as gate-control signal generation unit；The output signal Q2/QB2 of the middle comparator of 2 bit per cycle SAR ADC is the input signal of middle comparator judgement complement mark signal generation unit；Gate-control signal generates the input signal that unit generates unit with the output signal of middle comparator judgement complement mark signal generation unit as comparator asynchronous clock；Comparator asynchronous clock generate unit output signal as first to third comparator asynchronous clock.Such circuit is avoided using the external clock higher than more times of sample rate, while avoiding the problem of synchronous metastable state is easily sent out in the case where realizing high speed data conversion.
Description
Technical field
The invention belongs to modulus hybrid-intergated-circuit technique fields, more particularly to a kind of to be suitable for 2-bit-per-cycle
The asynchronous clock generation circuit of SAR ADC.
Background technology
Asynchronous gradual approaching A/D converter (SAR ADC) due to its low-power consumption, high digitlization, be not required to multiple frequence clock
Characteristic be widely used.However, traditional asynchronous SAR ADC are substantially or serial structure, i.e., big 1-bit- known to the public
The operation principle of per-cycle strongly limits its application in high speed situation.In recent years, such as to the speed-raising of SAR ADC research
Fire such as the bitter edible plant.
Wherein, the Hyeok-Ki Hong of science and technology institute of South Korea in 2015 are in solid-state circuit magazine (JOURNAL OF SOLID-
STATE CIRCUITS) on propose that synchronization 7 SAR ADC, the ADC of a kind of 2-bit-per-cycle need 5 times of sampling frequencies
The external clock of rate, and in order to correct the problem of metastable state is brought, digital correcting technology has been used, this may need to use number
Word back-end technology, increases system complexity and design difficulty.
Invention content
The purpose of the present invention is to provide a kind of asynchronous clock generation suitable for 2-bit-per-cycle SAR ADC
Circuit is avoided in the case where realizing high speed data conversion using the external clock higher than more times of sample rate, while being avoided same
The problem of step metastable state is easily sent out.
In order to achieve the above objectives, solution of the invention is：
A kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC, including comparator convert
Unit is generated at marking signal, gate-control signal generates unit, middle comparator adjudicates complement mark signal generation unit and ratio
Unit is generated compared with device asynchronous clock, wherein comparator converts the output signal and change over clock that marking signal generates unit
Conv generates the input signal of unit as gate-control signal；The output of the middle comparator of 2-bit-per-cycle SAR ADC
Signal Q2/QB2 is the input signal of middle comparator judgement complement mark signal generation unit；Gate-control signal generates unit in
Between comparator decision complement mark signal generation unit output signal as comparator asynchronous clock generate unit input letter
Number；Comparator asynchronous clock generate unit output signal as first to third comparator asynchronous clock CKC1, CKC2,
CKC3。
It includes three same or doors, the first same or door input signal that above-mentioned comparator, which converts marking signal and generates unit,
For the latch result that first comparator mutually compares for the last time in conversion, output signal is that first comparator converts mark
Signal；Second same or door input signal is the latch result that the second comparator mutually compares for the last time in conversion, and output is believed
Number marking signal is converted for the second comparator；Third with or door input signal be third comparator conversion mutually last
The latch result of secondary comparison, output signal are that third comparator converts marking signal.
It includes three and door that above-mentioned gate-control signal, which generates unit, and first meets change over clock Conv with the first input end of door,
The change over clock high level is effective, and the second input termination first comparator converts marking signal, output signal first
Gate-control signal, for controlling the length of the asynchronous sequential of first comparator；Second meets change over clock Conv with the first input end of door,
The change over clock high level is effective, and second input the second comparator of termination converts marking signal, output signal second
Gate-control signal, for controlling the length of the asynchronous sequential of the second comparator；The first input end of third and door meets change over clock Conv,
The change over clock high level is effective, and the second input termination third comparator converts marking signal, and output signal is third
Gate-control signal, for controlling the length of the asynchronous sequential of third comparator.
Above-mentioned intermediate comparator decision complement mark signal generation unit uses a gate circuit, input signal second
The output signal of comparator, output signal are the marking signal that middle comparator judgement is completed.
When the output signal that above-mentioned second comparator resets phase is high level, gate circuit uses NAND gate；Second comparator
When the output signal for resetting phase is low level, gate circuit uses or door.
It includes the first NMOS tube, the second NMOS tube, third PMOS tube to the 6th that above-mentioned comparator asynchronous clock, which generates unit,
PMOS tube and the 4th with Men Zhi six and door；
Connection relation is：First NMOS tube grid connects the output letter of middle comparator judgement complement mark signal generation unit
Number, source electrode connects power ground, and drain electrode connects the source electrode of the second NMOS tube；Second NMOS tube grid is connected with third PMOS tube grid, the
Two NMOS tubes drain to be connected with the drain electrode of third PMOS tube；Third PMOS tube source electrode and the 4th PMOS tube, the 5th PMOS tube, the 6th
The drain electrode of PMOS tube connects altogether；4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube source electrode be connected to power supply altogether；4th PMOS tube
Grid connects power ground；5th PMOS tube grid connects the first acceleration enable signal；6th PMOS tube grid connects the enabled letter of the second acceleration
Number；4th connects the drain electrode of the second NMOS tube and third PMOS tube with door, the 5th with door, the 6th with the first input end of door；The
Four input the first gate-control signal of termination with the second of door, and output signal is the asynchronous clock CKC1 of first comparator；5th with
Second input the second gate-control signal of termination of door, output signal is the asynchronous clock CKC2 of the second comparator；6th with door
Second input termination third gate-control signal, output signal is the asynchronous clock CKC3 of third comparator；In addition, the 5th with door
Output signal, the second NMOS tube are connected with the grid of third PMOS tube；First accelerates enable signal low level effective, in third time
It is opened when comparing；Second accelerates enable signal low level effective, is opened in the 4th comparison.
After adopting the above scheme, the present invention compared with the prior art, has the following advantages that：
(1) present invention uses asynchronous sequential on the basis of traditional 2-bit-per-cycle SAR ADC structures, accelerates
The conversion rate of analog-digital converter avoids and is higher than the clock of more times of sample rate using external, while avoiding synchronous metastable state
The problem of easily sending out；The present invention generates asynchronous sequential on the basis of utilizing middle comparator so that sequential is compacter；
(2) asynchronous timing sequence generating circuit of the invention can also apply to 2-bit-per-cycle and 1-bit-per-cycle
The occasion being combined；
(3) in addition, introducing the acceleration of two steps in compared with low level asynchronous loop road, bit capacitor array is more made full use of to establish speed
The free time having more soon；
(4) the SAR ADC of present invention low resolution suitable for high-speed low-power-consumption.
Description of the drawings
Fig. 1 is the module frame chart of the present invention；
Fig. 2 is that comparator converts the circuit diagram that marking signal generates unit in the present invention；
Fig. 3 is the circuit diagram that gate-control signal generates unit in the present invention；
Fig. 4 is the circuit diagram of middle comparator judgement complement mark signal generation unit of the present invention；
Fig. 5 is the circuit diagram that comparator asynchronous clock generates unit in the present invention；
Fig. 6 is the sequence diagram of the present invention.
Specific implementation mode
Below with reference to attached drawing, technical scheme of the present invention and advantageous effect are described in detail.
As shown in Figure 1, the present invention provides a kind of asynchronous clock generation electricity suitable for 2-bit-per-cycle SAR ADC
Road, including comparator convert marking signal and generate unit 1, gate-control signal generation unit 2, middle comparator judgement completion mark
Will signal generation unit 3 and comparator asynchronous clock generate unit 4；Wherein, external clock mainly has ADC change over clock
Conv, high level start to convert；The comparator converts marking signal and generates unit to generate 2-bit-per-cycle
Each comfortable conversion phase last time court verdict of three parallel comparators is latched the marking signal of completion in SAR ADC；Institute
It states gate-control signal generation unit and marking signal generation unit is converted with the change over clock Conv and the comparator of ADC
Output signal is as input signal, to generate the respective asynchronous sequential enable signal of three parallel comparators；Centre is relatively
Device adjudicates complement mark signal generation unit, and to generate the middle comparator in three parallel comparators, judgement terminates every time
Marking signal；Comparator asynchronous clock generates unit to generate parallel in 2-bit-per-cycle SAR ADC three
The respective asynchronous clock of comparator；For from connection relation, comparator converts the output letter that marking signal generates unit 1
Number with change over clock Conv as gate-control signal generate unit 2 input signal；The centre of 2-bit-per-cycle SAR ADC
The output signal Q2/QB2 of comparator is the input signal of middle comparator judgement complement mark signal generation unit 3；Gate letter
Number the output signal of unit 2 and middle comparator judgement complement mark signal generation unit 3 is generated as comparator asynchronous clock
Generate the input signal of unit 4；Comparator asynchronous clock generates asynchronous clock of the output signal of unit 4 as three comparators
CKC1、CKC2、CKC3。
As shown in Fig. 2, the comparator convert marking signal generate unit 1 by three with or door form, first is same
Or the input signal of door XNOR1 be first comparator CMP1 conversion mutually compare for the last time latch result Dp1 [last]/
Dn1 [last], output signal are that first comparator CMP1 converts marking signal Done1；Second is same or door XNOR2 defeated
It is latch result Dp2 [last]/Dn2 [last] that the second comparator CMP2 mutually compares for the last time in conversion to enter signal, defeated
It is that the second comparator CMP2 converts marking signal Done2 to go out signal；Third is together or the input signal of door XNOR3 is third ratio
Compared with latch result Dp3 [last]/Dn3 [last] that device CMP3 mutually compares for the last time in conversion, output signal is third ratio
Marking signal Done3 is converted compared with device CMP3.
It is formed with door by three as shown in figure 3, the gate-control signal generates unit 2, first inputs with the first of door AND1
Change over clock Conv (high level is effective) is terminated, the second input termination first comparator CMP1's converts marking signal
Done1, output signal is the first gate-control signal GT1, for controlling the length of the asynchronous sequential of first comparator CMP1；Second and door
The first input end of AND2 meets change over clock Conv (high level is effective), and second input the second comparator CMP2's of termination converts
At marking signal Done2, output signal is the second gate-control signal GT2, for controlling the length of the second asynchronous sequential of comparator CMP2
Degree；The first input end of third and door AND3 connect change over clock Conv (high level is effective), the second input termination third comparator
CMP3's converts marking signal Done3, and output signal is third gate-control signal GT3, for controlling third comparator CMP3
The length of asynchronous sequential.
As shown in figure 4, the middle comparator judgement complement mark signal generation unit 3 is made of a gate circuit,
Input signal is the output signal Q2/QB2 of middle comparator (i.e. the second comparator CMP2), and output signal is denoted as Rdy, to produce
The marking signal that raw middle comparator judgement is completed；If the output signal that comparator resets phase is high level, which is
NAND gate；If the output signal that comparator resets phase is low level, which is or door.
As shown in figure 5, the comparator asynchronous clock generates unit 4 by the first NMOS tube M1, the second NMOS tube M2, third
PMOS tube M3 to the 6th PMOS tube M6 and the 4th and door AND4 to the 6th is formed with door AND6；
The connection relation of each device is：First NMOS tube M1 grids connect the middle comparator judgement complement mark signal production
The output signal Rdy of raw unit (3), source electrode meet power ground GND, and drain electrode connects the source electrode of the second NMOS tube M2；Second NMOS tube M2
Grid is connected with third PMOS tube M3 grids, and the second NMOS tube M2 drain electrodes are connected with the M3 drain electrodes of third PMOS tube；Third PMOS tube
M3 source electrodes and the drain electrode of the 4th PMOS tube M4, the 5th PMOS tube M5, the 6th PMOS tube M6 connect altogether；4th PMOS tube M4, the 5th
PMOS tube M5, the 6th PMOS tube M6 source electrode be connected to power vd D altogether；4th PMOS tube M4 grids meet power ground GND；5th PMOS
Pipe M5 grids meet the first acceleration enable signal ACLR1；6th PMOS tube M6 grids meet the second acceleration enable signal ACLR2；4th
The second NMOS tube M2 and third PMOS tube M3 are met with the first input end of door AND4, the 5th and door AND5, the 6th and door AND6
Drain electrode；4th inputs the first gate-control signal GT1 of termination with the second of door AND4, and output signal is first comparator CMP1's
Asynchronous clock CKC1；5th inputs the second gate-control signal GT2 of termination with the second of door AND5, and output signal is the second comparator
The asynchronous clock CKC2 of CMP2；6th inputs termination third gate-control signal GT3 with the second of door AND6, and output signal is third
The asynchronous clock CKC3 of comparator CMP3；In addition, the output signal CKC2 and the second NMOS tube M2 and third of the 5th and door AND5
The grid of PMOS tube M3 is connected；First accelerates enable signal ACLR1 low levels effective, is opened when comparing for the third time；Second adds
Fast enable signal ACLR2 low levels are effective, opened in the 4th comparison.
Below by taking 10 2-bit-per-cycle SAR ADC as an example, middle comparator (i.e. is discussed in detail in conjunction with Fig. 6
Two comparator CMP2) relevant sequential, first is similar with the sequential of the second comparator with third comparator；
First, before ADC enters conversion phase, each signal original state is：Change over clock Conv is low level, the second ratio
The marking signal Done2 that converts compared with device CMP2 is high level, and the second gate-control signal GT2 is low level, and first accelerates to enable
It is low level that signal ACLR1 and second, which accelerates enable signal ACLR2, and comparison and the reset clock CKC2 of the second comparator CMP2 are
Low level, it is low level that middle comparator (i.e. the second comparator CMP2), which adjudicates complement mark signal Rdy,；
When change over clock Conv is changed into high level, the second gate-control signal GT2 becomes high level so that CKC2 becomes high
Level, the first time for starting comparator compare；When comparator decision is completed, Rdy signals become high level so that CKC2 becomes
Low level, at this time comparator enter reseting stage；After the completion of reset, Rdy signals become low level；Then comparator carries out successively
Second to the 5th comparison；Unlike, the first acceleration enable signal ACLR1 and the second acceleration enable signal ACLR2 exist respectively
Comparator is effective when carrying out third with the 4th comparison so that the resetting time (i.e. CKC2 is in the low level time) of comparator
It changes, if it is t that note ith CKC2, which is in the low level time,low_i, then tlow_1=tlow_2>tlow_3>tlow_4, such as Fig. 6 institutes
Show, this is to make full use of low level DAC settling times short advantage.
It should be noted that when the present invention on the basis of middle comparator (i.e. the second comparator CMP2) using generating asynchronous
Sequence so that sequential is compacter, and the time margin that brings of the delay of Digital Logic can meet external comparator (i.e. first compares
Device CMP1 and third comparator CMP3) time decision requirement；In addition, controlling the asynchronous of comparator using different gate-control signals
The length of clock is to meet the needs of different occasions, some occasions such as 2-bit-per-cycle and 1-bit-per-
When cycle is combined, each comparator is different in the number of comparisons of conversion phase, this makes the asynchronous sequential of the present invention more
Flexibly.
Above example is merely illustrative of the invention's technical idea, and protection scope of the present invention cannot be limited with this, every
According to technological thought proposed by the present invention, any change done on the basis of technical solution each falls within the scope of the present invention
Within.
Claims (6)
1. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC, it is characterised in that：Including comparing
Device converts marking signal and generates unit, gate-control signal generation unit, middle comparator judgement complement mark signal generation list
Member and comparator asynchronous clock generate unit, wherein comparator convert marking signal generate unit output signal with
Change over clock Conv generates the input signal of unit as gate-control signal；The intermediate of 2-bit-per-cycle SAR ADC compares
The output signal Q2/QB2 of device is the input signal of middle comparator judgement complement mark signal generation unit；Gate-control signal generates
Unit and the output signal of middle comparator judgement complement mark signal generation unit generate unit as comparator asynchronous clock
Input signal；Comparator asynchronous clock generate unit output signal as first to third comparator asynchronous clock
CKC1、CKC2、CKC3。
2. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC as described in claim 1,
It is characterized in that：It includes three same or doors, the first same or door input letter that the comparator, which converts marking signal and generates unit,
Number for first comparator, in conversion, mutually the latch result that compares for the last time, output signal are that first comparator converts mark
Will signal；Second same or door input signal is the latch result that the second comparator mutually compares for the last time in conversion, output
Signal is that the second comparator converts marking signal；Third is together or the input signal of door is that third comparator is mutually last in conversion
The latch result once compared, output signal are that third comparator converts marking signal.
3. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC as described in claim 1,
It is characterized in that：It includes three and door that the gate-control signal, which generates unit, and first meets change over clock Conv with the first input end of door,
The change over clock high level is effective, and the second input termination first comparator converts marking signal, output signal first
Gate-control signal, for controlling the length of the asynchronous sequential of first comparator；Second meets change over clock Conv with the first input end of door,
The change over clock high level is effective, and second input the second comparator of termination converts marking signal, output signal second
Gate-control signal, for controlling the length of the asynchronous sequential of the second comparator；The first input end of third and door meets change over clock Conv,
The change over clock high level is effective, and the second input termination third comparator converts marking signal, and output signal is third
Gate-control signal, for controlling the length of the asynchronous sequential of third comparator.
4. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC as described in claim 1,
It is characterized in that：Middle comparator judgement complement mark signal generation unit uses a gate circuit, input signal the
The output signal of two comparators, output signal are the marking signal that middle comparator judgement is completed.
5. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC as claimed in claim 4,
It is characterized in that：When the output signal that second comparator resets phase is high level, gate circuit uses NAND gate；Second comparator
When the output signal for resetting phase is low level, gate circuit uses or door.
6. a kind of asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC as described in claim 1,
It is characterized in that：It includes the first NMOS tube, the second NMOS tube, third PMOS tube to the 6th that the comparator asynchronous clock, which generates unit,
PMOS tube and the 4th with Men Zhi six and door；
Connection relation is：First NMOS tube grid connects the output signal of middle comparator judgement complement mark signal generation unit,
Source electrode connects power ground, and drain electrode connects the source electrode of the second NMOS tube；Second NMOS tube grid is connected with third PMOS tube grid, and second
NMOS tube drains to be connected with the drain electrode of third PMOS tube；Third PMOS tube source electrode and the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS
The drain electrode of pipe connects altogether；4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube source electrode be connected to power supply altogether；4th PMOS tube grid
Connect power ground；5th PMOS tube grid connects the first acceleration enable signal；6th PMOS tube grid connects the second acceleration enable signal；The
Four connect the drain electrode of the second NMOS tube and third PMOS tube with door, the 5th with door, the 6th with the first input end of door；4th and door
Second input termination the first gate-control signal, output signal be first comparator asynchronous clock CKC1；5th and the of door
Two input the second gate-control signals of termination, output signal is the asynchronous clock CKC2 of the second comparator；6th is defeated with the second of door
Enter to terminate third gate-control signal, output signal is the asynchronous clock CKC3 of third comparator；In addition, the 5th believes with the output of door
Number, the second NMOS tube is connected with the grid of third PMOS tube；First accelerates enable signal low level effective, when comparing for the third time
It opens；Second accelerates enable signal low level effective, is opened in the 4th comparison.
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| CN201810436097.9A CN108599770B (en) | 2018-05-09 | 2018-05-09 | Asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC |
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| CN110086471A (en) * | 2019-05-05 | 2019-08-02 | 西安电子科技大学 | A kind of three gradual approaching A/D converters of a step |
| CN110401443A (en) * | 2019-06-25 | 2019-11-01 | 中国科学院上海微系统与信息技术研究所 | Circuit is eliminated in the metastable detection of synchronised clock adc circuit |
| CN110401444A (en) * | 2019-06-25 | 2019-11-01 | 中国科学院上海微系统与信息技术研究所 | Circuit is eliminated in the metastable detection of asynchronous clock adc circuit |
| CN113282533A (en) * | 2021-07-20 | 2021-08-20 | 中科南京智能技术研究院 | Asynchronous link sending end circuit and chip receiving end circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110086471A (en) * | 2019-05-05 | 2019-08-02 | 西安电子科技大学 | A kind of three gradual approaching A/D converters of a step |
| CN110401443A (en) * | 2019-06-25 | 2019-11-01 | 中国科学院上海微系统与信息技术研究所 | Circuit is eliminated in the metastable detection of synchronised clock adc circuit |
| CN110401444A (en) * | 2019-06-25 | 2019-11-01 | 中国科学院上海微系统与信息技术研究所 | Circuit is eliminated in the metastable detection of asynchronous clock adc circuit |
| CN110401443B (en) * | 2019-06-25 | 2023-03-31 | 中国科学院上海微系统与信息技术研究所 | Metastable state detection elimination circuit of synchronous clock ADC circuit |
| CN110401444B (en) * | 2019-06-25 | 2023-04-07 | 中国科学院上海微系统与信息技术研究所 | Metastable state detection elimination circuit of asynchronous clock ADC circuit |
| CN113282533A (en) * | 2021-07-20 | 2021-08-20 | 中科南京智能技术研究院 | Asynchronous link sending end circuit and chip receiving end circuit |
| CN113282533B (en) * | 2021-07-20 | 2021-09-28 | 中科南京智能技术研究院 | Asynchronous link sending end circuit and chip receiving end circuit |
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