CN110474623A - A kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter - Google Patents
A kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter Download PDFInfo
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- CN110474623A CN110474623A CN201910609630.1A CN201910609630A CN110474623A CN 110474623 A CN110474623 A CN 110474623A CN 201910609630 A CN201910609630 A CN 201910609630A CN 110474623 A CN110474623 A CN 110474623A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Abstract
The invention discloses a kind of imbalance self-correcting dynamic comparers for gradual approaching A/D converter, it is improved by the dynamic comparer approached in type analog-to-digital converter conventional successive, so that dynamic comparer is able to carry out offset correction, cut-offfing for NMOS and PMOS is controlled by clock signal that comparator output end generates, and self-correcting is carried out according to the principle of charge redistribution, it avoids and introduces amplifier to reduce the quiescent dissipation that imbalance generates, to reduce power loss of comparator.The present invention efficiently utilizes the principle of charge redistribution, the capacitance of adjustable corrective capacity and charge and discharge capacitance effectively improves correction accuracy, and comparison procedure separates by the correction course of dynamic comparer and in gradual approaching A/D converter system, avoid influence of the system to offset correction process, the offset voltage that dynamic comparer can be reduced improves the precision of dynamic comparer.
Description
Technical field
The invention belongs to modulus conversion technique fields, and in particular to a kind of imbalance for gradual approaching A/D converter
Self-correcting dynamic comparer.
Background technique
In nature, most of signals of generation are all being macroscopically analog quantitys, for example, temperature, pressure, sound or
Touch signal etc., these signals finally all must carry out various processing in digital field, so each system requires one
A analog-to-digital conversion device ADC and digital signal processor DSP composition.The development of super large-scale integration has been started using number
The climax of processing technique, promotes people that must pay attention to the effect of analog- and digital- intersystem interface component, and analog-digital converter becomes
The bridge of connection analog signal and digital signal；In today of information-based high speed development, analog-digital converter is measuring device, each
The important component of kind conversion and display and information system, therefore analog-digital converter is the important module in a system, it
Performance height directly determines the performance of electronic information processing system.
There are many kinds of ADC types, including parallel, successive approximation, integral form, pipeline-type and ∑-Δ type ADC etc., no
Speed, precision and the power consumption of same type ADC can be different, therefore also can be different for the different selected ADC of system；And by
Secondary approach type ADC apply more some low-power consumption, in high-precision system, as shown in Figure 1, it mainly includes four modules:
Sampling and keep module, comparator module, capacitor array module and successive approximation register module etc.；SAR ADC
The analog signal that working principle inputs first as shown in Figure 1: is by being sent into comparator and DAC array after sampling and keep module
The reference voltage of generation is compared, and successive approximation register controls the capacitor of capacitor array according to the output result of comparator
Switching changes reference level to be compared next time, and the numeric results finally exported are exactly the output quantity of ADC.
In recent years, with the fast development of integrated circuit technique, constantly push SAR ADC to low pressure, low-power consumption,
At a high speed, high-precision direction is developed, and the key modules as SAR ADC, the speed and precision of comparator affect
The performance of entire ADC, wherein dynamic comparer be because it can realize high speed, and the characteristics of do not consume the quiescent dissipation of system, often
It is often used.In order to further increase the performance of dynamic comparer, often requires that and is still able to maintain high-precision performance at high speeds,
Wherein offset voltage is directly related to the precision of comparator；The method for reducing imbalance in the prior art, which has to be added before comparator, puts
The structure of big grade, but amplifying stage is added and increases system power dissipation, it also will affect the speed of comparator.
Summary of the invention
In view of above-mentioned, the present invention provides a kind of imbalance self-correcting Dynamic comparisons for gradual approaching A/D converter
Device enables to carry out imbalance self-correcting according to the output result of comparator every time；Clock is corrected by the output of dynamic comparer
Signal generates, and comparison procedure separates by the correction course of dynamic comparer and in gradual approaching A/D converter system, keeps away
Exempt from influence of the system to offset correction process, improves correction accuracy；It is corrected, is not consumed quiet using the principle of charge redistribution
State power consumption, reduces system power dissipation.
A kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter, including Dynamic comparison circuit,
Offset adjusting circuit and clock control circuit；Wherein:
The clock control circuit is for generating following three groups of clock signals:
Clock signal CAL, for controlling offset adjusting circuit；
Clock signal CALB reaches its voltage altogether for being pre-charged to the corrective capacity in offset adjusting circuit
Mould level；
Clock signal clk, for the reset of Dynamic comparison circuit and the control of comparison phase；
The Dynamic comparison circuit is used to be compared two-pass DINSAR input signal inn and inp, and in clock signal
Two-pass DINSAR comparison signal outn and outp are gradually generated under the control of CLK；
The offset adjusting circuit enters offset correction mode under the control of clock signal CAL and CALB, according to described
Differential comparison signal makes corresponding corrective capacity carry out charge and discharge, changes capacitance voltage size by changing charge size, with
Offset correction is carried out to Dynamic comparison circuit.
Further, the Dynamic comparison circuit is made of pre-amplification circuit and positive feedback latch structure and contains 13
A metal-oxide-semiconductor M1~M13, in which: the source electrode of metal-oxide-semiconductor M1 is grounded, and the grid of metal-oxide-semiconductor M1 connects clock signal clk, the leakage of metal-oxide-semiconductor M1
Pole is connected with the source electrode of the source electrode of metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3, and the grid of metal-oxide-semiconductor M2 and the grid of metal-oxide-semiconductor M3 connect difference respectively
Input signal inn and inp, the drain electrode of metal-oxide-semiconductor M2 and drain electrode, the grid of metal-oxide-semiconductor M6 and the grid of metal-oxide-semiconductor M12 of metal-oxide-semiconductor M4
It is connected, the drain electrode of metal-oxide-semiconductor M3 is connected with the grid of the drain electrode of metal-oxide-semiconductor M5, the grid of metal-oxide-semiconductor M7 and metal-oxide-semiconductor M13, metal-oxide-semiconductor M4
Grid be connected with the grid of metal-oxide-semiconductor M5 and connect clock signal clk, the source electrode of metal-oxide-semiconductor M4 is connected and connects with the source electrode of metal-oxide-semiconductor M5
The source electrode of operating voltage VDD, metal-oxide-semiconductor M12 are connected and are grounded with the source electrode of metal-oxide-semiconductor M10, the source electrode and metal-oxide-semiconductor M11 of metal-oxide-semiconductor M13
Source electrode be connected and be grounded, the drain electrode of metal-oxide-semiconductor M12 and the drain electrode of metal-oxide-semiconductor M10, the drain electrode of metal-oxide-semiconductor M8, metal-oxide-semiconductor M9 grid with
And the connected simultaneously drain electrode of output difference comparison signal outn, metal-oxide-semiconductor M13 of grid and the drain electrode of metal-oxide-semiconductor M11, MOS of metal-oxide-semiconductor M11
The grid of the drain electrode of pipe M9, the grid of metal-oxide-semiconductor M8 and metal-oxide-semiconductor M10 is connected and output difference comparison signal outp, metal-oxide-semiconductor M8
Source electrode be connected with the drain electrode of metal-oxide-semiconductor M6, the source electrode of metal-oxide-semiconductor M9 is connected with the drain electrode of metal-oxide-semiconductor M7, the source electrode and MOS of metal-oxide-semiconductor M6
The source electrode of pipe M7 is connected and meets operating voltage VDD.
Further, metal-oxide-semiconductor M1~M5 constitutes pre-amplification circuit, and metal-oxide-semiconductor M6~M13 constitutes positive feedback and latches knot
Structure；Wherein, metal-oxide-semiconductor M1~M3 and metal-oxide-semiconductor M10~M13 uses NMOS tube, and metal-oxide-semiconductor M4~M5 and metal-oxide-semiconductor M6~M9 are used
PMOS tube.
Further, the offset adjusting circuit is made of two completely identical in structure offset correction modules, the mistake
Adjust correction module be made of and contain pre-charge circuit and capacitor charge and discharge circuit two phase inverters INV1 and INV2, one with
NOT gate, one and door, two conventional capacitives C1 and C2, a corrective capacity, a controllable switch and five metal-oxide-semiconductor M16,
M18~M21；Wherein: the first input end of NAND gate meets differential comparison signal outp, the second input terminal of NAND gate with door
First input end is connected and connects clock signal CAL, the second input termination differential comparison signal outn with door, the output of NAND gate
End is connected with the input terminal of the grid of metal-oxide-semiconductor M19 and phase inverter INV1, with the output end of door and the grid of metal-oxide-semiconductor M20 and
The input terminal of phase inverter INV2 is connected, and the output end of phase inverter INV1 is connected with the grid of metal-oxide-semiconductor M18, and phase inverter INV2's is defeated
Outlet is connected with the grid of metal-oxide-semiconductor M21, and the source electrode of metal-oxide-semiconductor M18 meets operating voltage VDD, and the drain electrode of metal-oxide-semiconductor M18 is with capacitor C1's
The source electrode of one end and metal-oxide-semiconductor M19 are connected, the other end of capacitor C1 ground connection, one end of the drain electrode of metal-oxide-semiconductor M21 and capacitor C2 with
And the source electrode of metal-oxide-semiconductor M20 is connected, the other end of capacitor C2 is connected and is grounded with the source electrode of metal-oxide-semiconductor M21, the drain electrode of metal-oxide-semiconductor M19
It is connected with one end of the drain electrode of metal-oxide-semiconductor M20, one end of controllable switch, the grid of metal-oxide-semiconductor M16 and corrective capacity, controllable switch
Another termination common mode electrical level, the control electrode of controllable switch meets clock signal CALB, the other end ground connection of corrective capacity, metal-oxide-semiconductor
Two the output ports O1 and O2 of the drain electrode of M16 and source electrode respectively as offset correction module；One of offset correction module
Output port O1 and O2 be connected respectively with the drain electrode of metal-oxide-semiconductor M2 in Dynamic comparison circuit and source electrode, another offset correction mould
The output port O1 and O2 of block are connected with the drain electrode of metal-oxide-semiconductor M3 in Dynamic comparison circuit and source electrode respectively.
Further, controllable switch, corrective capacity and metal-oxide-semiconductor M16 constitute pre-charge circuit, metal-oxide-semiconductor M18~M21,
Phase inverter INV1 and INV2, NAND gate constitute capacitor charge and discharge circuit with door and conventional capacitive C1 and C2；Wherein, metal-oxide-semiconductor
M16, M20 and M21 use NMOS tube, and metal-oxide-semiconductor M18 and M19 use PMOS tube.
Further, the clock control circuit includes mistuned circuit correction signal generation module, the generation of CLK clock signal
Module and CALB clock signal generating module, in which:
The mistuned circuit correction signal generation module includes one and a door U1 and delayer T1, two with door
Input terminal connects the corresponding inversion signal out+ and out- of differential comparison signal outn and outp, output end and delay with door respectively
The input terminal of device is connected, and the output end of delayer generates correction signal clk_calib；
The CLK clock signal generating module include one three input with door U2, one with or door, one or, one
An a delayer T2 and phase inverter INV3, same or door two input terminals connect the output of a current and preceding comparator respectively
Value, comparator output valve is the output Q value that inversion signal out+ and out- are input to after rest-set flip-flop, same or door output end
It is connected with the input terminal of phase inverter INV3, the output end of phase inverter INV3 generates clock signal OFF, three input terminals with door U2
Meet correction signal clk_calib, clock signal OFF and clock signal CAL respectively, with the output end of door U2 with or door first
Input terminal is connected or the output end and delayer of the clock signal clk of the external given comparator of the second input termination of door or door
The input terminal of T2 is connected, and the output end of delayer T2 generates clock signal clk；
The CALB clock signal generating module includes two-stage frequency-dividing clock circuit, and first order frequency-dividing clock circuit is by multiple
Frequency unit cascades, and each frequency unit includes a d type flip flop and a phase inverter, the input terminal of d type flip flop and anti-
The output end of phase device is connected, and the output end of d type flip flop is connected with the input terminal of phase inverter and the output end as frequency unit, D
Input terminal of the clock end of trigger as frequency unit, the output end of previous frequency unit are defeated with the latter frequency unit
Enter end to be connected, the input of first frequency unit terminates correction signal clk_calib；Second level frequency-dividing clock circuit includes multiple
Cascade d type flip flop and a phase inverter INV4, the output end of previous d type flip flop and the input terminal of the latter d type flip flop
It is connected, the input of first d type flip flop terminates high level, the input of the output end and phase inverter INV4 of the last one d type flip flop
End is connected, and the output end of phase inverter INV4 generates clock signal CALB, and the clock end of each d type flip flop connects altogether and connects the first fraction
The output end of the last one frequency unit in frequency clock circuit.
Further, the clock signal CAL is given by outside, generates via clock control circuit, high level time control
Offset adjusting circuit processed is corrected, and comparator enters offset correction mode.
The present invention is improved by the dynamic comparer approached in type analog-to-digital converter conventional successive, so that dynamic ratio
It is able to carry out offset correction compared with device, cut-offfing for NMOS and PMOS is controlled by clock signal that comparator output end generates, and
Self-correcting is carried out according to the principle of charge redistribution, avoids the quiescent dissipation for introducing amplifier to reduce imbalance generation, from
And reduce power loss of comparator.
The present invention efficiently utilizes the principle of charge redistribution, the capacitance of adjustable corrective capacity and charge and discharge capacitance
To effectively improve correction accuracy, and compare by the correction course of dynamic comparer and in gradual approaching A/D converter system
It is separated compared with process, avoids influence of the system to offset correction process.The present invention is for can be in gradual approaching A/D converter
System power dissipation is reduced, the offset voltage of dynamic comparer is reduced, improves the precision of dynamic comparer, is suitable for high speed, high-precision
The design of gradually-appoximant analog-digital converter.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of gradual approaching A/D converter system.
Fig. 2 is the structural schematic diagram of present invention imbalance self-correcting dynamic comparer.
Fig. 3 (a) is the structural schematic diagram of offset adjusting circuit in the present invention.
Fig. 3 (b) is the variation waveform signal of imbalance self-correcting dynamic comparer output valve and corrective capacity top crown voltage
Figure.
Fig. 4 is the structural schematic diagram of clock control circuit in the present invention.
Fig. 5 is the time diagram of each clock signal in the present invention.
Specific embodiment
In order to more specifically describe the present invention, with reference to the accompanying drawing and specific embodiment is to technical solution of the present invention
It is described in detail.
As shown in Fig. 2, the present invention is used for the imbalance self-correcting dynamic comparer of gradual approaching A/D converter, comprising:
Dynamic comparison circuit, offset adjusting circuit, clock control circuit；Wherein dynamic comparer circuit is by pre-amplification circuit and positive feedback
Latch structure composition, pre-amplification circuit are made of three NMOS tube M1~M3 and two PMOS tube M4~M5, and knot is latched in positive feedback
There are four NMOS tube M10~M13 and four PMOS tube M6~M9 to constitute for structure, inputs the drain terminal and NMOS to pipe NMOS tube M2~M3
Pipe M12~M13, the grid end of PMOS tube M6~M7 are connected.Dynamic comparison circuit is used to be compared differential input signal, according to
Clock signal clk obtains two-pass DINSAR comparison signal, and gradually generates comparison signal.When CAL is high level, circuit enters mistake
Adjustment holotype；When CAL is low level, circuit enters comparator operating mode.There are two the stages when dynamic comparer works:
Reset and comparison phase, when CLK is low level, dynamic comparer enters reseting stage, the Dynamic comparison when CLK is high level
Device enters comparison phase；Offset adjusting circuit enters offset correction mode by clock control circuit, according to comparison signal result
Corresponding corrective capacity is subjected to charge and discharge, changes voltage swing by changing charge size, gradually carry out n times compare until
Comparison signal changes.Clock control circuit is used for the pattern switching of dynamic comparer, offset correction mode and comparison pattern.Including
Three clock control signals: CAL clock signal is controlled to offset adjusting circuit；CALB clock signal, for imbalance
The corrective capacity of circuit is pre-charged, and corrective capacity is charged to common mode electrical level；CLK clock signal, it is multiple for comparator circuit
Position and comparison phase are controlled.
Shown in offset adjusting circuit of the invention such as Fig. 3 (a), it is by pre-charge circuit and capacitor charge and discharge circuit group
At；Wherein pre-charge circuit is made of switch, corrective capacity Ccal and two NMOS tube M16~M17, when switching by CALB
Clock system is charged to common mode electrical level, corrective capacity to grid end voltage X, Y point of two NMOS tube M16~M17 into line precharge
Corresponding charge is stored on Ccal；Capacitor charge and discharge circuit by two PMOS tube M18~M19, two NMOS tube M20~M21 and
Logic gate is constituted, and wherein comparator differential comparison signal outp and CAL clock signal are after NAND gate and the grid of PMOS tube M19
End is connected, while being connected behind the door with the grid end of PMOS tube M18 by non-, and PMOS tube M18, which is realized, charges to the top crown of capacitor C1
To VDD.Comparator differential comparison signal other end outn and CAL clock signal are after NAND gate and the grid end of NMOS tube M20
It is connected, while is connected behind the door with the grid end of NMOS tube M21 by non-, NMOS tube M20 realization charges to the top crown of capacitor C1
GND.Charge and discharge are carried out to corrective capacity by cut-offfing for the M19 and NMOS tube M20 of PMOS tube.When circuit is started to work, when
Outp, outn output are low level when comparator enters reseting stage, cause PMOS tube M19 and NMOS tube M20 to turn off, PMOS tube
M18 and NMOS tube M21 is opened so that C1 and C2 capacitor is respectively charged in VDD and GND, corresponding in the top crown storage of C1 and C2
Charge, when comparator enters comparison phase, outp, outn if comparator is there are offset voltage are on the contrary, make PMOS tube M19
Or NMOS tube M20 is open-minded, correspondingly C1 and Ccal, C2 and Ccal charge redistribution carry out charge and discharge process, lead to NMOS tube
Grid end voltage X, Y point voltage of M16~M17 changes, to influence dynamic comparer input to the drain terminal of pipe NMOS tube M2~M3
Voltage constantly switches with comparison phase as dynamic comparer is resetted, constantly carries out charge and discharge to capacitor C1 or C2, until school
Just terminate.As shown in Fig. 3 (b), in offset correction, the voltage of corrective capacity Ccal top crown is charged first within the t1 moment
To common mode electrical level, the correction for then making NMOS tube M16, M17 grid end connected according to the output result of self-correcting dynamic comparer
Capacitor side is charged, and other side is discharged, until t2 moment self-correcting dynamic comparer output result start into
Row 1/0 is overturn, and correction terminates at this time, and corrective capacity Ccal top crown voltage value fluctuates near droop voltage.
Clock control circuit of the invention is as shown in figure 4, clock control circuit includes three clock circuits, CAL clock letter
Number, CALB clock signal and CLK clock signal.
CAL clock signal is made up of the clock signal that outside is given, when CAL is high level, the input of dynamic comparer
End NMOS tube M2~M3 connects common mode electrical level, and self-correcting comparator enters offset correction mode；When CAL is low level, self-correcting ratio
Enter normal comparison pattern compared with device.
CALB clock signal, corrective capacity when for offset correction mode to mistuned circuit are pre-charged, will be corrected
Capacitor is charged to common mode electrical level, is made of two-stage frequency-dividing clock；Wherein first order frequency-dividing clock is by d type flip flop and phase inverter INV structure
At, self-correcting dynamic comparer differential output signal outp, outn by obtained after phase inverter differential signal out+,
Out-, and by with input signal clk_calib, the clk_calib signal that first order frequency-dividing clock is obtained after gate delay and
The clock end of one d type flip flop is connected, and the clock end of remaining d type flip flop is connected with the output end of previous d type flip flop, passes through
The output signal of the first order is obtained after n d type flip flop and phase inverter；The output signal of the first order and the institute of second level frequency-dividing clock
There is the clock end of d type flip flop to be connected, the output end of last d type flip flop is obtained into offset adjusting circuit after phase inverter INV
Precharge clock CALB.
CLK clock signal resets for comparator circuit and comparison phase is controlled.When self-correcting positive circuit works, when
Clock signal is generated by internal signal, and differential signal out+, out-, which pass through, forms offset adjusting circuit with after door and delay
Timing in clk_calib, the output valve Q of self-correcting comparator and a preceding output valve Q* by with or after obtain correction knot
Beam signal OFF, clk_calib signal, OFF signal and CAL clock signal pass through with behind the door and/or one end of door is connected, the other end
It is connected with the comparator signal clk in gradual approaching A/D converter, obtains CLK clock signal.During offset correction,
It is corrected by offset adjusting circuit, until the output valve Q of dynamic comparer realizes overturning, illustrates that correction is complete at this time
At correction error is the correction voltage value of single correction clock.CLK clock signal by the correction course of dynamic comparer and by
Comparison procedure separates in secondary approach type analog-to-digital converter, avoids influence of the system to offset correction process.
Lack of proper care self-correcting dynamic comparer working sequence as shown in figure 5, gradually type analog-to-digital converter system work when,
The correction for first carrying out imbalance self-correcting dynamic comparer, avoids the influence in dynamic comparer correction course by system, influences
Correction accuracy.When CAL is high level, self-correcting dynamic comparer enters offset correction mode.Into after offset correction mode,
It is first pre-charged to corrective capacity Ccal, when CALB is high level, by the top crown voltage bulk charge of corrective capacity Ccal
To common mode electrical level VCM, when CALB is low level, precharge terminates when as in Fig. 5 to t1 point.Inside self-correcting dynamic comparer
The offset correction clock that signal generates is clk_calib, and when clk_calib is high level, self-correcting positive circuit carries out imbalance school
Just, correction accuracy is related with capacitor value, and the difference of C1, C2 and Ccal are bigger, and correction accuracy is higher.When clk_calib is low
Self-correcting positive circuit is charged to VDD and GND to capacitor C1 and C2 respectively when level, and in clk_calib clock high level next time
Charge redistribution is carried out, is successively corrected.At the t2 moment, the output signal Q of dynamic comparer is flipped, OFF signal from
High level jumps to low level, and correction terminates, and offset adjusting circuit stops working.Until the t3 moment, the conversion of successive approximation modulus
Clk clock in device arrives, and self-correcting dynamic comparer is started to work in gradually type analog-to-digital converter system.
The above-mentioned description to embodiment is for that can understand and apply the invention convenient for those skilled in the art.
Person skilled in the art obviously easily can make various modifications to above-described embodiment, and described herein general
Principle is applied in other embodiments without having to go through creative labor.Therefore, the present invention is not limited to the above embodiments, ability
Field technique personnel announcement according to the present invention, the improvement made for the present invention and modification all should be in protection scope of the present invention
Within.
Claims (7)
1. a kind of imbalance self-correcting dynamic comparer for gradual approaching A/D converter, which is characterized in that including dynamic
Comparison circuit, offset adjusting circuit and clock control circuit；Wherein:
The clock control circuit is for generating following three groups of clock signals:
Clock signal CAL, for controlling offset adjusting circuit；
Clock signal CALB makes its voltage reach common mode electricity for being pre-charged to the corrective capacity in offset adjusting circuit
It is flat；
Clock signal clk, for the reset of Dynamic comparison circuit and the control of comparison phase；
The Dynamic comparison circuit is used to be compared two-pass DINSAR input signal inn and inp, and in clock signal clk
Two-pass DINSAR comparison signal outn and outp are gradually generated under control；
The offset adjusting circuit enters offset correction mode under the control of clock signal CAL and CALB, according to the difference
Comparison signal makes corresponding corrective capacity carry out charge and discharge, changes capacitance voltage size by changing charge size, to dynamic
State comparison circuit carries out offset correction.
2. imbalance self-correcting dynamic comparer according to claim 1, it is characterised in that: the Dynamic comparison circuit is by pre-
Amplifying circuit and positive feedback latch structure form and contain 13 metal-oxide-semiconductor M1~M13, in which: the source electrode of metal-oxide-semiconductor M1 connects
Ground, the grid of metal-oxide-semiconductor M1 connect clock signal clk, the source electrode phase of the drain electrode of metal-oxide-semiconductor M1 and the source electrode of metal-oxide-semiconductor M2 and metal-oxide-semiconductor M3
Even, the grid of metal-oxide-semiconductor M2 and the grid of metal-oxide-semiconductor M3 meet differential input signal inn and inp, the drain electrode of metal-oxide-semiconductor M2 and MOS respectively
The grid of the drain electrode of pipe M4, the grid of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M12 is connected, the drain electrode of metal-oxide-semiconductor M3 and the drain electrode of metal-oxide-semiconductor M5,
The grid of metal-oxide-semiconductor M7 and the grid of metal-oxide-semiconductor M13 are connected, and the grid of metal-oxide-semiconductor M4 is connected with the grid of metal-oxide-semiconductor M5 and connects clock
The source electrode of signal CLK, metal-oxide-semiconductor M4 are connected with the source electrode of metal-oxide-semiconductor M5 and connect operating voltage VDD, the source electrode and metal-oxide-semiconductor of metal-oxide-semiconductor M12
The source electrode of M10 is connected and is grounded, and the source electrode of metal-oxide-semiconductor M13 is connected and is grounded with the source electrode of metal-oxide-semiconductor M11, the drain electrode of metal-oxide-semiconductor M12 with
The drain electrode of metal-oxide-semiconductor M10, the drain electrode of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M9 and metal-oxide-semiconductor M11 grid be connected and output difference ratio
Compared with signal outn, the drain electrode and the drain electrode of metal-oxide-semiconductor M11 of metal-oxide-semiconductor M13, the drain electrode of metal-oxide-semiconductor M9, metal-oxide-semiconductor M8 grid and MOS
The grid of pipe M10 is connected and the source electrode of output difference comparison signal outp, metal-oxide-semiconductor M8 are connected with the drain electrode of metal-oxide-semiconductor M6, metal-oxide-semiconductor
The source electrode of M9 is connected with the drain electrode of metal-oxide-semiconductor M7, and the source electrode of metal-oxide-semiconductor M6 is connected with the source electrode of metal-oxide-semiconductor M7 and meets operating voltage VDD.
3. imbalance self-correcting dynamic comparer according to claim 2, it is characterised in that: metal-oxide-semiconductor M1~M5 constitutes pre-
Amplifying circuit, metal-oxide-semiconductor M6~M13 constitute positive feedback latch structure；Wherein, metal-oxide-semiconductor M1~M3 and metal-oxide-semiconductor M10~M13 are adopted
With NMOS tube, metal-oxide-semiconductor M4~M5 and metal-oxide-semiconductor M6~M9 use PMOS tube.
4. imbalance self-correcting dynamic comparer according to claim 2, it is characterised in that: the offset adjusting circuit is by two
A completely identical in structure offset correction module composition, the offset correction module is by pre-charge circuit and capacitor charge and discharge circuit
Form and contain two phase inverters INV1 and INV2, a NAND gate, one and door, two conventional capacitives C1 and C2, one
Corrective capacity, a controllable switch and five metal-oxide-semiconductor M16, M18~M21；Wherein: the first input end of NAND gate connects difference
The second input terminal of comparison signal outp, NAND gate are connected with the first input end with door and meet clock signal CAL, and with door
Two input termination differential comparison signal outn, the input of the output end of NAND gate and the grid of metal-oxide-semiconductor M19 and phase inverter INV1
End is connected, and is connected with the output end of door with the input terminal of the grid of metal-oxide-semiconductor M20 and phase inverter INV2, phase inverter INV1's is defeated
Outlet is connected with the grid of metal-oxide-semiconductor M18, and the output end of phase inverter INV2 is connected with the grid of metal-oxide-semiconductor M21, the source of metal-oxide-semiconductor M18
Pole meets operating voltage VDD, and the drain electrode of metal-oxide-semiconductor M18 is connected with the source electrode of one end of capacitor C1 and metal-oxide-semiconductor M19, and capacitor C1's is another
One end ground connection, the drain electrode of metal-oxide-semiconductor M21 is connected with the source electrode of one end of capacitor C2 and metal-oxide-semiconductor M20, the other end of capacitor C2 and
The source electrode of metal-oxide-semiconductor M21 is connected and is grounded, the drain electrode of metal-oxide-semiconductor M19 and the drain electrode of metal-oxide-semiconductor M20, one end of controllable switch, metal-oxide-semiconductor
The grid of M16 and one end of corrective capacity are connected, and another termination common mode electrical level of controllable switch, the control electrode of controllable switch connects
Clock signal CALB, the other end ground connection of corrective capacity, the drain electrode of metal-oxide-semiconductor M16 and source electrode are respectively as offset correction module
Two output ports O1 and O2；The output port O1 and O2 of one of offset correction module are respectively and in Dynamic comparison circuit
The drain electrode of metal-oxide-semiconductor M2 is connected with source electrode, the output port O1 and O2 of another offset correction module respectively with Dynamic comparison circuit
The drain electrode of middle metal-oxide-semiconductor M3 is connected with source electrode.
5. imbalance self-correcting dynamic comparer according to claim 4, it is characterised in that: controllable switch, corrective capacity with
And metal-oxide-semiconductor M16 constitutes pre-charge circuit, metal-oxide-semiconductor M18~M21, phase inverter INV1 and INV2, NAND gate, with door and common
Capacitor C1 and C2 constitute capacitor charge and discharge circuit；Wherein, metal-oxide-semiconductor M16, M20 and M21 uses NMOS tube, metal-oxide-semiconductor M18 and M19
Using PMOS tube.
6. imbalance self-correcting dynamic comparer according to claim 1, it is characterised in that: the clock control circuit includes
Mistuned circuit correction signal generation module, CLK clock signal generating module and CALB clock signal generating module, in which:
The mistuned circuit correction signal generation module includes one and a door U1 and delayer T1, two inputs with door
End meets the corresponding inversion signal out+ and out- of differential comparison signal outn and outp respectively, with the output end of door and delayer
Input terminal is connected, and the output end of delayer generates correction signal clk_calib；
The CLK clock signal generating module include one three input with door U2, one with or door, one or, one prolong
When a device T2 and phase inverter INV3, with or two input terminals of door connect the output valve of a current and preceding comparator respectively, than
Compared with the output Q value that device output valve is after inversion signal out+ and out- are input to rest-set flip-flop, with or the output end of door and anti-
The input terminal of phase device INV3 is connected, and the output end of phase inverter INV3 generates clock signal OFF, distinguishes with three input terminals of door U2
Meet correction signal clk_calib, clock signal OFF and clock signal CAL, with the output end of door U2 with or door the first input
Hold the output end of the external clock signal clk for giving comparator of connected or door the second input termination or door with delayer T2's
Input terminal is connected, and the output end of delayer T2 generates clock signal clk；
The CALB clock signal generating module includes two-stage frequency-dividing clock circuit, and first order frequency-dividing clock circuit is by multiple frequency dividings
Unit cascaded to form, each frequency unit includes a d type flip flop and a phase inverter, the input terminal and phase inverter of d type flip flop
Output end be connected, the output end of d type flip flop is connected with the input terminal of phase inverter and the output end as frequency unit, D trigger
Input terminal of the clock end of device as frequency unit, the output end of previous frequency unit and the input terminal of the latter frequency unit
It is connected, the input of first frequency unit terminates correction signal clk_calib；Second level frequency-dividing clock circuit includes multiple cascades
D type flip flop and a phase inverter INV4, the output end of previous d type flip flop be connected with the input terminal of the latter d type flip flop,
The input of first d type flip flop terminates high level, the input terminal phase of the output end and phase inverter INV4 of the last one d type flip flop
Even, the output end of phase inverter INV4 generates clock signal CALB, when the clock end of each d type flip flop connects altogether and connects first order frequency dividing
The output end of the last one frequency unit in clock circuit.
7. imbalance self-correcting dynamic comparer according to claim 1, it is characterised in that: the clock signal CAL is by outer
Portion is given, generates via clock control circuit, and control offset adjusting circuit is corrected when high level, and comparator enters imbalance
Correction mode.
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