CN108011635A - A kind of method of dynamic comparer and its mistuning calibration function - Google Patents

Abstract

The invention discloses a kind of method of dynamic comparer and its mistuning calibration function, which includes：Latch and the prime amplifier including pre-amplification circuit and calibration auxiliary circuit；The calibration auxiliary circuit includes charge storage capacitance, charge and discharge switch, common mode switch, the first calibration controlling switch and the second calibration controlling switch of storage offset voltage；By the input terminal series connection charge storage capacitance in dynamic comparer, and the control for passing through charge and discharge switch, common mode switch, the first calibration controlling switch and the second calibration controlling switch carries out mistuning calibration function.

Description

A Dynamic Comparator and Its Offset Calibration Method

technical field

The invention relates to the communication field, in particular to a dynamic comparator and a method for offset calibration thereof.

Background technique

With the continuous improvement of the data processing speed of modern digital systems, high-performance A/D converters have become an inevitable development trend. As one of the basic modules of the A/D converter, the circuit design technology and performance optimization of the comparator are also very important. Among them, due to its low power consumption, high speed, and better compatibility with deep submicron technology, full dynamic comparators are increasingly used in high-performance, low-power A/D converter circuits. However, the full dynamic comparator also has the disadvantage of large offset, especially as the size of the CMOS process shrinks, the offset will become more serious, and gradually become one of the main bottlenecks restricting the performance of the A/D converter. In order to reduce the offset of the full dynamic comparator, large-sized integrated components can be used, but this will increase the area and load. Another method is to use the offset calibration technology. By measuring and adjusting the offset of the offset, it can be compared with a relatively small device area to achieve high comparison accuracy. Full dynamic comparator offset calibration usually needs to work with the support of calibration auxiliary circuits and calibration logic, and requires a certain calibration time and additional power consumption.

The pros and cons of a calibration technique are mainly measured comprehensively by the performance of the calibrated circuit, the area and power consumption increased due to calibration, and the calibration time.

Figure 1 is a traditional dynamic comparator offset calibration circuit. Its principle is to adjust the threshold voltage of the input transistor by adjusting the load capacitance of the pre-amplified differential output to offset the original offset voltage of the comparator. The adjustment of the load capacitance can be realized through the configurable capacitor arrays CP and CN. The configurable capacitor array is composed of m units with capacitors connected in series with switches. If the switch is turned on, the capacitance of the unit is incorporated into the load capacitance; otherwise, the capacitance of the unit does not form the load. Usually, the switch control signal comes from the output of the m-bit memory, and the content of the memory is obtained through a power-on calibration control circuit. The value of m here is determined by the offset voltage calibration range and calibration accuracy. Also, the larger the calibration range and the higher the accuracy, the larger m is required.

Figure 2 is another traditional dynamic comparator offset calibration circuit, its working principle is to calibrate the comparator offset by adjusting the current of the differential branch. In terms of circuit implementation, the calibration technology compensates the mismatch by adjusting the gate voltage difference of the auxiliary input differential pair transistors M1 and M2. The gate of the M1 tube is connected to a fixed voltage value, and the gate of the M2 tube is connected to a voltage holding capacitor CH, whose voltage is controlled by a calibration circuit. When the circuit is in the calibration mode, the two input terminals of the comparator are short-circuited with the common-mode signal, and the offset voltage of the circuit is amplified and compared with the output, so as to control the external control current source to extract or inject current from the capacitor CH. If the current source injects current into CH, it will increase the gate voltage of M2, increasing its discharge current. The mismatch of the auxiliary input tube current is used to compensate the offset of the comparator itself. Through the comparison and compensation of multiple cycles, the comparator offset can be reduced to a relatively small range. Here, the capacitance of the voltage holding capacitor CH is determined by the calibration accuracy of the comparator offset. The higher the calibration accuracy, the larger the capacitance of CH.

It can be clearly seen that the disadvantage of traditional calibration method 1 is that it needs to increase the configurable capacitor array, memory and logic controller, and its area is proportional to the calibration range and calibration accuracy; the added load capacitance of the pre-amplification circuit will reduce the speed of the comparator . However, this method can be used permanently with a single calibration, without refreshing and without additional power consumption. The second traditional calibration method needs to increase the voltage holding capacitor CH, and its area is proportional to the calibration accuracy. In addition, the adjustment of the gate voltage of the auxiliary input tube requires multiple cycles of successive approximation to complete, which increases the calibration time; calibration requires the participation of the entire comparator (including the dynamic pre-amplifier and the subsequent latch circuit), and the power consumption is relatively high. . Therefore, there is an urgent need for a dynamic comparator and a technical solution for offset calibration thereof, which can realize offset calibration with small area cost, short calibration time, and low power consumption cost.

Contents of the invention

In view of this, the embodiments of the present invention hope to provide a dynamic comparator and its offset calibration method, which can realize offset calibration with small area cost, short calibration time and low power consumption cost.

The technical scheme of the embodiment of the present invention is realized like this:

An embodiment of the present invention provides a dynamic comparator, the dynamic comparator includes: a latch and a pre-amplifier including a pre-amplification circuit and a calibration auxiliary circuit;

The calibration auxiliary circuit includes a charge storage capacitor for storing an offset voltage, a charge and discharge switch, a common mode switch, a first calibration control switch, and a second calibration control switch;

The gate of the input differential NMOS transistor of the pre-amplification circuit is respectively connected to the first end of the charge storage capacitor and the first end of the charge and discharge switch, and the second end of the charge storage capacitor is respectively connected to the common The first end of the mode switch is connected to the input end of the dynamic comparator, the second end of the common mode switch is connected to the input common mode voltage power supply of the pre-amplification circuit, and the second end of the charge and discharge switch is connected to to the output of the pre-amplifier;

The drain of the input differential NMOS transistor is connected to the first end of the first calibration control switch;

The source of the input differential NMOS transistor is connected to the first end of the second calibration control switch;

The output terminal of the pre-amplifier is connected to the input stage of the latch.

In the above solution, the turn-on and turn-off of the first calibration control switch is controlled by a calibration trigger clock signal, and the turn-on and turn-off of the second calibration control switch is controlled by inverting the calibration trigger clock signal Control; wherein, the first calibration control switch is a PMOS transistor, and the second calibration control switch is an NMOS transistor.

In the above solution, the second end of the charge storage capacitor is connected to the first end of the differential input switch of the pre-amplification circuit, and the second end of the differential input switch is connected to the input end of the dynamic comparator; Wherein, the differential input switch is turned off in the offset calibration state and turned on in the comparison state.

In the above solution, the second end of the first calibration control switch is connected to the first end of the first comparison control switch of the pre-amplification circuit, wherein the second end of the first comparison control switch is connected to the Calibration voltage supply connection;

The first end of the second calibration control switch is connected to the first end of the second comparison control switch of the pre-amplification circuit, and the second end of the second calibration control switch is respectively connected to the second comparison control switch. The second end is connected to the ground end of the pre-amplification circuit.

In the above solution, the turn-on and turn-off of the first comparison control switch is controlled by a comparison trigger clock signal, and the turn-on and turn-off of the second comparison control switch is controlled by inverting the comparison trigger clock signal control; wherein, the first comparison control switch is a PMOS transistor, and the second comparison control switch is an NMOS transistor.

In the solution above, the turn-on and turn-off of the charge-discharge switch is controlled by the control signal obtained by inverting the control signal of the common-mode switch and the signal obtained by AND operation of the voltage signal at the output terminal.

An embodiment of the present invention also provides a method for offset calibration applied to the above-mentioned dynamic comparator, the method comprising:

In the offset calibration state, the first calibration control switch is set to be turned on, and the second calibration control switch, the common mode switch and the charging and discharging switch are respectively set to be turned off, and the calibration voltage power supply of the pre-amplification circuit is supplied to The input differential NMOS tube is charged so that the voltage value of the drain of the input differential NMOS tube reaches a calibration voltage;

Set the first calibration control switch to turn off, respectively set the second calibration control switch, the common mode switch and the charge and discharge switch to conduct, and the drain voltage of the input differential NMOS transistor is passed through the input differential The NMOS transistor performs common-mode discharge, charges the charge storage capacitor, and stores the offset charge in the charge storage capacitor.

In the above scheme, the method also includes:

Set the first calibration control switch and the charging and discharging switch to be turned off respectively, respectively set the second calibration control switch and the common mode switch to be turned on, and the drain voltage of the input differential NMOS transistor is passed through the input differential NMOS The tube undergoes a common-mode discharge and stops charging the charge storage capacitor.

In the above scheme, the method also includes:

In the comparison state, the first calibration control switch is set to be turned on, and the common mode switch, the charge and discharge switch, and the second calibration control switch are respectively set to be turned off, and the differential input of the input terminal of the dynamic comparator is amplified. The signal and the offset voltage corresponding to the offset charge stored in the charge storage capacitor are superimposed to obtain an equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and the amplified judgment of the latch to obtain the equivalent voltage. The comparison results of the above differential amplified signals.

In the above scheme, the method also includes:

The first calibration control switch is turned on and on by the calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; wherein, the first calibration The control switch is a PMOS transistor, and the second calibration control switch is an NMOS transistor.

In the above scheme, the method also includes:

When in the offset calibration state, the differential input switch is turned off; wherein, the first end of the differential input switch is connected to the second end of the charge storage capacitor, and the second end of the differential input switch is connected to the dynamic comparison connected to the input of the device.

In the above scheme, the method also includes:

When the first comparison control switch of the pre-amplification circuit is turned on and the second comparison control switch of the pre-amplification circuit is turned off, the dynamic comparator is in an offset calibration state; wherein,

The second end of the first calibration control switch is connected to the first end of the first comparison control switch, and the second end of the first comparison control switch is connected to the calibration voltage power supply;

The first terminal of the second calibration control switch is connected to the first terminal of the second comparison control switch, and the second terminal of the second calibration control switch is respectively connected to the second terminal of the second comparison control switch and The ground terminal of the pre-amplification circuit is connected.

In the above scheme, the method also includes:

Turning on and off of the charging and discharging switch is controlled by an AND operation of the control signal obtained by inverting the control signal of the common mode switch and the voltage signal at the output terminal.

The dynamic comparator and its offset calibration method in the embodiment of the present invention eliminate the offset by storing the offset voltage of the dynamic comparator on the series capacitor at the input end of the dynamic comparator, without requiring a large amount of memory and control lines, and only needing to spend The power consumption of the pre-amplifier does not need to wait for the calibration convergence time, which not only effectively reduces the offset of the dynamic pre-amplifier, improves the conversion accuracy of the comparator, but also has the advantages of small area cost, low power consumption cost and fast calibration speed.

Description of drawings

Fig. 1 is a schematic structural diagram of a traditional dynamic comparator offset calibration circuit 1;

The structural schematic diagram of the traditional dynamic comparator offset calibration circuit 2 of Fig. 2;

FIG. 3 is a schematic structural diagram of a dynamic comparator provided in Embodiment 1 of the present invention;

FIG. 4 is a working principle diagram of a dynamic comparator provided by Embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of a circuit structure of a preamplifier and a latch of a dynamic comparator provided in Embodiment 1 of the present invention;

6 is a schematic structural diagram of a control circuit of a charging and discharging switch provided in Embodiment 1 of the present invention;

FIG. 7 is a schematic flowchart of a method for calibrating a dynamic comparator offset provided by Embodiment 2 of the present invention;

8 is a schematic circuit diagram of the offset charge storage process of the dynamic comparator provided by Embodiment 3 of the present invention;

9 is a schematic circuit diagram of the comparison process of the dynamic comparator provided in Embodiment 3 of the present invention;

FIG. 10 is a timing diagram of a dynamic comparator provided in Embodiment 3 of the present invention;

Description of reference signs: charge storage capacitor, Ch; charge and discharge switch, K2; common mode switch, F2; first calibration control switch, K11; second calibration control switch, K12; first input differential NMOS transistor, M1; second Input differential NMOS transistor, M2; differential input switch, F1; first comparison control switch F1K1; second comparison control switch F1K2.

Detailed ways

The implementation of the technical solution will be further described in detail below in conjunction with the accompanying drawings.

Embodiment one

Embodiment 1 of the present invention provides a dynamic comparator. As shown in FIG. 3, the dynamic comparator includes: a latch and a pre-amplifier including a pre-amplification circuit and a calibration auxiliary circuit; the calibration auxiliary circuit includes a storage offset voltage Charge storage capacitor Ch, charge and discharge switch K2, common mode switch F2, first calibration control switch K11 and second calibration control switch K12; the gate of the input differential NMOS transistor of the pre-amplification circuit is connected to the gate of the charge storage capacitor Ch The first terminal is connected to the first terminal of the charging and discharging switch K2, the second terminal of the charge storage capacitor Ch is respectively connected to the first terminal of the common mode switch F2 and the input terminal of the dynamic comparator, and the second terminal of the common mode switch F2 It is connected with the input common-mode voltage power supply V _CM of the pre-amplification circuit, and the second end of the charge-discharge switch K2 is connected to the output end of the pre-amplifier; the drain of the input differential NMOS transistor is connected to the first calibration control The first end of the switch is connected; the source of the input differential NMOS transistor is connected to the first end of the second calibration control switch; the output end of the pre-amplifier is connected to the input stage of the latch. Among them, in the pre-amplification circuit, it includes a completely symmetrical circuit composed of the first input differential NMOS transistor M1 and the second input differential NMOS transistor M2, the drain of the first input differential NMOS transistor and the drain of the second input differential NMOS transistor It is the output terminal of the preamplifier, and the voltage at the output terminal is connected to the input stage of the latch. As shown in FIG. 3 , the gate, drain, and source of the first input differential NMOS transistor M1 and the second input differential NMOS transistor M2 are respectively connected with charge storage capacitor Ch, charge and discharge switch K2, and common mode switch F2. 1. A calibration auxiliary circuit for the first calibration control switch K11 and the second calibration control switch K12. By adding a calibration auxiliary circuit in the pre-amplifier, the dynamic comparator performs offset storage and normal comparison in each cycle.

As shown in Figure 3, the turn-on and turn-off of the first calibration control switch is controlled by a calibration trigger clock signal, and the turn-on and turn-off of the second calibration control switch is controlled by inverting the calibration trigger clock signal performing control; wherein, the first calibration control switch is a PMOS transistor, and the second calibration control switch is an NMOS transistor. Here, when the calibration trigger clock signal is CLK _K1 , the first calibration control switch K11 and the second calibration control switch K12 are simultaneously controlled by CLK _K1 , and the states of the first calibration control switch K11 and the second calibration control switch K12 are opposite, specifically The low level of CLK _K1 controls the first calibration control switch K11 to be turned on, and the second calibration control switch K12 is turned off; the high level of CLK _K1 controls the first calibration control switch K11 to be turned off, and the second calibration control switch K12 conduction.

Wherein, when the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube, the first end of the first calibration control switch is a source, the second end of the first calibration switch is a drain, and the second calibration switch is a drain. The first end of the control switch is the source, and the second end of the second calibration control switch is the drain.

Here, the low level of the calibration trigger clock signal CLK _K1 controls the first calibration control switch K11 to be turned on, and the second calibration control switch K12 is to be turned off. In the offset storage stage, as shown in FIG. 4 , the calibration trigger clock signal CLK _K1 The low-level phase control nodes P and N are charged to the voltage V _DD of the calibration voltage power supply; the high-level phase control nodes P and N of the calibration trigger clock signal CLK _K1 perform common mode via the input differential pair (M1, M2) discharge at this time. During the common-mode discharge process of the input differential pair tubes, the mismatch of the circuit affects the discharge speed of nodes P and N. The charge storage capacitors Ch corresponding to the nodes P and N track and store the voltages (Vp and Vn) of the nodes P and N. Wherein, node P and node N are the output terminals of the amplifier, which are connected to the input stage of the latch.

The circuit structure of the pre-amplification circuit of the dynamic comparator provided by the embodiment of the present invention is shown in Figure 5, and the circuit structure of the latch is shown in Figure 6, wherein the output node P (V _P ) and node N (V _N ) is respectively connected to the input stages V _IP and V _IN of the latch, so that the output signal of the pre-amplification circuit is used as the input signal of the latch, and the latch performs the operation according to the voltage signal amplified by the pre-amplification circuit. The amplification decision is to compare the differential signals input by the dynamic comparator from the differential input terminals V _IP and V _IN of the pre-amplification circuit.

Here, the pre-amplification circuit further includes a differential input switch F1 and a first comparison control switch F1K1 and a second comparison control switch F1K2.

As shown in Figure 5, the second end of the charge storage capacitor Ch is connected to the first end of the differential input switch F1 of the pre-amplification circuit, and the second end of the differential input switch F1 is connected to the input end of the dynamic comparator; Wherein, the differential input switch is turned off in the offset calibration state and turned on in the comparison state. Wherein, the input terminals of the pre-amplification circuit include V _IP and V _IN .

As shown in Figure 5, the second end of the first calibration control switch K11 is connected to the first end of the first comparison control switch F1K1 of the pre-amplification circuit, wherein the second end of the first comparison control switch F1K1 is connected to the first end of the first comparison control switch F1K1. Calibration voltage power supply connection; the first end of the second calibration control switch K12 is connected to the first end of the second comparison control switch F1K2 of the pre-amplification circuit, and the second end of the second calibration control switch K12 is connected to the second comparison control switch F1K2 respectively. The second end of the switch F1K2 is connected to the ground end of the pre-amplification circuit. Wherein, the voltage of the calibration voltage supply VDD is V _DD .

In the embodiment of the present invention, the turn-on and turn-off of the first comparison control switch F1K1 is controlled by a comparison trigger clock signal, and the turn-on and turn-off of the second comparison control switch F1K2 is controlled by inverting the comparison trigger clock signal control; wherein, the first comparison control switch F1K1 is a PMOS transistor, and the second comparison control switch F1K2 is an NMOS transistor. Wherein, when the first comparison control switch is a PMOS transistor and the second comparison control switch is an NMOS transistor, the first terminal of the first comparison control switch is a source, the second terminal of the first comparison switch is a drain, and the second comparison control switch is a drain. The first end of the quasi-control switch is the source, and the second end of the second comparison control switch is the drain.

Here, when the comparison trigger clock signal is CLK _F1K , the first comparison control switch F1K1 and the second comparison control switch F1K2 are simultaneously controlled by CLK _F1K , and the states of the first comparison control switch F1K1 and the second comparison control switch F1K2 are opposite, specifically The low level of CLK _F1K controls the first comparison control switch F1K1 to turn on, and the second comparison control switch F1K2 turns off; the high level of CLK _F1K controls the first comparison control switch F1K1 to turn off, and the second comparison control switch F1K2 conduction.

In the embodiment of the present invention, as shown in FIG. 7, the turn-on and turn-off of the charge-discharge switch K2 is obtained by ANDing the control signal obtained by inverting the control signal of the common-mode switch F2 and the voltage signal at the output terminal. signal to control. Therefore, the AND gate of the voltage Vp of the node P/the voltage Vn of the node N and the control signal of the charging and discharging switch F2 controls the common mode switch K2 to be at a high level or a low level, wherein the control signal CLK _F1 of F2 is K2’s A small delay of the control signal CLK _K2 .

In practical applications, in order to ensure that the input differential NMOS transistor of the pre-amplification circuit works normally in the saturation region during the next comparison time, it is necessary to control the Vp and Vn stored in the charge storage capacitor Ch corresponding to the node P and node N. When the voltages of the nodes P and N drop to a certain voltage range, the charging and discharging switch K2 needs to be turned off in time. In the comparator reset stage, this calibration technology adds a discharge and charge operation to the output node of the pre-amplification circuit by calibrating the change of the clock K1 from low level to high level, and at two points of node P and node N The storage of the offset charge is completed during the discharge process.

In the dynamic comparator provided by the embodiment of the present invention, the first calibration control switch F11 and the second calibration control switch F12 are added in the pre-amplification circuit, and the first calibration control switch F11 and the second calibration control switch F12 are turned on and off. , when the control signal is calibrated to trigger the change of the clock signal CLK _K1 from low level to high level, a discharge and charge operation is added to the output node of the pre-amplification circuit, and the discharge process at the two points of node P and node N to complete the storage of the offset charge in the charge storage capacitor.

In the embodiment of the present invention, the dynamic The offset voltage of the comparator is stored on the series capacitor Ch at the input end to eliminate the offset, which does not require a large amount of memory and control lines, only consumes the power consumption of the pre-amplifier, and does not need to wait for the calibration convergence time, which not only effectively reduces the offset of the dynamic pre-amplifier, The conversion accuracy of the comparator is improved, and it has the advantages of small area cost, low power consumption cost and fast calibration speed.

Compared with the traditional dynamic comparator offset calibration technology, the dynamic comparator provided by the embodiment of the present invention does not require a large number of memory and control lines, and the size of the offset charge storage capacitor Ch is related to the parasitic capacitance of the input MOS transistor, due to the circuit The size of the input MOS tube is small, the charge storage capacitor Ch is relatively small, and the area cost is small; the dynamic comparator stores the offset voltage before each normal comparison, and this process only costs the power consumption of the pre-amplifier and does not require subsequent latching The device circuit is involved, and the power consumption cost is low; the principle is simple and easy to implement, and the calibration is completed in an instant, without the time spent on gradual convergence, the system can be powered on and working without a special calibration process, and the calibration time is short. Compared with the traditional offset calibration technology, the dynamic comparator offset calibration technology proposed by the present invention has comprehensive advantages in terms of area, power consumption and calibration time.

Embodiment two

In the embodiment of the invention, the method for offset calibration of the dynamic comparator provided by the embodiment of the invention is described in conjunction with the dynamic comparator shown in FIG. 3 to FIG. 6 , as shown in FIG. 7 , the method includes:

S701. In the offset calibration state, set the first calibration control switch to be turned on, respectively set the second calibration control switch, the common mode switch, and the charge and discharge switch to be off, and the calibration voltage of the pre-amplification circuit The power supply charges the input differential NMOS transistor so that the voltage value of the drain of the input differential NMOS transistor reaches the calibration voltage;

S702. Turn off the first calibration control switch, respectively turn on the second calibration control switch, the common mode switch, and the charging and discharging switch, and the drain voltage of the input differential NMOS transistor is passed through the The input differential NMOS transistor performs common-mode discharge, charges the charge storage capacitor, and stores the offset charge in the charge storage capacitor.

Wherein, in S701, a discharge operation of the output node of the pre-amplification circuit is completed; in S702, a charging operation of the output node of the pre-amplification circuit is completed, thereby charging the charge storage capacitor from the output node of the pre-amplification circuit, Storage of offset charges takes place in the charge storage capacitor.

In the embodiment of the present invention, the first calibration control switch and the charging and discharging switch are respectively turned off, the second calibration control switch and the common mode switch are respectively turned on, and the drain of the input differential NMOS transistor The voltage is discharged in a common mode through the input differential NMOS transistor and stops charging to the charge storage capacitor.

In the comparison state, the first calibration control switch is set to be turned on, and the common mode switch, the charge and discharge switch, and the second calibration control switch are respectively set to be turned off, and the differential amplified signal input at the input terminal and The offset voltage corresponding to the offset charge stored in the charge storage capacitor is superimposed to obtain an equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and amplified by the latch to obtain the differential voltage. The comparison result of the amplified signal.

Wherein, the first calibration control switch is turned on and on by the calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; wherein, the first A calibration control switch is a PMOS transistor, and the second calibration control switch is an NMOS transistor.

When in the offset calibration state, the differential input switch is turned off; wherein, the first end of the differential input switch is connected to the second end of the charge storage capacitor, and the second end of the differential input switch is connected to the pre-amplifier The input terminal of the circuit is connected.

When the first comparison control switch of the pre-amplification circuit is turned on and the second comparison control switch of the pre-amplification circuit is turned off, the dynamic comparator is in an offset calibration state; wherein, the first calibration The second end of the control switch is connected to the first end of the first comparison control switch, and the second end of the first comparison control switch is connected to the calibration voltage power supply; the first end of the second calibration control switch connected to the first terminal of the second comparison control switch, and the second terminal of the second calibration control switch is respectively connected to the second terminal of the second comparison control switch and the ground terminal of the pre-amplification circuit. Wherein, the turn-on and turn-off of the charge-discharge switch is controlled by the control signal obtained by inverting the control signal of the common-mode switch and the signal obtained by AND operation of the voltage signal at the output terminal.

Embodiment three

In this embodiment, the offset calibration of the dynamic comparator shown in Fig. 3-Fig. 6 provided by the embodiment of the present invention is combined with Fig. The method is explained.

It should be noted that in the pre-amplifier part, the input differential pair transistors M1 and M2, the first comparison control switch F1K1, the second comparison control switch F1K2 and the differential input switch F1 constitute the normal pre-amplification circuit of the comparator, and the input of the pre-amplification circuit The charge storage capacitor Ch, the first calibration control switch K11 , the second calibration control switch K12 , the charging and discharging switch K2 and the common mode switch F2 connected in series with each other form a calibration auxiliary circuit of the comparator. The comparator is divided into two stages: offset storage (offset calibration state) and normal comparison (comparison state). Specifically, the charge storage process in the offset storage stage is shown in Figure 8(a) and Figure 8(b). The normal comparison stage The comparison process of the differential voltage is shown in Figure 9(a) and Figure 9(b).

In the offset storage stage, as shown in Figure 8(a), the comparison trigger clock signal CLK _F1K and the calibration trigger clock signal CLK _K1 are low, and the first comparison control switch F1K1 and the first calibration control switch F11 (PMOS tube) turn the pre-amplifier The output nodes (node P, node N) of the two points are pre-charged to the calibration voltage V _DD , and at the same time the output node out of the latch is reset to ground, and the tail current transistors of the pre-amplifier and the latch are turned off. As shown in Figure 8(b), when the rise of the common-mode voltage of nodes P and N triggers CLK _K1 to change to a high level, the tail current tube of the pre-amplifier is turned on, and the pre-amplifier outputs nodes P and N The common mode discharge starts, and the mismatch effect of the circuit causes the discharge speed to be different. When the common-mode voltage of node P and node N drops, the falling edge of K2 is triggered, and the offset voltage is stored in the corresponding input series capacitor Ch. When CLK _K1 becomes low level, the offset storage phase of the comparator ends. In addition, in order to ensure that the input differential pair tubes (M1, M2) of the pre-amplification circuit work normally in the saturation region during the next comparison time, it is necessary to control the Vp and Vn stored in Ch. In terms of circuit implementation, Vp/Vn and the AND gate of switch F2 control K2 to be high or low, and K1 is a small delay of K2, as shown in Figure 6.

Then, the comparator is controlled by the comparison trigger clock CLK _F1K to enter the normal comparison stage, as shown. The equivalent input of the comparator is the voltage value obtained by superimposing the input signal and the offset voltage. As shown in Figure 9(a), when CLK _F1K is low, the comparator is reset. As shown in Figure 9(a), when CLK _F1K is at a high level, the pre-amplifier amplifies the input differential signal, triggers the latch to amplify and judge through positive feedback, and then outputs the comparison result.

According to the timing diagram shown in Figure 10, the circuit of the dynamic comparator offset calibration technology in the embodiment of the present invention is divided into 5 working states:

(1) Calibration trigger clock CLK _K1 and comparison trigger clock CLK _F1K are low, K2 is off, F2 is off, F12 is off, F11 is on, the input capacitor precharge state;

(2) Calibration trigger clock CLK _K1 is high and comparison trigger clock CLK _F1K is low, K2 is on, F2 is on and F11 is on, and F12 is off to calibrate the charge storage state;

(3) Calibration trigger clock CLK _K1 is high, comparison trigger clock CLK _F1K is low, K2 is off, F2 is on, F11 is on, F12 is off, and the calibration charge stops storing;

_{and _}

(5) The calibration trigger clock CLK _K1 is low and the comparison trigger clock CLK _F1K is high, K2 is disconnected, F2 is disconnected, F11 is disconnected, and F12 is closed. The comparator is in normal comparison working state.

In the above states, the state where the calibration charge stops storing and the reset state before the comparator works normally are almost at the same time, and the control signal of F2 in the timing diagram has a small delay than the control signal of K2.

In the embodiment of the present invention, the first calibration control switch F11 and the second calibration control switch F12 can be implemented by MOS transistors, and the specific switch forms of the common mode switch F2 and the charging and discharging switch K2 are not limited in this embodiment of the present invention.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (13)

1. A dynamic comparator, wherein the dynamic comparator comprises: a latch and a preamplifier including a preamplification circuit and a calibration auxiliary circuit;

the calibration auxiliary circuit comprises a charge storage capacitor for storing offset voltage, a charge-discharge switch, a common-mode switch, a first calibration control switch and a second calibration control switch;

the grid electrode of an input differential NMOS tube of the pre-amplification circuit is respectively connected with a first end of the charge storage capacitor and a first end of the charge and discharge switch, a second end of the charge storage capacitor is respectively connected with a first end of the common mode switch and an input end of the dynamic comparator, a second end of the common mode switch is connected with an input common mode voltage power supply of the pre-amplification circuit, and a second end of the charge and discharge switch is connected to an output end of the pre-amplifier;

the drain electrode of the input differential NMOS tube is connected with the first end of the first calibration control switch;

the source electrode of the input differential NMOS tube is connected with the first end of the second calibration control switch;

the output end of the preamplifier is connected with the input stage of the latch.

2. The dynamic comparator according to claim 1, wherein the first calibration control switch is controlled to turn on and off by a calibration trigger clock signal, and the second calibration control switch is controlled to turn on and off by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.

3. The dynamic comparator according to claim 1, wherein a second terminal of the charge storage capacitor is connected to a first terminal of a differential input switch of the pre-amplification circuit, and a second terminal of the differential input switch is connected to an input terminal of the dynamic comparator; wherein the differential input switch is off in the offset calibration state and on in the comparison state.

4. The dynamic comparator according to claim 1 or 2, wherein a second terminal of the first calibration control switch is connected to a first terminal of a first comparison control switch of the pre-amplification circuit, wherein the second terminal of the first comparison control switch is connected to the calibration voltage supply;

the first end of the second calibration control switch is connected with the first end of a second comparison control switch of the pre-amplifying circuit, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplifying circuit.

5. The dynamic comparator according to claim 4, wherein the turning on and off of the first comparison control switch is controlled by comparing a trigger clock signal, and the turning on and off of the second comparison control switch is controlled by inverting the comparison trigger clock signal; the first comparison control switch is a PMOS tube, and the second comparison control switch is an NMOS tube.

6. The dynamic comparator according to claim 1, wherein the on and off states of the charge and discharge switches are controlled by a signal obtained by performing an and operation on a control signal obtained by inverting a control signal of the common mode switch and a voltage signal of the output terminal.

7. A method for the offset calibration of a dynamic comparator, the method being applied to the dynamic comparator of claim 1, the method comprising:

in an offset calibration state, the first calibration control switch is turned on, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned off, and a calibration voltage power supply of the pre-amplification circuit charges the input differential NMOS transistor to enable the voltage value of the drain electrode of the input differential NMOS transistor to reach a calibration voltage;

and the first calibration control switch is turned off, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned on, the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube, the charge storage capacitor is charged, and offset charge is stored in the charge storage capacitor.

8. The method of claim 7, further comprising:

and the first calibration control switch and the charge and discharge switch are respectively arranged to be turned off, the second calibration control switch and the common mode switch are respectively arranged to be turned on, and the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube and stops charging the charge storage capacitor.

9. The method of claim 7, further comprising:

in a comparison state, the first calibration control switch is turned on, the common mode switch, the charge and discharge switch and the second calibration control switch are turned off respectively, a differential amplification signal input from an input end of the dynamic comparator and offset voltage corresponding to the offset charge stored in the charge storage capacitor are superposed to obtain equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and is judged by the latch to obtain a comparison result of the differential amplification signal.

10. The method of claim 7, further comprising:

the first calibration control switch is turned on and off by a calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.

11. The method of claim 7, further comprising:

when the differential input switch is in the maladjustment calibration state, the differential input switch is switched off; wherein a first terminal of the differential input switch is connected to a second terminal of the charge storage capacitor, and a second terminal of the differential input switch is connected to an input terminal of the dynamic comparator.

12. The method of claim 7, further comprising:

when a first comparison control switch of the pre-amplification circuit is switched on and a second comparison control switch of the pre-amplification circuit is switched off, the dynamic comparator is in an offset calibration state; wherein,

a second end of the first calibration control switch is connected with a first end of the first comparison control switch, and a second end of the first comparison control switch is connected with the calibration voltage power supply;

the first end of the second calibration control switch is connected with the first end of the second comparison control switch, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplification circuit.

13. The method of claim 7, further comprising:

and controlling the on and off of the charge and discharge switch through a control signal obtained by inverting the control signal of the common mode switch and a signal obtained by performing AND operation on the voltage signal of the output end.