CN108011635A - A kind of method of dynamic comparer and its mistuning calibration function - Google Patents
A kind of method of dynamic comparer and its mistuning calibration function Download PDFInfo
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Abstract
The invention discloses a kind of method of dynamic comparer and its mistuning calibration function, which includes：Latch and the prime amplifier including pre-amplification circuit and calibration auxiliary circuit；The calibration auxiliary circuit includes charge storage capacitance, charge and discharge switch, common mode switch, the first calibration controlling switch and the second calibration controlling switch of storage offset voltage；By the input terminal series connection charge storage capacitance in dynamic comparer, and the control for passing through charge and discharge switch, common mode switch, the first calibration controlling switch and the second calibration controlling switch carries out mistuning calibration function.
Description
Technical Field
The invention relates to the field of communication, in particular to a dynamic comparator and a method for calibrating offset thereof.
Background
With the increasing data processing speed of modern digital systems, high performance a/D converters are becoming a necessary trend. As one of the basic blocks of the a/D converter, circuit design techniques and performance optimization of the comparator are also very important. The full dynamic comparator is increasingly applied to high-performance and low-power-consumption A/D converter circuits due to the characteristics of low power consumption, high speed and better compatibility with deep submicron technology. However, the fully dynamic comparator has the disadvantage of large offset, and especially as the CMOS process size is reduced, the offset becomes more serious, and becomes one of the major bottlenecks that limit the performance of the a/D converter. In order to reduce the offset of the fully dynamic comparator, a large-sized integrated component can be used, but this increases the area and load, and another method is to use an offset calibration technique, which can achieve higher comparison accuracy with a smaller comparator area by measuring and adjusting the offset. Full dynamic comparator offset calibration typically requires operation with the support of calibration support circuitry and calibration logic, and requires some calibration time and additional power consumption.
The quality of a calibration technique is generally measured by the performance of the calibrated circuit, the area and power consumption increased by the calibration, and the calibration time.
Fig. 1 is a conventional offset calibration circuit of a dynamic comparator, which adjusts the threshold voltage of an input tube by adjusting the load capacitance of a pre-amplified differential output terminal to cancel the original offset voltage of the comparator. The adjustment of the load capacitance may be achieved by the configurable capacitor arrays CP and CN. The configurable capacitor array is composed of m units of capacitors connected in series with switches, and if the switches are turned on, the capacitors of the units are incorporated into the load capacitors, otherwise, the capacitors of the units do not constitute the load. Typically, the switch control signal is derived from the output of an m-bit memory whose contents are obtained by a power-up calibration control circuit. Where the value of m is determined by the offset voltage calibration range and the calibration accuracy. Also, the larger the calibration range, the higher the accuracy, the larger m is required.
Fig. 2 is another conventional dynamic comparator offset calibration circuit, which operates to calibrate the comparator offset by adjusting the current of the differential branch. In circuit implementation, the calibration technique compensates for the mismatch by adjusting the gate voltage difference of the auxiliary input differential pair transistors M1 and M2. The gate of the M1 transistor is connected to a fixed voltage value, and the gate of the M2 transistor is connected to a voltage holding capacitor CH, and the voltage of the voltage holding capacitor CH is controlled by a calibration circuit. When the circuit is in a calibration mode, the two input ends of the comparator are in short circuit with a common-mode signal, the offset voltage of the circuit is amplified and compared to be output, and therefore the external control current source is controlled to draw or inject current from the capacitor CH. If the current source injects current into CH, the gate voltage of M2 is increased, increasing its discharge current. The mismatch of the auxiliary input tube current is used to compensate for the offset of the comparator itself. By comparing and compensating for a plurality of cycles, the offset of the comparator can be reduced to a smaller range. The capacitance value of the voltage holding capacitor CH is determined by the calibration accuracy of the offset of the comparator, and the higher the calibration accuracy is, the larger the capacitance value of CH is.
It is obvious that the first disadvantage of the conventional calibration method is that a configurable capacitor array, a memory and a logic controller are required to be added, and the area of the configurable capacitor array, the memory and the logic controller is proportional to the calibration range and the calibration precision; the increased pre-amp circuit load capacitance reduces the speed of the comparator. But the method can be permanently used after single calibration, does not need to be refreshed, and has no extra power consumption. The conventional calibration method two needs to add a voltage holding capacitor CH, and the area of the voltage holding capacitor CH is in direct proportion to the calibration precision. In addition, the adjustment of the grid voltage of the auxiliary input tube needs a plurality of periods of successive approximation to be completed, and the calibration time is increased; calibration requires the involvement of the entire comparator (including the dynamic preamplifier and subsequent latch circuits), which is costly in power consumption. Therefore, a technical solution for dynamic comparator and offset calibration thereof is needed to implement offset calibration with low area cost, short calibration time, and low power consumption cost.
Disclosure of Invention
In view of this, it is desirable to provide a dynamic comparator and a method for performing offset calibration thereof, which can perform offset calibration with low area cost, short calibration time, and low power consumption cost.
The technical scheme of the embodiment of the invention is realized as follows:
an embodiment of the present invention provides a dynamic comparator, where the dynamic comparator includes: a latch and a preamplifier including a preamplification circuit and a calibration auxiliary circuit;
the calibration auxiliary circuit comprises a charge storage capacitor for storing offset voltage, a charge-discharge switch, a common-mode switch, a first calibration control switch and a second calibration control switch;
the grid electrode of an input differential NMOS tube of the pre-amplification circuit is respectively connected with a first end of the charge storage capacitor and a first end of the charge and discharge switch, a second end of the charge storage capacitor is respectively connected with a first end of the common mode switch and an input end of the dynamic comparator, a second end of the common mode switch is connected with an input common mode voltage power supply of the pre-amplification circuit, and a second end of the charge and discharge switch is connected to an output end of the pre-amplifier;
the drain electrode of the input differential NMOS tube is connected with the first end of the first calibration control switch;
the source electrode of the input differential NMOS tube is connected with the first end of the second calibration control switch;
the output end of the preamplifier is connected with the input stage of the latch.
In the above solution, the on and off of the first calibration control switch is controlled by a calibration trigger clock signal, and the on and off of the second calibration control switch is controlled by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.
In the above scheme, the second end of the charge storage capacitor is connected to the first end of the differential input switch of the pre-amplification circuit, and the second end of the differential input switch is connected to the input end of the dynamic comparator; wherein the differential input switch is off in the offset calibration state and on in the comparison state.
In the above scheme, a second end of the first calibration control switch is connected to a first end of a first comparison control switch of the pre-amplification circuit, wherein the second end of the first comparison control switch is connected to the calibration voltage power supply;
the first end of the second calibration control switch is connected with the first end of a second comparison control switch of the pre-amplifying circuit, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplifying circuit.
In the above scheme, the on and off of the first comparison control switch is controlled by comparing a trigger clock signal, and the on and off of the second comparison control switch is controlled by inverting the comparison trigger clock signal; the first comparison control switch is a PMOS tube, and the second comparison control switch is an NMOS tube.
In the above scheme, the on and off of the charge and discharge switch is controlled by a control signal obtained by inverting the control signal of the common mode switch and a signal obtained by performing an and operation on the voltage signal of the output end.
The embodiment of the present invention further provides a method for calibrating offset applied to the dynamic comparator, where the method includes:
in an offset calibration state, the first calibration control switch is turned on, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned off, and a calibration voltage power supply of the pre-amplification circuit charges the input differential NMOS transistor to enable the voltage value of the drain electrode of the input differential NMOS transistor to reach a calibration voltage;
and the first calibration control switch is turned off, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned on, the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube, the charge storage capacitor is charged, and offset charge is stored in the charge storage capacitor.
In the above aspect, the method further includes:
and the first calibration control switch and the charge and discharge switch are respectively arranged to be turned off, the second calibration control switch and the common mode switch are respectively arranged to be turned on, and the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube and stops charging the charge storage capacitor.
In the above aspect, the method further includes:
in a comparison state, the first calibration control switch is turned on, the common mode switch, the charge and discharge switch and the second calibration control switch are turned off respectively, a differential amplification signal input from an input end of the dynamic comparator and offset voltage corresponding to the offset charge stored in the charge storage capacitor are superposed to obtain equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and is judged by the latch to obtain a comparison result of the differential amplification signal.
In the above aspect, the method further includes:
the first calibration control switch is turned on and off by a calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.
In the above aspect, the method further includes:
when the differential input switch is in the maladjustment calibration state, the differential input switch is switched off; wherein a first terminal of the differential input switch is connected to a second terminal of the charge storage capacitor, and a second terminal of the differential input switch is connected to an input terminal of the dynamic comparator.
In the above aspect, the method further includes:
when a first comparison control switch of the pre-amplification circuit is switched on and a second comparison control switch of the pre-amplification circuit is switched off, the dynamic comparator is in an offset calibration state; wherein,
a second end of the first calibration control switch is connected with a first end of the first comparison control switch, and a second end of the first comparison control switch is connected with the calibration voltage power supply;
the first end of the second calibration control switch is connected with the first end of the second comparison control switch, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplification circuit.
In the above aspect, the method further includes:
and controlling the on and off of the charge and discharge switch through a control signal obtained by inverting the control signal of the common mode switch and a signal obtained by performing AND operation on the voltage signal of the output end.
According to the dynamic comparator and the offset calibration method thereof, the offset voltage of the dynamic comparator is stored in the series capacitor at the input end of the dynamic comparator to eliminate the offset, a large number of memories and control lines are not needed, only the power consumption of the preamplifier is needed, and the calibration convergence time is not needed, so that the offset of the dynamic preamplifier is effectively reduced, the conversion precision of the comparator is improved, and the dynamic comparator and the offset calibration method thereof have the advantages of small area cost, small power consumption cost and high calibration speed.
Drawings
FIG. 1 is a schematic diagram of a first conventional dynamic comparator offset calibration circuit;
FIG. 2 is a schematic diagram of a second conventional offset calibration circuit of a dynamic comparator;
fig. 3 is a schematic structural diagram of a dynamic comparator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a dynamic comparator according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a preamplifier and a latch of a dynamic comparator according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a control circuit of a charge and discharge switch according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a method for performing offset calibration of a dynamic comparator according to a second embodiment of the present invention;
FIG. 8 is a circuit diagram illustrating an offset charge storing process of a dynamic comparator according to a third embodiment of the present invention;
fig. 9 is a circuit schematic diagram of a comparison process of a dynamic comparator according to a third embodiment of the present invention;
FIG. 10 is a timing diagram of a dynamic comparator according to a third embodiment of the present invention;
description of reference numerals: a charge storage capacitor, Ch; a charge and discharge switch, K2; common mode switch, F2; a first calibration control switch, K11; a second calibration control switch, K12; a first input differential NMOS transistor, M1; a second input differential NMOS transistor, M2; differential input switch, F1; a first comparison control switch F1K 1; the second comparison controls the switch F1K 2.
Detailed Description
The following describes the embodiments in further detail with reference to the accompanying drawings.
Example one
In one embodiment of the present invention, a dynamic comparator is provided, as shown in fig. 3, where the dynamic comparator is used for comparing the dynamic signal with the reference signalThe comparator includes: a latch and a preamplifier including a preamplification circuit and a calibration auxiliary circuit; the calibration auxiliary circuit comprises a charge storage capacitor Ch for storing an offset voltage, a charge and discharge switch K2, a common mode switch F2, a first calibration control switch K11 and a second calibration control switch K12; the grid electrode of an input differential NMOS tube of the pre-amplifying circuit is respectively connected with a first end of a charge storage capacitor Ch and a first end of a charge-discharge switch K2, a second end of the charge storage capacitor Ch is respectively connected with a first end of a common mode switch F2 and an input end of the dynamic comparator, and a second end of the common mode switch F2 is connected with an input common mode voltage power supply V of the pre-amplifying circuitCMThe second end of the charge and discharge switch K2 is connected to the output end of the preamplifier; the drain electrode of the input differential NMOS tube is connected with the first end of the first calibration control switch; the source electrode of the input differential NMOS tube is connected with the first end of the second calibration control switch; the output end of the preamplifier is connected with the input stage of the latch. The pre-amplifying circuit comprises a fully symmetrical circuit formed by a first input differential NMOS tube M1 and a second input differential NMOS tube M2, the drain electrode of the first input differential NMOS tube and the drain electrode of the second input differential NMOS tube are output ends of the pre-amplifier, and the voltage of the output ends is connected with the input stage of the latch. As shown in fig. 3, the gate, the drain and the source of the first input differential NMOS transistor M1 and the second input differential NMOS transistor M2 are connected to a calibration auxiliary circuit including a charge storage capacitor Ch, a charge/discharge switch K2, a common mode switch F2, a first calibration control switch K11 and a second calibration control switch K12, respectively. By adding a calibration auxiliary circuit in the preamplifier, the dynamic comparator performs offset storage and normal comparison in each period.
As shown in fig. 3, the turn-on and turn-off of the first calibration control switch is controlled by a calibration trigger clock signal, and the turn-on and turn-off of the second calibration control switch is controlled by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube. Here, when the calibration trigger clock signal is CLKK1Is passed through CLKK1The first calibration control switch K11 and the second calibration control switch K12 are controlled simultaneously, and the states of the first calibration control switch K11 and the second calibration control switch K12 are opposite, specifically, CLKK1The low level of (b) controls the first calibration control switch K11 to be turned on, and the second calibration control switch K12 to be turned off; CLKK1The high level of (b) controls the first calibration control switch K11 to be off and the second calibration control switch K12 to be on.
When the first calibration control switch is a PMOS transistor and the second calibration control switch is an NMOS transistor, the first end of the first calibration control switch is a source, the second end of the first calibration switch is a drain, the first end of the second calibration control switch is a source, and the second end of the second calibration control switch is a drain.
Here, the trigger clock signal CLK is calibratedK1The low level controls the first calibration control switch K11 to be turned on and the second calibration control switch K12 to be turned off, and during the offset storing period, as shown in FIG. 4, the clock signal CLK is calibratedK1The low level phase of the control node P and the node N is charged to the voltage V of the calibration voltage sourceDD(ii) a Calibrating a trigger clock signal CLKK1The high-level phase of the control node P and the node N is subjected to common-mode discharge through the input differential pair transistors (M1, M2). During the common-mode discharge process of the input differential pair transistors, the discharge speed of the nodes P and N is influenced by the mismatch of the circuits. The charge storage capacitors Ch corresponding to the nodes P and N track and store the voltages (Vp and Vn) of the nodes P and N. Wherein, the node P and the node N are the output end of the preventive amplifier and are connected with the input stage of the latch.
The circuit structure of the pre-amplifying circuit of the dynamic comparator provided by the embodiment of the invention is shown in fig. 5, and the circuit structure of the latch is shown in fig. 6, wherein the output end node P (V) of the pre-amplifying circuitP) Node N (V)N) Input stage V of respective AND latchIP、VINConnected so that the output signal of the pre-amplifying circuit is used as the input signal of the latch, and the latch makes an amplification decision based on the voltage signal amplified by the pre-amplifying circuit, and the slave dynamic comparator is connectedDifferential input end V of pre-amplifying circuitIP、VINThe input differential signals are compared.
Here, the pre-amplifying circuit further includes a differential input switch F1 and first and second comparison control switches F1K1 and F1K 2.
As shown in fig. 5, the second terminal of the charge storage capacitor Ch is connected to the first terminal of the differential input switch F1 of the pre-amplifying circuit, and the second terminal of the differential input switch F1 is connected to the input terminal of the dynamic comparator; wherein the differential input switch is off in the offset calibration state and on in the comparison state. Wherein the input end of the pre-amplifying circuit comprises VIPAnd VIN。
As shown in fig. 5, a second terminal of the first calibration control switch K11 is connected to a first terminal of a first comparison control switch F1K1 of the pre-amplifying circuit, wherein the second terminal of the first comparison control switch F1K1 is connected to the calibration voltage power supply; a first terminal of the second calibration control switch K12 is connected to a first terminal of a second comparison control switch F1K2 of the pre-amplifying circuit, and a second terminal of the second calibration control switch K12 is connected to a second terminal of the second comparison control switch F1K2 and a ground terminal of the pre-amplifying circuit, respectively. Wherein, the voltage of the calibration voltage power supply VDD is VDD。
In the embodiment of the invention, the on and off of the first comparison control switch F1K1 are controlled by comparing the trigger clock signal, and the on and off of the second comparison control switch F1K2 are controlled by inverting the comparison trigger clock signal; the first comparison control switch F1K1 is a PMOS transistor, and the second comparison control switch F1K2 is an NMOS transistor. When the first comparison control switch is a PMOS transistor and the second comparison control switch is an NMOS transistor, the first end of the first comparison control switch is a source electrode, the second end of the first comparison switch is a drain electrode, the first end of the second comparison control switch is a source electrode, and the second end of the second comparison control switch is a drain electrode.
Here, when the comparison trigger clock signal is CLKF1KIs passed through CLKF1KThe first comparison control switch F1K1 and the second comparison control switch F1K2 are controlled simultaneously and the states of the first comparison control switch F1K1 and the second comparison control switch F1K2 are reversed, specifically CLKF1KThe low level of the first comparator control switch F1K1 is turned on, and the second comparator control switch F1K2 is turned off; CLKF1KThe high level of (1) controls the first comparison control switch F1K1 to be off and the second comparison control switch F1K2 to be on.
In the embodiment of the present invention, as shown in fig. 7, the on and off of the charge and discharge switch K2 are controlled by a signal obtained by performing an and operation on a control signal obtained by inverting a control signal of the common mode switch F2 and a voltage signal of the output terminal. Therefore, the common mode switch K2 is controlled to be at a high level or a low level by the voltage Vp of the node P/the voltage Vn of the node N and the AND gate of the control signal of the charge and discharge switch F2, wherein the control signal CLK of F2F1Control signal CLK of K2K2A short delay.
In practical applications, to ensure that the input differential NMOS transistor of the preamplifier circuit normally operates in the saturation region in the following comparison time, Vp and Vn stored in the charge storage capacitor Ch corresponding to the node P and the node N need to be controlled. When the voltages of the node P and the node N fall within a certain voltage range, the charge and discharge switch K2 needs to be turned off in time. The calibration technology adds one discharging and charging operation to the output node of the pre-amplifying circuit through the change of the calibration clock K1 from low level to high level in the reset stage of the comparator, and completes the storage of offset charge in the discharging process of the node P and the node N.
In the dynamic comparator provided by the embodiment of the invention, the first calibration control switch F11 and the second calibration control switch F12 are added in the pre-amplifying circuit, and the trigger clock signal CLK is calibrated in the control signal of the dynamic comparator through the on and off of the first calibration control switch F11 and the second calibration control switch F12K1The change from low level to high level adds one discharging and charging operation to the output node of the pre-amplifying circuit, and in the discharging process of the node P and the node NTo complete the storage of the offset charge in the charge storage capacitor.
In the embodiment of the invention, the charge storage capacitor Ch for storing the offset voltage, the charge and discharge switch K2, the common mode switch F2, the first calibration control switch K11 and the second calibration control switch K12 are added to the pre-amplification circuit, and the offset voltage of the dynamic comparator is stored in the series capacitor Ch at the input end to eliminate the offset, so that a large number of memories and control lines are not needed, the power consumption of the pre-amplifier is only needed, the calibration convergence time is not needed, the offset of the dynamic pre-amplifier is effectively reduced, the conversion precision of the comparator is improved, and the dynamic pre-amplifier has the advantages of small area cost, small power consumption cost and high calibration speed.
Compared with the traditional dynamic comparator offset calibration technology, the dynamic comparator provided by the embodiment of the invention does not need a large number of memories and control lines, and the size of the offset charge storage capacitor Ch is related to the parasitic capacitance of the input MOS tube; the dynamic comparator stores the offset voltage before normal comparison every time, and the process only needs the power consumption of the preamplifier, does not need the participation of a subsequent latch circuit and has low power consumption cost; the principle is simple and easy to realize, calibration is completed instantly without time spent in gradual convergence, the system can be electrified to work without a special calibration process, and the calibration time is short. Compared with the traditional offset calibration technology, the offset calibration technology of the dynamic comparator has comprehensive advantages in three aspects of area, power consumption and calibration time.
Example two
In the embodiment of the present invention, a method for calibrating the offset of a dynamic comparator provided in the embodiment of the present invention is described with reference to the dynamic comparator shown in fig. 3 to fig. 6, as shown in fig. 7, the method includes:
s701, in an offset calibration state, the first calibration control switch is turned on, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned off, and a calibration voltage power supply of the pre-amplification circuit charges the input differential NMOS tube to enable the voltage value of the drain electrode of the input differential NMOS tube to reach a calibration voltage;
s702, turning off the first calibration control switch, turning on the second calibration control switch, the common mode switch, and the charge/discharge switch, respectively, performing common mode discharge on the drain voltage of the input differential NMOS transistor through the input differential NMOS transistor, charging the charge storage capacitor, and storing offset charges in the charge storage capacitor.
Wherein, in S701, the discharging operation of the output node of the pre-amplifying circuit is completed once; in S702, the charging operation of the output node of the pre-amplification circuit is completed once, so that the charge storage capacitor, in which the offset charge is stored, is charged from the output node of the pre-amplification circuit.
In an embodiment of the present invention, the first calibration control switch and the charge/discharge switch are respectively turned off, the second calibration control switch and the common mode switch are respectively turned on, and the drain voltage of the input differential NMOS transistor performs common mode discharge via the input differential NMOS transistor and stops charging the charge storage capacitor.
In a comparison state, the first calibration control switch is turned on, the common mode switch, the charge and discharge switch and the second calibration control switch are turned off respectively, the differential amplification signal input from the input end and the offset voltage corresponding to the offset charge stored in the charge storage capacitor are superposed to obtain an equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and is judged by the latch to obtain a comparison result of the differential amplification signal.
Wherein the first calibration control switch is turned on and off by a calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.
When the differential input switch is in the maladjustment calibration state, the differential input switch is switched off; the first end of the differential input switch is connected with the second end of the charge storage capacitor, and the second end of the differential input switch is connected with the input end of the pre-amplifying circuit.
When a first comparison control switch of the pre-amplification circuit is switched on and a second comparison control switch of the pre-amplification circuit is switched off, the dynamic comparator is in an offset calibration state; a second end of the first calibration control switch is connected with a first end of the first comparison control switch, and a second end of the first comparison control switch is connected with the calibration voltage power supply; the first end of the second calibration control switch is connected with the first end of the second comparison control switch, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplification circuit. And the on and off of the charge and discharge switch are controlled by a control signal obtained by inverting the control signal of the common mode switch and a signal obtained by performing AND operation on the voltage signal of the output end.
EXAMPLE III
In this embodiment, a method for calibrating the offset of the dynamic comparator shown in fig. 3 to 6 according to an embodiment of the present invention is described with reference to fig. 8 (a), 8 (b), 9 (a) and 9 (b).
In the preamplifier section, the input differential pair transistors M1 and M2, the first comparison control switch F1K1, the second comparison control switch F1K2 and the differential input switch F1 form a normal preamplifier circuit of the comparator, and the charge storage capacitor Ch, the first calibration control switch K11, the second calibration control switch K12, the charge and discharge switch K2 and the common mode switch F2, which are connected in series at the input end of the preamplifier circuit, form a calibration auxiliary circuit of the comparator. The comparator is divided into two stages of offset storage (offset calibration state) and normal comparison (comparison state), specifically, the charge storage process in the offset storage stage is shown in fig. 8 (a) and 8 (b), and the differential voltage comparison process in the normal comparison stage is shown in fig. 9 (a) and 9 (b).
In the offset storing stage, as shown in FIG. 8 (a), the flip-flop clock signal CLK is comparedF1KAnd calibrating the trigger clock signal CLKK1The first comparison control switch F1K1 and the first calibration control switch F11 (PMOS transistor) precharge the output nodes (nodes P, N) of the preamplifier to the calibration voltage V at two pointsDDAnd simultaneously, the output node out of the latch is reset to the ground, and the tail current tubes of the preamplifier and the latch are both turned off. CLK is triggered when the common mode voltage of the nodes P and N rises as shown in FIG. 8 (b)K1After the high level is changed, a tail current tube of the preamplifier is conducted, common mode discharge is started at two points of an output node P and an output node N of the preamplifier, and the discharge speed is different due to the mismatch effect of the circuit. When the common mode voltage at the nodes P and N falls to trigger the falling edge of K2, the offset voltage is stored in the corresponding input series capacitor Ch when CLKK1After the low level, the offset storing phase of the comparator is finished. In addition, to ensure that the input differential pair transistors (M1, M2) of the pre-amplifying circuit normally work in the saturation region in the next comparison time, Vp and Vn stored by Ch need to be controlled. In circuit implementation, K2 is controlled to be high or low by Vp/Vn and an and gate of the switch F2, and K1 is a short delay of K2, as shown in fig. 6.
The comparator then triggers the clock CLK by comparisonF1KControl enters the normal comparison phase, shown. The equivalent input of the comparator is the voltage value obtained by superposing the input signal and the offset voltage. When CLK is used, as shown in FIG. 9 (a)F1KWhen the voltage is low, the comparator is reset. When CLK is used, as shown in FIG. 9 (a)F1KWhen the voltage is high level, the preamplifier amplifies the input differential signal, triggers the latch to carry out amplification judgment through positive feedback, and then outputs a comparison result.
As shown in the timing diagram of fig. 10, the circuit of the dynamic comparator offset calibration technique according to the embodiment of the present invention has 5 operation states:
(1) calibrating a trigger clock CLKK1And comparing the trigger clock CLKF1KAn input capacitor precharge state of low, K2 off, F2 off, F12 off, F11 on;
(2) calibrating a trigger clock CLKK1Toggling clock CLK for high and compareF1KA calibration charge storage state of low, K2 on, F2 on, F11 on, F12 off;
(3) calibrating a trigger clock CLKK1To high, compare the trigger clock CLKF1KA calibration charge stop storage state of low, K2 off, F2 on, F11 on, F12 off;
(4) calibrating a trigger clock CLKK1And comparing the trigger clock CLKF1KThe comparator which is low, K2 is off, F2 is off, F11 is on, and F12 is off is in a reset state before normal comparison operation; and
(5) calibrating a trigger clock CLKK1Toggling clock CLK for Low and comparisonF1KThe comparators with high, K2 open, F2 open, F11 open and F12 closed compare the working state normally.
In the above state, in which the calibration charge stop storing state and the reset state before the comparator operates normally are almost the same, the control signal of F2 is delayed by a small amount from the control signal of K2 in the timing chart.
In the embodiment of the present invention, the first calibration control switch F11 and the second calibration control switch F12 may be implemented by MOS transistors, and the specific switch forms of the common mode switch F2 and the charge/discharge switch K2 are not limited in any way in the embodiment of the present invention.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (13)
1. A dynamic comparator, wherein the dynamic comparator comprises: a latch and a preamplifier including a preamplification circuit and a calibration auxiliary circuit;
the calibration auxiliary circuit comprises a charge storage capacitor for storing offset voltage, a charge-discharge switch, a common-mode switch, a first calibration control switch and a second calibration control switch;
the grid electrode of an input differential NMOS tube of the pre-amplification circuit is respectively connected with a first end of the charge storage capacitor and a first end of the charge and discharge switch, a second end of the charge storage capacitor is respectively connected with a first end of the common mode switch and an input end of the dynamic comparator, a second end of the common mode switch is connected with an input common mode voltage power supply of the pre-amplification circuit, and a second end of the charge and discharge switch is connected to an output end of the pre-amplifier;
the drain electrode of the input differential NMOS tube is connected with the first end of the first calibration control switch;
the source electrode of the input differential NMOS tube is connected with the first end of the second calibration control switch;
the output end of the preamplifier is connected with the input stage of the latch.
2. The dynamic comparator according to claim 1, wherein the first calibration control switch is controlled to turn on and off by a calibration trigger clock signal, and the second calibration control switch is controlled to turn on and off by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.
3. The dynamic comparator according to claim 1, wherein a second terminal of the charge storage capacitor is connected to a first terminal of a differential input switch of the pre-amplification circuit, and a second terminal of the differential input switch is connected to an input terminal of the dynamic comparator; wherein the differential input switch is off in the offset calibration state and on in the comparison state.
4. The dynamic comparator according to claim 1 or 2, wherein a second terminal of the first calibration control switch is connected to a first terminal of a first comparison control switch of the pre-amplification circuit, wherein the second terminal of the first comparison control switch is connected to the calibration voltage supply;
the first end of the second calibration control switch is connected with the first end of a second comparison control switch of the pre-amplifying circuit, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplifying circuit.
5. The dynamic comparator according to claim 4, wherein the turning on and off of the first comparison control switch is controlled by comparing a trigger clock signal, and the turning on and off of the second comparison control switch is controlled by inverting the comparison trigger clock signal; the first comparison control switch is a PMOS tube, and the second comparison control switch is an NMOS tube.
6. The dynamic comparator according to claim 1, wherein the on and off states of the charge and discharge switches are controlled by a signal obtained by performing an and operation on a control signal obtained by inverting a control signal of the common mode switch and a voltage signal of the output terminal.
7. A method for the offset calibration of a dynamic comparator, the method being applied to the dynamic comparator of claim 1, the method comprising:
in an offset calibration state, the first calibration control switch is turned on, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned off, and a calibration voltage power supply of the pre-amplification circuit charges the input differential NMOS transistor to enable the voltage value of the drain electrode of the input differential NMOS transistor to reach a calibration voltage;
and the first calibration control switch is turned off, the second calibration control switch, the common mode switch and the charge and discharge switch are respectively turned on, the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube, the charge storage capacitor is charged, and offset charge is stored in the charge storage capacitor.
8. The method of claim 7, further comprising:
and the first calibration control switch and the charge and discharge switch are respectively arranged to be turned off, the second calibration control switch and the common mode switch are respectively arranged to be turned on, and the drain voltage of the input differential NMOS tube carries out common mode discharge through the input differential NMOS tube and stops charging the charge storage capacitor.
9. The method of claim 7, further comprising:
in a comparison state, the first calibration control switch is turned on, the common mode switch, the charge and discharge switch and the second calibration control switch are turned off respectively, a differential amplification signal input from an input end of the dynamic comparator and offset voltage corresponding to the offset charge stored in the charge storage capacitor are superposed to obtain equivalent voltage, and the equivalent voltage is amplified by the pre-amplification circuit and is judged by the latch to obtain a comparison result of the differential amplification signal.
10. The method of claim 7, further comprising:
the first calibration control switch is turned on and off by a calibration trigger clock signal, and the second calibration control switch is turned off and on by inverting the calibration trigger clock signal; the first calibration control switch is a PMOS tube, and the second calibration control switch is an NMOS tube.
11. The method of claim 7, further comprising:
when the differential input switch is in the maladjustment calibration state, the differential input switch is switched off; wherein a first terminal of the differential input switch is connected to a second terminal of the charge storage capacitor, and a second terminal of the differential input switch is connected to an input terminal of the dynamic comparator.
12. The method of claim 7, further comprising:
when a first comparison control switch of the pre-amplification circuit is switched on and a second comparison control switch of the pre-amplification circuit is switched off, the dynamic comparator is in an offset calibration state; wherein,
a second end of the first calibration control switch is connected with a first end of the first comparison control switch, and a second end of the first comparison control switch is connected with the calibration voltage power supply;
the first end of the second calibration control switch is connected with the first end of the second comparison control switch, and the second end of the second calibration control switch is respectively connected with the second end of the second comparison control switch and the grounding end of the pre-amplification circuit.
13. The method of claim 7, further comprising:
and controlling the on and off of the charge and discharge switch through a control signal obtained by inverting the control signal of the common mode switch and a signal obtained by performing AND operation on the voltage signal of the output end.
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| CN201610933177.6A CN108011635B (en) | 2016-10-31 | 2016-10-31 | Dynamic comparator and offset calibration method thereof |
| PCT/CN2017/077576 WO2018076599A1 (en) | 2016-10-31 | 2017-03-21 | Dynamic comparator, method for calibrating offset thereof, and computer storage medium |
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| CN201610933177.6A CN108011635B (en) | 2016-10-31 | 2016-10-31 | Dynamic comparator and offset calibration method thereof |
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| CN108011635B (en) | 2020-12-08 |
| WO2018076599A1 (en) | 2018-05-03 |
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