CN102386923A - Asynchronous successive approximation analog-to-digital converter and conversion method - Google Patents
Asynchronous successive approximation analog-to-digital converter and conversion method Download PDFInfo
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- CN102386923A CN102386923A CN2011102809638A CN201110280963A CN102386923A CN 102386923 A CN102386923 A CN 102386923A CN 2011102809638 A CN2011102809638 A CN 2011102809638A CN 201110280963 A CN201110280963 A CN 201110280963A CN 102386923 A CN102386923 A CN 102386923A
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Abstract
The invention discloses an asynchronous successive approximation analog-to-digital converter and a conversion method. The asynchronous successive approximation analog-to-digital converter comprises: a sampling network, a main capacitor array, an auxiliary capacitor array, a comparator and a logic control circuit. The sampling network of the main capacitor array uses a bootstrap switch. The sampling network of the auxiliary capacitor array uses a CMOS switch. Each two same capacitors in the main capacitor array are in a group. A capacitance value size is reduced as two times relationship. Top crowns of all the capacitors and the bootstrap switch are connected and output to the comparator. The each two same capacitors in the auxiliary capacitor array are in one group. The capacitance value size is reduced as four times relationship. The top crowns of all the capacitors and the CMOS switch are connected and output to the comparator. The comparator comprises a preamplifier and a latch and compares the size of an output voltage of the main capacitor array and the auxiliary capacitor array. The logic control circuit uses an asynchronous sequential control capacitor array to successively complete switching. A power consumption efficiency of the analog-to-digital converter can be effectively raised. And demands of capacitor coupling and a peripheral circuit can be reduced. The method is suitable for a deep-submicron low voltage design.
Description
Technical field
The present invention relates to a kind of asynchronous gradually-appoximant analog-digital converter and conversion method; Be particularly related to a kind of through improving retrieval mode; Improve power consumption efficiency, reduce electric capacity coupling and peripheral circuit demand, and be applicable to the asynchronous gradually-appoximant analog-digital converter of deep-submicron low supply voltage.
Technical background
Gradually-appoximant analog-digital converter is a kind of type that is applied to medium accuracy, medium sample rate, with respect to other types analog to digital converters such as flash-type, pipeline-types the highest power consumption efficiency is arranged, and in medical treatment and portable equipment, is widely used.
Traditional synchronous gradually-appoximant analog-digital converter needs a High Speed System clock (transducer of sample frequency is resolved figure place doubly); No matter be to produce in inside; Still direct input all can increase the extra power consumption of chip outside sheet, lets the high power consumption efficiency of successive approximation have a greatly reduced quality.
Because gradually-appoximant analog-digital converter need be used the capacitor array that twice increases progressively, the coupling between the minimum and maximum electric capacity has limited the overall precision of analog to digital converter.Adopt specific capacitance and centrosymmetric laying out pattern can reduce the influence of this restriction, but can not be from address this problem at all, a lot of designs adopt the mode of figure adjustment to improve the precision of electric capacity coupling.
Gradually-appoximant analog-digital converter approaches final result one by one through the reference voltage that switching is connected on the electric capacity bottom crown; The electric charge that consumes in the switch-capacitor is the main source of this type analog to digital converter power consumption, and the switching mode that service efficiency is higher also becomes one of main direction of studying of further raising power consumption efficiency.
Summary of the invention
The object of the invention is; Through a kind of asynchronous gradually-appoximant analog-digital converter and conversion method are provided; Improvement approaches searching algorithm and uses asynchronous SECO; Improve the power consumption efficiency of gradually-appoximant analog-digital converter, reduce electric capacity coupling and peripheral circuit demand, and be applicable to the deep-submicron low supply voltage.
The present invention adopts following technological means to realize:
A kind of asynchronous gradually-appoximant analog-digital converter comprises: sampling network, main capacitance array, attach capacitor array, comparator and logic control circuit.
The sampling network of main capacitance array is connected respectively to the normal phase input end and the reverse input end of difference analogue input signal by two bootstrap type switches; The sampling network that attaches capacitor array is connected to the common mode reference voltage of analog input signal by two cmos switches.
An end of the top crown of all electric capacity and the aforementioned bootstrap type switch input comparator that links together in the main capacitance array; Wherein per two identical electric capacity are one group; Bottom crown passes through inverter controlling by the output of logic control circuit; The capacitance size is successively decreased according to the relation of twice one by one, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array.
An end that attaches top crown and the aforementioned cmos switch of all electric capacity in the capacitor array input comparator that links together; Wherein per two identical electric capacity are one group; Bottom crown passes through inverter controlling by the output of logic control circuit; The capacitance size is successively decreased according to four times relation one by one, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array.
Comparator is through comparing main capacitance array and the voltage that attaches the capacitor array top crown, output comparative result and the signal of relatively accomplishing.
Logic control circuit receives from the comparative result of comparator and relatively accomplishes signal; Correspondingly alternately switch the main capacitance array respectively and attach capacitor array until accomplishing all comparisons of once sampling, and then all bottom crown control signals are reset to initial value begin to sample next time.
A kind of asynchronous D conversion method that approaches one by one comprises following several steps:
Step 1: the bottom crown control signal of resetting all is an initial value.
Step 2: according to the first time comparative result switch and to attach the corresponding control signal of one group of electric capacity maximum in the capacitor array: if comparative result, then switches to its output+1/2Vref (difference analogue input reference signal arrive at+Vref-Vref between) for just; If comparative result then switches to its output-1/2Vref for negative.
Step 3: switch the corresponding control signal of one group of electric capacity maximum in the main capacitance array according to the comparative result of a new round once more behind the completing steps 2: 1. if step 2 comparative result for just: if this comparative result for just, the then operation of switching completion-3/4Vref; If this comparative result for negative, then switches the operation of completion-1/4Vref.2. if step 2 comparative result is negative: if this comparative result then switches the operation of completion+1/4Vref for just; If this comparative result for negative, then switches the operation of completion+3/4Vref.
Step 4: by that analogy; Repetitive cycling step 2 and step 3 are until switching to the main capacitance array and attaching one group of minimum in capacitor array electric capacity; Export the binary code that relatively obtains then and convert signal, finish this sample conversion process, wait for getting into next time.
The main capacitance array with attach that per two electric capacity are one group in the capacitor array, one is played the effect that adds reference voltage, another plays the effect that deducts reference voltage, changing the initial value of its control signal in sampling process just can complete operation.
The present invention compared with prior art has following remarkable advantages and beneficial effect:
The present invention uses the gradually-appoximant analog-digital converter of asynchronous SECO, be operated in (less than 1 volt) under the low-voltage, has saved the link that peripheral circuit provides the High Speed System clock.Through the searching algorithm that approaches after improving, the coupling demand to electric capacity in the tradition analog to digital converter of the same type is relax in the past 4 times, and reduced the power consumption in the electric capacity handoff procedure.Because comparison reference voltage uses supply voltage and ground, therefore no longer need conducting resistance with the buffer that provides in the cmos switch of signal changes in amplitude and the peripheral circuit.
In sum, the present invention has realized the asynchronous gradually-appoximant analog-digital converter of Low-voltage Low-power, has improved power consumption efficiency, has reduced electric capacity coupling and peripheral circuit demand.
Description of drawings
Fig. 1 is the structured flowchart of asynchronous gradually-appoximant analog-digital converter;
Fig. 2 is the circuit diagram of asynchronous gradually-appoximant analog-digital converter in the embodiment of the invention;
Fig. 3 is the circuit diagram of comparator in the embodiment of the invention;
Fig. 4 is the structure chart of logic control circuit in the embodiment of the invention;
Fig. 5 is the circuit diagram of logic control circuit unit 1 in the embodiment of the invention;
Fig. 6 is the circuit diagram of logic control circuit unit 2 in the embodiment of the invention;
Fig. 7 is the sequential sketch map of comparator in the embodiment of the invention;
Fig. 8 is main capacitance array in the embodiment of the invention and the simulation result sketch map that attaches capacitor array output;
Fig. 9 is the fast Fourier transform simulation result sketch map of analog to digital converter output in the embodiment of the invention.
Symbol description:
201: the main capacitance array; 202: attach capacitor array; 203: the bootstrap type sampling switch; 204: comparator; 205: logic control circuit;
801: analog input signal; 802: the main capacitance array output signal; 803: attach capacitor array output signal.
The practical implementation method
Below in conjunction with Figure of description specific embodiment of the present invention is explained:
As shown in Figure 1, the structured flowchart of a kind of asynchronous gradually-appoximant analog-digital converter of the present invention comprises: sampling network, main capacitance array, attach capacitor array, comparator and logic control circuit.What realize in the embodiment of the invention is the gradually-appoximant analog-digital converter of one 8 bit, 50 megahertz sample rates.
Therefore the input signal of main capacitance array adopts the bootstrap type sampling switch owing to be time dependent analog signal; The input signal that attaches capacitor array is a common mode reference voltage, does not change in time, therefore adopts the CMOS sampling switch.
Fig. 2 has provided main capacitance array and the circuit diagram that attaches capacitor array.The main capacitance array comprises the electric capacity that 13 top crowns link together; The bottom crown ground connection of 1 electric capacity wherein; Capacitance size is C*262/3 (C is a specific capacitance), and per two of other 12 electric capacity are one group, and bottom crown is by the output process inverter controlling of logic control circuit; Maximum one group is 32*C, and minimum one group is 1*C; Attach capacitor array and comprise the electric capacity that 9 top crowns link together; The bottom crown ground connection of 1 electric capacity wherein; Capacitance size is C*770/3, and per two of other 8 electric capacity are one group, and bottom crown is by the output process inverter controlling of logic control circuit; Maximum one group is 64*C, and minimum one group is 1*C.
Fig. 3 has provided the circuit diagram of comparator.Two differential pairs are adopted in input, and wherein IP and IN are the output of main capacitance array, and REF1 and REF2 are the output that attaches capacitor array.On the left of Fig. 3 is prime amplifier, enlarges the gap between the voltage to be compared; The right side is latch (latch), and the gap between the voltage is further enlarged to supply voltage and ground.In order to simplify peripheral circuit, prime amplifier is not to use reference current source to do biasing, does biasing but introduce clock signal through voltage-controlled current source, so can when need not amplifying, turn off amplifier yet and reduce power consumption.Likewise, clock signal can be turn-offed latch when comparator is idle.Relatively accomplishing signal then is NOR gate to be passed through in the output of latch obtain afterwards.
Fig. 4 has provided the structure chart of logic control circuit; Mainly form by unit 1 and unit 2; Wherein all unit 1 cascades provide the enable signal of back 8 comparisons of once sampling respectively together successively, and a part of post-processing function of unit 1 output signal is accomplished in 2 of unit.Last combinational logic then converts the output of unit 2 master to, attaches the needed control signal of capacitor array.Fig. 5 has provided the circuit diagram of unit 1, and wherein set and set_next are interfaces at the corresponding levels and previous stage and back one-level, and rdy relatively accomplishes signal, and cmp is the comparator enable signal; Fig. 6 has provided the circuit diagram of unit 2, and cmp_out is the comparative result of comparator, and rst is a reset signal, all can be effectively once before each sampling, and set is among Fig. 4 or the output of door, and rdy relatively accomplishes signal, and bit is an analog to digital converter digital code to be exported.Fig. 7 has provided the sequential chart of comparator, and the cmp enable signal is effectively low, through the comparative result of comparator output after a while cmp_out, and stablizes back output at comparative result and relatively accomplishes signal rdy.
Fig. 8 has provided under the situation of sinusoidal analog signal input, main capacitance array variation of output signals when attaching the capacitor array switched voltage.Compare with traditional approach, power consumption efficiency is improved.Fig. 9 is the fast Fourier transform simulation result of analog to digital converter output.
The key of embodiment of the present invention is to design asynchronous sequential circuit; Because parasitic influence on load and the line and between line; In various degree time-delay and the increase of rise and fall time can appear between each control signal; This problem can influence the realization of asynchronous controlled function on the one hand, can reduce the sample rate of analog to digital converter on the other hand.Address this problem, the device size that need to strengthen key node to be reducing rise and fall time, and the rdy signal is done enough time-delays, guarantees that under the situation of process deviation output was ready to when rdy was effective.
In sum, the present invention has reached purpose of design through this embodiment, has realized a kind of asynchronous gradually-appoximant analog-digital converter, has the power consumption efficiency height, electric capacity is mated and the low characteristics of peripheral circuit requirement.The present invention is not limited to the foregoing description, can under the situation that does not depart from scope of the present invention and spirit, it be made amendment and change.
Claims (3)
1. asynchronous gradually-appoximant analog-digital converter comprises: sampling network, main capacitance array, attach capacitor array, comparator and logic control circuit; It is characterized in that: the sampling network of main capacitance array is connected respectively to the normal phase input end and the reverse input end of difference analogue input signal by two bootstrap type switches; The sampling network that attaches capacitor array is connected to the common mode reference voltage of analog input signal by two cmos switches;
An end of the top crown of all electric capacity and the aforementioned bootstrap type switch input comparator that links together in the described main capacitance array; Wherein per two identical electric capacity are one group; Bottom crown passes through inverter controlling by the output of logic control circuit; The capacitance size is successively decreased according to the relation of twice one by one, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;
One end of described top crown that attaches all electric capacity in the capacitor array and the aforementioned cmos switch input comparator that links together; Wherein per two identical electric capacity are one group; Bottom crown passes through inverter controlling by the output of logic control circuit; The capacitance size is successively decreased according to four times relation one by one, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;
Comparator is through comparing main capacitance array and the voltage that attaches the capacitor array top crown, output comparative result and the signal of relatively accomplishing;
Logic control circuit receives from the comparative result of comparator and relatively accomplishes signal; Correspondingly alternately switch the main capacitance array respectively and attach capacitor array until accomplishing all comparisons of once sampling, and then all bottom crown control signals are reset to initial value begin to sample next time.
2. the asynchronous gradually-appoximant analog-digital converter of low-voltage according to claim 1 is characterized in that: described difference analogue input reference signal at+Vref between-the Vref.
3. asynchronous D conversion method that approaches one by one is characterized in that comprising following several steps:
Step 1: the bottom crown control signal of resetting all is an initial value;
Step 2: attach the corresponding control signal of one group of electric capacity maximum in the capacitor array according to the comparative result switching first time: if comparative result then switches to its output+1/2Vref for just; If comparative result then switches to its output-1/2Vref for negative;
Step 3: switch the corresponding control signal of one group of electric capacity maximum in the main capacitance array according to the comparative result of a new round once more behind the completing steps 2: if step 2 comparative result is for just: if this comparative result for just, the then operation of switching completion-3/4Vref; If this comparative result for negative, then switches the operation of completion-1/4Vref; If step 2 comparative result is for negative: if this comparative result then switches the operation of completion+1/4Vref for just; If this comparative result for negative, then switches the operation of completion+3/4Vref;
Step 4: by that analogy; Repetitive cycling step 2 and step 3 are until switching to the main capacitance array and attaching one group of minimum in capacitor array electric capacity; Export the binary code that relatively obtains then and convert signal, finish this sample conversion process, wait for getting into next time.
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| CN110535470A (en) * | 2019-08-26 | 2019-12-03 | 中国电子科技集团公司第二十四研究所 | A kind of comparator clock generation circuit and high speed gradual approaching A/D converter |
| CN111865319A (en) * | 2020-07-28 | 2020-10-30 | 西安电子科技大学 | Ultra-low power consumption successive approximation type analog-to-digital converter based on four-input comparator |
| CN116633353A (en) * | 2023-07-19 | 2023-08-22 | 高拓讯达(北京)微电子股份有限公司 | Low-power-consumption analog-to-digital conversion circuit |
| CN116633353B (en) * | 2023-07-19 | 2023-10-03 | 高拓讯达(北京)微电子股份有限公司 | Low-power-consumption analog-to-digital conversion circuit |
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