CN116633353A - Low-power-consumption analog-to-digital conversion circuit - Google Patents
Low-power-consumption analog-to-digital conversion circuit Download PDFInfo
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 80
- 238000005070 sampling Methods 0.000 claims abstract description 169
- 230000007958 sleep Effects 0.000 claims abstract description 47
- 239000003990 capacitor Substances 0.000 claims description 101
- 230000005059 dormancy Effects 0.000 claims description 7
- 238000003491 array Methods 0.000 claims description 4
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- 230000001934 delay Effects 0.000 claims description 3
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- 238000004891 communication Methods 0.000 description 9
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- 230000003071 parasitic effect Effects 0.000 description 6
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- 230000003111 delayed effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a low-power-consumption analog-to-digital conversion circuit, which relates to the technical field of integrated circuits, and comprises a sampling array, a pre-amplifier, a dynamic comparator, an asynchronous clock generation circuit and a successive approximation logic circuit; sampling the analog signal by the sampling array to obtain a differential signal; the pre-amplifier amplifies the differential signal to obtain a differential amplified signal; the dynamic comparator compares the voltages of two amplified signals in the differential amplified signals and outputs a comparison signal according to a comparison result; the successive approximation logic circuit latches the comparison signal to obtain a digital signal, and generates a high-level sleep signal after analog-to-digital conversion in the current sampling period is completed; the asynchronous clock generating circuit and the preamplifier enter a sleep state after receiving a high-level sleep signal, and the dynamic comparator receives a sleep control signal to enter the sleep state. By adopting the low-power-consumption analog-digital conversion circuit, the problem that the analog-digital conversion circuit has higher power consumption under the conditions of a rapid process angle and a variable sampling rate is solved.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a low-power-consumption analog-to-digital conversion circuit.
Background
With the development of deep submicron semiconductor technology, the integration level of digital circuits is higher and higher, and consumer electronics have a trend of being digitalized. However, in real life, all signals are analog signals, so that in order to facilitate the processing of the digital circuit, an analog-to-digital converter is required to quantize and sample the external analog signals to form digital signals which can be processed by the digital circuit. The charge redistribution type successive approximation (Successive Approximation Register, SAR) Analog-to-Digital Converter (ADC) Analog-to-Analog converter is simple in circuit and suitable for deep submicron technology, and along with the progress of technology nodes, the power consumption and the area of the ADC Analog-to-Analog converter are continuously reduced, and the precision is gradually increased due to the progress of technology matching. In a system, an ADC of SAR architecture is typically used, provided that the conversion rate is satisfactory.
However, in the analog-to-digital conversion circuit of the existing asynchronous clock architecture, the rate of the semiconductor process corner has a larger variance, the conversion rate of the fastest process corner is more than one time faster than the conversion rate of the slowest process corner, so that conversion is performed according to the slowest process corner, the conversion half period just meets the conversion time requirement of the slow process corner, and the conversion time is far less than the time of half period for the fast process corner. In addition, the internal clock is automatically delayed by a delay chain, the clock can still be continuously generated after the conversion is completed, the internal partial circuit is controlled to turn over, the internal partial static circuit still continuously works after the conversion is completed, and current is extracted, so that the asynchronous successive approximation type analog-to-digital conversion circuit has the problem of higher power consumption under the conditions of quick process angle and variable sampling rate.
Disclosure of Invention
In view of the above, the present application is directed to providing a low-power analog-to-digital conversion circuit to solve the problem of high power consumption of an asynchronous successive approximation analog-to-digital conversion circuit under a fast process angle and a variable sampling rate.
In a first aspect, an embodiment of the present application provides a low-power analog-to-digital conversion circuit, where the analog-to-digital conversion circuit includes a sampling array, a preamplifier, a dynamic comparator, an asynchronous clock generating circuit, and a successive approximation logic circuit;
the input end of the sampling array is connected with the output end of the external circuit, the analog signal in the current sampling period is received from the external circuit, and the analog signal is sampled to obtain a differential signal;
the input end of the pre-amplifier is connected with the output end of the sampling array, the pre-amplifier receives the differential signal, and the differential signal is amplified to obtain a differential amplified signal;
the input end of the dynamic comparator is connected with the output end of the pre-amplifier, the dynamic comparator receives the differential amplified signals, compares the voltages of two amplified signals in the differential amplified signals, and outputs a comparison signal according to the comparison result;
the input end of the successive approximation logic circuit is connected with the output end of the dynamic comparator and the output end of the asynchronous clock generation circuit, the successive approximation logic circuit latches the comparison signal according to the asynchronous clock signal generated by the asynchronous clock generation circuit to obtain a digital signal, and the first output end of the successive approximation logic circuit outputs the digital signal;
After the analog-to-digital conversion in the current sampling period is completed, the successive approximation logic circuit generates a high-level sleep signal, and a second output end of the successive approximation logic circuit outputs the high-level sleep signal;
the input end of the asynchronous clock generation circuit and the gating end of the preamplifier are respectively connected with the second output end of the successive approximation logic circuit, the asynchronous clock generation circuit and the preamplifier enter a sleep state after receiving a high-level sleep signal, and the asynchronous clock generation circuit also generates a sleep control signal according to the high-level sleep signal;
the enabling end of the dynamic comparator is also connected with the output end of the asynchronous clock generation circuit, and the dynamic comparator enters a sleep state after receiving the sleep control signal.
Optionally, the asynchronous clock generating circuit includes an exclusive or gate, a first delay circuit, and a nor gate; the first input end and the second input end of the exclusive-OR gate are respectively used as the first input end and the second input end of the asynchronous clock generation circuit and are connected with the first output end and the second output end of the dynamic comparator; the output end of the exclusive-OR gate is connected with the input end of the first delay circuit, and the output end of the first delay circuit is connected with the first input end of the NOR gate; the second input end of the NOR gate is connected with the second output end of the successive approximation logic circuit and receives the dormancy signal; the output end of the NOR gate is used as the output end of the asynchronous clock generation circuit and is connected with the enabling end of the dynamic comparator and the third input end of the successive approximation logic circuit.
Optionally, the successive approximation logic circuit includes a plurality of logic units and a second delay circuit; the first input end and the second input end of each logic unit are respectively used as the first input end and the second input end of the successive approximation logic circuit and are connected with the first output end and the second output end of the dynamic comparator, and the third input end of each logic unit is used as the third input end of the successive approximation logic circuit and is connected with the output end of the asynchronous clock generation circuit; the first output end of each logic unit is used as the first output end of the successive approximation logic circuit to output the converted digital signal; the logic units are sequentially connected end to end, the second output end of each logic unit is connected with the fourth input end of the next logic unit, and the latch signal output by the logic unit is input into the next logic unit; the third output end and the fourth output end of each logic unit are used as the third output end and the fourth output end of the successive approximation logic circuit to respectively output a first switch control signal and a second switch control signal, and the first switch control signal and the second switch control signal are input into a sampling array; the second output end of the last logic unit is connected with the input end of the second delay circuit, the latch signal is input into the second delay circuit, and the second delay circuit delays the latch signal to generate a dormant signal; the output end of the second delay circuit is used as the second output end of the successive approximation logic circuit to output a sleep signal.
Optionally, each logic unit includes a signal generator, a signal latch, and a buffer circuit; the first input end of the signal generator is used as a fourth input end of the logic unit and is connected with the second output end of the previous logic unit; the second input end of the signal generator is used as a third input end of the logic unit and is connected with the output end of the asynchronous clock generation circuit; the output end of the signal generator is connected with the third input end of the signal latch, and the output end of the signal generator is also used as the second output end of the logic unit to output a latch signal; the first input end and the second input end of the signal latch are respectively used as the first input end and the second input end of the logic unit and are connected with the first output end and the second output end of the dynamic comparator, the first output end of the signal latch is used as the first output end of the logic unit to output a digital signal, and the second output end of the signal latch is connected with the input end of the buffer circuit; the first output end and the second output end of the buffer circuit are respectively used as a third output end and a fourth output end of the logic unit to output a first switch control signal and a second switch control signal.
Optionally, the dynamic comparator is configured to start comparing the voltage of the amplified signal at the first input terminal with the voltage of the amplified signal at the second input terminal at the rising edge time of the strobe signal; if the voltage of the amplified signal of the first input end is larger than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a high-level comparison signal, and the second output end outputs a low-level comparison signal; if the voltage of the amplified signal of the first input end is smaller than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a low-level comparison signal, and the second output end outputs a high-level comparison signal; at the moment of the falling edge of the gating signal, the voltages of the first output end and the second output end of the dynamic comparator are both pulled up, the connection between the dynamic comparator and the internal power supply is disconnected, and the dynamic comparator does not consume power consumption.
Optionally, the sampling array includes a first sampling capacitor array, a second sampling capacitor array, a first upper plate switch array, and a second upper plate switch array, where the first sampling capacitor array includes a plurality of first sampling capacitors, the second sampling capacitor array includes a plurality of second sampling capacitors, the first upper plate switch array includes a plurality of first upper plate switches, and the second upper plate switch array includes a plurality of second upper plate switches; the first upper pole plate switches are used for selecting a first target voltage end from the first voltage ends according to a first switch control signal output by the successive approximation logic circuit and connecting the first target voltage end with upper pole plates of the first sampling capacitors, wherein the first voltage ends are voltage positive input ends, reference voltage ends and grounding ends; the lower polar plates of the first sampling capacitors are used as first output ends of the sampling arrays and are connected with first input ends of the preamplifiers; the plurality of second upper pole plate switches are used for selecting a second target voltage end from a plurality of second voltage ends according to a second switch control signal output by the successive approximation logic circuit and connecting the second target voltage end with upper pole plates of a plurality of second sampling capacitors, wherein the plurality of second voltage ends are voltage negative input ends, reference voltage ends and grounding ends; the lower polar plates of the plurality of second sampling capacitors are used as second output ends of the sampling arrays and are connected with second input ends of the preamplifiers; the first sampling capacitor array and the second sampling capacitor array are used for generating successive approximation voltage based on a switch control signal output by the successive approximation logic circuit.
Optionally, the sampling array further includes a first lower plate switch and a second lower plate switch; one end of the first lower polar plate switch is connected with a reference voltage end, and the other end of the first lower polar plate switch is connected with a first input end of the preamplifier; one end of the second lower polar plate switch is connected with the reference voltage end, and the other end of the second lower polar plate switch is connected with the second input end of the preamplifier.
Optionally, in the sampling array, according to an arrangement sequence of the plurality of first sampling capacitors, a capacitance value of a next first sampling capacitor is half of a capacitance value of a previous first sampling capacitor; according to the arrangement sequence of the plurality of second sampling capacitors, the capacitance value of the next second sampling capacitor is half of that of the previous second sampling capacitor.
Optionally, the number of the first sampling capacitors is equal to the number of the second sampling capacitors, which are N-1, and N is the number of bits of the digital signal obtained by conversion in one sampling period.
Optionally, the number of the plurality of logic cells in the successive approximation logic circuit is N.
The embodiment of the application has the following beneficial effects:
the low-power-consumption analog-to-digital conversion circuit provided by the embodiment of the application can generate a high-level sleep signal when the current sampling period is ended, and the high-level sleep signal is used for controlling an asynchronous clock generation circuit, a dynamic comparator and a preamplifier in the analog-to-digital conversion circuit to enter a sleep state so as to reduce power consumption.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic structural diagram of a low-power analog-to-digital conversion circuit according to an embodiment of the present application;
FIG. 2 shows a circuit diagram of a sampling array provided by an embodiment of the present application;
FIG. 3 is a circuit diagram of an analog-to-digital conversion circuit other than a sampling array according to an embodiment of the present application;
fig. 4 shows a circuit diagram of a logic unit provided by an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without making any inventive effort falls within the scope of protection of the present application.
It is noted that, prior to the development of the present application, with the development of deep submicron semiconductor technology, the integration level of digital circuits is higher and higher, and consumer electronics have a trend of being digitalized. However, in real life, all signals are analog signals, so that in order to facilitate the processing of the digital circuit, an analog-to-digital converter is required to quantize and sample the external analog signals to form digital signals which can be processed by the digital circuit. The charge redistribution type successive approximation analog-to-digital converter (SAR ADC) has a simpler circuit, is suitable for deep submicron technology, and along with the progress of technology nodes, the power consumption and the area of the SAR ADC are continuously reduced, and the precision is gradually increased due to the progress of technology matching. In a system, an ADC of SAR architecture is typically used, provided that the conversion rate is satisfactory. However, in the analog-to-digital conversion circuit of the existing asynchronous clock architecture, the rate of the semiconductor process corner has a larger variance, the conversion rate of the fastest process corner is more than one time faster than the conversion rate of the slowest process corner, so that when the conversion is performed according to the slowest process corner, the conversion half period just meets the conversion time requirement of the slow process corner, and for the fast process corner, the conversion time is far less than the half period time, but the conversion time still can continue to work for the rest time except the conversion time to generate power consumption. In addition, there are often different communication bandwidth requirements in a communication system, which is required to meet the communication application requirements of multiple bandwidths simultaneously. At this time, the analog-to-digital converter is often designed according to the highest bandwidth communication application requirements, but in order to reduce power consumption, it is often necessary to reduce the sampling rate in lower communication bandwidth applications in order to reduce the bandwidth. For asynchronous SAR, the internal clock is automatically generated by delay chain, even if the sampling rate is reduced, the clock can still be continuously generated after the conversion is completed, and the internal partial circuit is controlled to turn over, and the internal partial static circuit still continuously works after the conversion is completed, so that the asynchronous successive approximation type analog-to-digital conversion circuit has the problem of higher power consumption under the conditions of quick process angle and variable sampling rate.
Based on the above, the embodiment of the application provides a low-power-consumption analog-to-digital conversion circuit, so as to reduce the power consumption of the asynchronous successive approximation analog-to-digital conversion circuit under the conditions of a rapid process angle and a variable sampling rate.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a low-power analog-to-digital conversion circuit according to an embodiment of the application. As shown in fig. 1, the low-power analog-to-digital conversion circuit provided by the embodiment of the application includes a sampling array 100, a pre-amplifier 200, a dynamic comparator 300, an asynchronous clock generation circuit 400 and a successive approximation logic circuit 500;
the input end of the sampling array 100 is connected with the output end of an external circuit, receives an analog signal in the current sampling period from the external circuit, and samples the analog signal to obtain a differential signal;
the input end of the pre-amplifier 200 is connected with the output end of the sampling array 100, the pre-amplifier 200 receives the differential signal and amplifies the differential signal to obtain a differential amplified signal;
the input end of the dynamic comparator 300 is connected with the output end of the pre-amplifier 200, the dynamic comparator 300 receives the differential amplified signals, compares the voltages of two amplified signals in the differential amplified signals, and outputs a comparison signal according to the comparison result;
The input end of the successive approximation logic circuit 500 is connected with the output end of the dynamic comparator 300 and the output end of the asynchronous clock generation circuit 400, the successive approximation logic circuit 500 latches the comparison signal according to the asynchronous clock signal generated by the asynchronous clock generation circuit to obtain a digital signal, and the first output end of the successive approximation logic circuit 500 outputs the digital signal;
after completing analog-to-digital conversion in the current sampling period, the successive approximation logic circuit 500 generates a high-level sleep signal, and the second output end of the successive approximation logic circuit 500 outputs the high-level sleep signal;
the input end of the asynchronous clock generation circuit 400 and the gating end of the pre-amplifier 200 are respectively connected with the second output end of the successive approximation logic circuit 500, the asynchronous clock generation circuit 400 and the pre-amplifier 200 enter a sleep state after receiving a high-level sleep signal, and the asynchronous clock generation circuit 400 also generates a sleep control signal according to the high-level sleep signal;
the enabling end of the dynamic comparator 300 is also connected to the output end of the asynchronous clock generation circuit 400, and the dynamic comparator 300 enters a sleep state after receiving the sleep control signal.
In the embodiment of the application, the whole analog-to-digital conversion circuit is connected with an external circuit, receives an input signal from the external circuit, and can be a control analog signal or a communication analog signal, carries out differential processing on the input signal by the external circuit to obtain a plurality of paths of differential signals, and then inputs the differential signals to the analog-to-digital conversion circuit through a voltage positive input end Vip, a reference voltage end Vref and a voltage negative input end Vin, and converts the analog signals into digital signals through the analog-to-digital conversion circuit. For example: each sampling period can generate a 10-bit digital signal and a high-level dormant signal, and the pre-amplifying circuit, the dynamic comparator and the asynchronous clock generating circuit enter dormancy according to the high-level dormant signal so as to reduce power consumption. The pre-amplifier is used for amplifying the differential signal, and a specific structure of the pre-amplifier can be selected by a person skilled in the art according to practical situations, and the application is not limited herein.
The sampling array is described in detail below with reference to fig. 2.
Fig. 2 shows a circuit diagram of a sampling array provided by an embodiment of the present application.
As shown in fig. 2, the sampling array 100 includes a first sampling capacitor array 110, a second sampling capacitor array 120, a first upper plate switch array 130, and a second upper plate switch array 140, the first sampling capacitor array 110 includes a plurality of first sampling capacitors C1, the second sampling capacitor array 120 includes a plurality of second sampling capacitors C2, the first upper plate switch array 130 includes a plurality of first upper plate switches K1, and the second upper plate switch array 140 includes a plurality of second upper plate switches K2; the plurality of first upper plate switches K1 are configured to select a first target voltage terminal from a plurality of first voltage terminals according to a first switch control signal output by the successive approximation logic circuit 500, and connect the first target voltage terminal with an upper plate of the plurality of first sampling capacitors C1, where the plurality of first voltage terminals are a voltage positive input terminal Vip, a reference voltage terminal Vref, and a ground terminal GND; the lower polar plates of the first sampling capacitors C1 are used as first output ends Outp of the sampling array 100 and are connected with the first input end of the pre-amplifier 200; the plurality of second upper pole plate switches K2 are configured to select a second target voltage terminal from a plurality of second voltage terminals according to a second switch control signal output by the successive approximation logic circuit 500, and connect the second target voltage terminal with an upper pole plate of the plurality of second sampling capacitors C2, where the plurality of second voltage terminals are a voltage negative input terminal Vin, a reference voltage terminal Vref, and a ground terminal GND; the lower polar plates of the second sampling capacitors C2 are used as second output ends Outn of the sampling array 100 and are connected with second input ends of the pre-amplifier 200; the first sampling capacitor array 110 and the second sampling capacitor array 120 are used for generating successive approximation voltages based on the switch control signals output by the successive approximation logic circuit 500.
The first switch control signal is input to the sampling array 100 through an in1 input end of the sampling array 100 to control a plurality of first upper pole plate switches K1; the second switch control signal is input to the sampling array 100 through the in2 input terminal of the sampling array 100 to control the plurality of second upper plate switches K2.
The first upper polar plate switch K2 and the second upper polar plate switch K2 are multiphase switches, and can be connected by selecting one from three voltage ends.
The first sampling capacitor array 110 and the second sampling capacitor array 120 are used for performing charge transfer to generate a voltage of the successive approximation Vip-Vin according to the switch control signal output by the successive approximation logic circuit 500.
The sampling array 100 further includes a first lower plate switch D1 and a second lower plate switch D2; one end of a first lower polar plate switch D1 is connected with a reference voltage end Vref, and the other end of the first lower polar plate switch D1 is connected with a first input end of the preamplifier 200; one end of the second lower plate switch D2 is connected to the reference voltage terminal Vref, and the other end of the second lower plate switch D2 is connected to the second input terminal of the preamplifier 200.
The sampling array 100 further includes a first parasitic capacitor C3 and a second parasitic capacitor C4; one end of the first parasitic capacitor C3 is connected to the first input end of the preamplifier 200, and the other end of the first parasitic capacitor C3 is grounded to GND; one end of the second parasitic capacitance C4 is connected to the second input terminal of the preamplifier 200, and the other end of the second parasitic capacitance C4 is grounded GND.
In the sampling array 100, according to the arrangement sequence of the plurality of first sampling capacitors C1, the capacitance value of the next first sampling capacitor C1 is half of the capacitance value of the previous first sampling capacitor C1; in the arrangement order of the plurality of second sampling capacitors C2, the capacitance value of the latter second sampling capacitor C2 is half of the capacitance value of the former second sampling capacitor C2.
The number of the first sampling capacitors C1 is equal to that of the second sampling capacitors C2, N-1 are adopted, and N is the bit number of the digital signal obtained through conversion in one sampling period.
Specifically, assuming that after an analog signal is converted into a digital signal in each sampling period, a digital signal with 10 bits is obtained, the number of the first sampling capacitors C1 and the second sampling capacitors C2 is 9.
The remaining modules except for the sampling array are described below with reference to fig. 3.
Fig. 3 shows a circuit diagram of an analog-to-digital conversion circuit provided by an embodiment of the present application, except for a sampling array.
As shown in fig. 3, the pre-amplifier 200 includes a positive input terminal Vp, a negative input terminal Vn, a positive output terminal, a negative output terminal, and a strobe port se, and the pre-amplifier 200 is configured to amplify differential signals of the positive input terminal and the negative input terminal to obtain amplified differential signals, and the positive output terminal and the negative output terminal output the amplified differential signals. The positive input end of the pre-amplifier 200 is the first input end, the negative input end of the pre-amplifier 200 is the second input end, the positive output end of the pre-amplifier 200 is the first output end, the negative output end of the pre-amplifier 200 is the second output end, and the gating port is the third input end. The power supply is arranged in the pre-amplifier 200, and after the pre-amplifier 200 receives the high-level dormancy signal sent by the successive approximation logic circuit through the gating port, the high-level dormancy signal is used as a gating signal, and the gating signal controls the pre-amplifier to be disconnected with the power supply so as to enable the pre-amplifier 200 to enter dormancy, and power consumption is reduced.
The dynamic comparator 300 includes a positive input end, a negative input end, a positive output end, a negative output end and an enable end, wherein the positive input end of the dynamic comparator 300 is a first input end, the negative input end of the dynamic comparator 300 is a second input end, the positive output end of the dynamic comparator 300 is a first output end, and the negative input end of the dynamic comparator 300 is a second output end. The positive input of the dynamic comparator 300 is connected to the positive output of the pre-amplifier 200, and the negative input of the dynamic comparator 300 is connected to the negative output of the pre-amplifier 200. The positive output of the dynamic comparator 300 is connected to the first input of the asynchronous clock generation circuit 400 and the first input of the successive approximation logic circuit 500, and the negative output of the dynamic comparator 300 is connected to the second input of the asynchronous clock generation circuit 400 and the second input of the successive approximation logic circuit 500.
The dynamic comparator 300 is configured to start comparing the voltage of the amplified signal at the first input terminal with the voltage of the amplified signal at the second input terminal at the rising edge time of the strobe signal; if the voltage of the amplified signal of the first input end is larger than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a high-level comparison signal, and the second output end outputs a low-level comparison signal; if the voltage of the amplified signal of the first input end is smaller than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a low-level comparison signal, and the second output end outputs a high-level comparison signal; at the moment of the falling edge of the gating signal, the voltages of the first output end and the second output end of the dynamic comparator are both pulled up, the connection between the dynamic comparator and the internal power supply is disconnected, and the dynamic comparator does not consume power consumption.
Specifically, the gate terminal of the dynamic comparator 300 receives the gate signal from the output terminal of the asynchronous clock generating circuit 400, and at the rising edge time of the gate signal, the voltage of the differential amplification signal output by the pre-amplifier 200 starts to be compared, if the voltage of the amplification signal at the positive input terminal of the dynamic comparator 300 is greater than the voltage of the signal at the negative input terminal, the positive output terminal of the dynamic comparator 300 outputs a high-level comparison signal, and the negative output terminal outputs a low-level comparison signal, otherwise, if the voltage of the amplification signal at the positive input terminal of the dynamic comparator 300 is less than the voltage of the signal at the negative input terminal, the positive output terminal of the dynamic comparator 300 outputs a low-level comparison signal, and the negative output terminal outputs a high-level comparison signal. At the time of the falling edge of the strobe signal, the voltages at the positive output terminal and the negative output terminal of the dynamic comparator 300 are both pulled high, and the connection between the dynamic comparator 300 and the internal power supply is disconnected. The positive output end of the dynamic comparator outputs 1 or 0, and correspondingly, the negative output end of the dynamic comparator outputs 0 or 1, namely, the comparison result of the dynamic comparator is the conversion from the analog signal to the digital signal.
Asynchronous clock generation circuit 400 includes an exclusive or gate 410, a first delay circuit 420, and a nor gate 430; the first input terminal and the second input terminal of the exclusive-or gate 410 are respectively used as the first input terminal and the second input terminal of the asynchronous clock generation circuit 400, and are connected with the first output terminal and the second output terminal of the dynamic comparator 300; the output of exclusive-or gate 410 is connected to the input of first delay circuit 420, and the output of first delay circuit 420 is connected to the first input of nor gate 430; a second input terminal of the nor gate 430 is connected to a second output terminal of the successive approximation logic circuit 500, and receives the sleep signal; an output terminal of the nor gate 430 is connected as an output terminal of the asynchronous clock generation circuit 400 to an enable terminal of the dynamic comparator 300 and a third input terminal of the successive approximation logic circuit 500.
Specifically, the xor gate 410 in the asynchronous clock generating circuit 400 generates a high-level signal according to the high-low level generated by the positive and negative output terminals after the dynamic comparator 300 finishes comparison, the high-level signal is delayed by the first delay circuit 420 to generate an asynchronous clock, the asynchronous clock and the sleep signal are inverted by the nor gate 430 to generate an enable signal, and the enable signal is fed back to the enable terminal of the dynamic comparator 300 to clear the dynamic comparator. The zero clearing of the dynamic comparator enables the positive and negative output terminal levels of the dynamic comparator 300 to be pulled up, and prevents the last comparison result from affecting the next comparison result. After the exclusive-or gate 410, a low-level signal is generated, the low-level signal is delayed by the first delay circuit 420 and inverted by the nor gate 430 and then fed back to the enable end of the dynamic comparator 300, at this time, the enable end of the dynamic comparator 300 is at a high level, and the dynamic comparator 300 completes 1-bit conversion, i.e. completes one-time comparison to obtain a comparison result, and the comparison result has already converted an analog signal into a digital signal, but needs to wait for the generation of the conversion result of other bits in the whole conversion period and then outputs the conversion result together. After the comparison is completed, the next comparison is started to obtain the bit value corresponding to the next comparison.
The entire asynchronous clock generation circuit 400 continuously completes the generation of one asynchronous clock cycle. The input of nor gate 430 is an asynchronous clock and sleep signal, and when the sleep signal is high, the nor gate output is also high, and the entire asynchronous clock generation circuit stops toggling.
The successive approximation logic circuit 500 includes a plurality of logic units 510 and a second delay circuit 520; the first input terminal ia and the second input terminal ib of each logic unit 510 are respectively used as a first input terminal and a second input terminal of the successive approximation logic circuit 500, are connected with the first output terminal and the second output terminal of the dynamic comparator 300, and the third input terminal ic of each logic unit 510 is used as a third input terminal of the successive approximation logic circuit 500 and is connected with the output terminal of the asynchronous clock generation circuit 400; the first output oa of each logic unit 510 is used as the first output of the successive approximation logic circuit 500 to output the converted digital signal; the logic units 510 are sequentially connected end to end, and the second output end ob of each logic unit 510 is connected with the fourth input end id of the next logic unit 510 to input the latch signal output by the logic unit into the next logic unit; the third output end oc and the fourth output end od of each logic unit 510 are used as the third output end and the fourth output end of the successive approximation logic circuit 500 to respectively output a first switch control signal and a second switch control signal, and the first switch control signal and the second switch control signal are input into the sampling array 100; the second output end ob of the last logic unit is connected with the input end of the second delay circuit 520, the latch signal is input into the second delay circuit 520, and the second delay circuit 520 delays the latch signal to generate a sleep signal; the output of the second delay circuit 520 outputs the sleep signal as a second output of the successive approximation logic circuit 500.
The circuit configuration of the logic unit is described below with reference to fig. 4.
Fig. 4 shows a circuit diagram of a logic unit provided by an embodiment of the present application.
As shown in fig. 4, each logic unit 510 includes a signal generator 511, a signal latch 512, and a buffer circuit 513; the first input ia1 of the signal generator 511 is connected as a fourth input id of the logic unit 510 to the second output ob of the previous logic unit; the second input ib1 of the signal generator 511 is connected as a third input ic of the logic unit 510 to the output of the asynchronous clock generation circuit 400; the output oa1 of the signal generator 511 is connected to the third input ic2 of the signal latch 512, and the output oa1 of the signal generator is also used as the second output ob of the logic unit to output the latch signal; the first input terminal ia2 and the second input terminal ib2 of the signal latch 512 are respectively used as the first input terminal ia and the second input terminal ib of the logic unit 510, and are connected with the first output terminal and the second output terminal of the dynamic comparator 300, the first output terminal oa2 of the signal latch 512 is used as the first output terminal oa of the logic unit 510 to output a digital signal, and the second output terminal ob2 of the signal latch 512 is connected with the input terminal ia3 of the buffer circuit 513; the first output oa3 and the second output ob3 of the buffer circuit 513 respectively serve as the third output oc and the fourth output od of the logic unit 510 to output the first switch control signal and the second switch control signal.
Here, the signal generator may refer to a D flip-flop, the signal latch may refer to a Digital signal latch, the buffer circuit is a Digital-to-Analog Converter (DAC) buffer circuit, and the logic unit is a SAR logic unit.
Specifically, the number of the plurality of logic units in the successive approximation logic circuit is N. Each logic cell includes a signal generator, a signal latch, and a buffer circuit. The first input end of the signal generator of the first logic unit is connected with a high-level power supply, and the first input ends of the signal generators of the other logic units are connected with the second output end of the previous logic unit. The re-terminal of the signal generator of each logic unit is also connected to a sampling clock, which is set independently, for use as a zero-setting signal.
For the first logic unit in the successive approximation logic circuit, the zero signal is an independently set sampling clock. After the dynamic comparator finishes the voltage comparison of the differential amplified signal of the first bit, the asynchronous clock generating circuit generates a high level, the control signal generator generates a high level latch signal, the high level latch signal controls the signal latch to latch the output signal of the dynamic comparator, the input signal of the signal latch is the output signal of the dynamic comparator, the clock of the signal latch is the latch signal of the stage, the first output end of the signal latch outputs a digital signal, namely a converted digital signal, and the second output end of the signal latch also inputs the digital signal to the buffer circuit. The buffer circuit carries out digital-to-analog conversion and inversion processing on the digital signal, and then the third output end and the fourth output end of the buffer circuit respectively output a first switch control signal and a second control signal, and the first switch control signal and the second control signal are output to a sampling array corresponding to the first bit.
For the second logic unit in the successive approximation logic circuit, the input signal is the latch signal of the first logic unit, the asynchronous clock is the output of the asynchronous clock generating circuit, and the zero setting signal is the sampling clock. After the comparison of the first bit is completed, the input signal of the second logic unit becomes high level, i.e., the latch signal output from the signal generator in the first logic unit becomes high level. Therefore, after the dynamic comparator finishes the voltage comparison of the differential amplified signal of the second bit, the high-level signal generated by the asynchronous clock triggers the signal generator to output a high-level latch signal, and the latch signal controls the stage signal latch to latch the output of the dynamic comparator, so that the output digital signal is ensured not to change in the current conversion period, which is equivalent to saving the output result of the dynamic comparator, the input signal of the signal latch is the output signal of the dynamic comparator, and the clock is the stage latch signal and is output as the digital signal. After the digital signal is subjected to digital-to-analog conversion and inversion processing by the buffer circuit, a first switch control signal and a second control signal corresponding to the second bit are respectively output by a third output end and a fourth output end of the buffer circuit, and the first switch control signal and the second control signal are output to the sampling array.
The architecture of each subsequent stage of logic unit is consistent with that of the second logic unit, and the working principle is the same as that of the second logic unit, and will not be repeated here.
In this way, the logic units sequentially output high-level latch signals according to the sequence, namely the conversion of the next bit is started after the previous bit is determined, after the last logic unit generates the latch signals, all digital conversion results are generated, and the asynchronous clock generation circuit and the preamplifier in the analog-to-digital converter do not need to continuously work at the moment, so that the latch signals of the last logic unit are delayed and then used as sleep signals, and the sleep signals are fed back to the asynchronous clock generation circuit and the preamplifier, so that the asynchronous clock generation circuit and the preamplifier enter a sleep state, and the purpose of reducing power consumption is achieved.
The third output end of the Mth logic unit in the successive approximation logic circuit is connected with the Mth first upper polar plate switch in the first sampling capacitor array, and the Mth logic unit controls the state of the Mth first upper polar plate switch in the first sampling capacitor array according to the output of the dynamic comparator so as to control the upper polar plate of the Mth first sampling capacitor to be connected with the voltage positive input end Vip, the reference voltage end Vref or the ground end GND.
The fourth output end of the M-th logic unit in the successive approximation logic circuit is connected with the M-th second upper polar plate switch in the second sampling capacitor array, and the M-th logic unit controls the state of the M-th second upper polar plate switch in the second sampling capacitor array according to the output of the dynamic comparator so as to control the upper polar plate of the M-th first sampling capacitor to be connected with the voltage negative input end Vin, the reference voltage end Vref or the grounding end GND, so that the output of the analog-to-digital conversion circuit approximates to the input voltage.
Specifically, the control and decision logic of the logic unit is: in the sampling stage, the upper plates of the first sampling capacitors C1 of the first sampling capacitor array 110 are connected to the voltage positive input terminal Vip, while the first lower plate switch D1 is closed, and the lower plates of the first sampling capacitors C1 are connected to the reference voltage terminal Vref. The upper plates of the plurality of second sampling capacitors C2 of the second sampling capacitor array 120 are connected to the voltage negative input terminal Vin, while the second sampling lower plate switch D2 is closed, and the lower plates of the plurality of second sampling capacitors C2 are connected to the reference voltage terminal Vref. Based on the connection relation, the input signal is sampled. At this time, the charge of the first sampling capacitance array 110 is (Vip-Vref) ×ctot1, ctot1 representing the total capacitance of the first sampling capacitance array 110. The charge of the second sampling capacitance array 120 is (Vin-Vref) times Ctot2, ctot2 representing the total capacitance of the second sampling capacitance array 120.
In the replacement stage, the upper electrode plate of the first sampling capacitor is grounded, the upper electrode plate of the second sampling capacitor is grounded, at this time, the voltage of the first input end of the pre-amplifier is Vref-Vip, the voltage of the second input end of the pre-amplifier is Vref-Vin, so that the difference value between the voltage of the first input end and the voltage of the second input end of the pre-amplifier is Vin-Vip, and then the dynamic comparator performs the first comparison.
The dynamic comparator compares the voltages of two amplified signals in the differential amplified signals for the first time, if the voltage of the first input end is larger than the voltage of the second input end, the highest bit code word output is 0, the upper polar plate of the highest bit sampling capacitor of the second sampling capacitor array corresponding to the second input end (namely the upper polar plate of the first second sampling capacitor) is connected to the reference voltage, the upper polar plates of the other second sampling capacitors are still connected to the ground, and the upper polar plates of all the capacitors of the first sampling capacitor array corresponding to the first input end are grounded. If the voltage of the first input end is smaller than that of the second input end, the highest bit code word is output to be 1, the upper polar plates of the highest bit sampling capacitors of the first sampling capacitor array corresponding to the first input end are connected to the reference voltage, the upper polar plates of the other first end sampling capacitors are still grounded, the upper polar plates of all the second sampling capacitors in the second sampling capacitor array are grounded, and after the input voltage of the preamplifier is stable, the second comparison can be performed, and only a fixed waiting time is required at the moment. If the voltage at the first input is equal to the voltage at the second input, the highest bit codeword output may be either 1 or 0.
And the dynamic comparator compares the voltages of the two amplified signals in the differential amplified signals for the second time, if the second result is that the voltage of the first input end is larger than the voltage of the second input end, the next higher bit code word is output as 0, and the upper polar plate of the next higher bit second sampling capacitor in the second sampling capacitor array corresponding to the second input end is connected to the reference voltage. If the voltage at the first input terminal is less than the voltage at the second input terminal, the next highest bit code word is output as 1, and the upper plate of the next highest bit first sampling capacitor in the first sampling capacitor array at the first input terminal is connected to the reference voltage.
And so on, if the current comparison result is that the voltage of the first input end is larger than the voltage of the second input end, the codeword output of the corresponding bit is 0, and the upper polar plate of the second sampling capacitor of the corresponding bit of the second input end is connected to the reference voltage. If the current result is that the voltage of the first input end is smaller than the voltage of the second input end, the codeword output of the corresponding bit is 1, and the upper polar plate of the first sampling capacitor of the corresponding bit of the first input end is connected to the reference voltage until all the capacitors are judged to be finished. When all the capacitor decisions are completed, all the converted code words, namely the converted digital signals, are obtained.
Compared with the analog-digital conversion circuit with low power consumption in the prior art, the application can turn the sleep signal into high level at the end of the current sampling period, and the asynchronous clock generation circuit, the dynamic comparator and the preamplifier in the analog-digital conversion circuit are controlled to enter the sleep state by the high level sleep signal so as to reduce the power consumption, namely, the preamplifier is disconnected from an internal power supply, the asynchronous clock generation circuit and the dynamic amplifier stop turning, and the traditional analog-digital conversion circuit can continue turning after the conversion is ended. During sleep, the analog-to-digital converter does not consume current except electric leakage until the next conversion period starts, the external sampling clock input sets all latches to zero, at this time, the sleep signal is converted into low level, the analog-to-digital converter starts the conversion of the next analog signal, the invalid inversion of the asynchronous clock generating circuit and the dynamic comparator and the static power consumption of the preamplifier are reduced, and the problems that the asynchronous successive approximation type analog-to-digital conversion circuit has higher power consumption under the conditions of a rapid process angle and a variable sampling rate are solved.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. The analog-to-digital conversion circuit with low power consumption is characterized by comprising a sampling array, a pre-amplifier, a dynamic comparator, an asynchronous clock generation circuit and a successive approximation logic circuit;
the input end of the sampling array is connected with the output end of an external circuit, the analog signal in the current sampling period is received from the external circuit, and the analog signal is sampled to obtain a differential signal;
the input end of the pre-amplifier is connected with the output end of the sampling array, the pre-amplifier receives the differential signal and amplifies the differential signal to obtain a differential amplified signal;
the input end of the dynamic comparator is connected with the output end of the pre-amplifier, the dynamic comparator receives the differential amplified signals, compares the voltages of two amplified signals in the differential amplified signals, and outputs a comparison signal according to the comparison result;
the input end of the successive approximation logic circuit is connected with the output end of the dynamic comparator and the output end of the asynchronous clock generation circuit, the successive approximation logic circuit latches the comparison signal according to the asynchronous clock signal generated by the asynchronous clock generation circuit to obtain a digital signal, and the first output end of the successive approximation logic circuit outputs the digital signal;
The successive approximation logic circuit generates a high-level sleep signal after completing analog-to-digital conversion in the current sampling period, and a second output end of the successive approximation logic circuit outputs the high-level sleep signal;
the input end of the asynchronous clock generation circuit and the gating end of the pre-amplifier are respectively connected with the second output end of the successive approximation logic circuit, the asynchronous clock generation circuit and the pre-amplifier enter a sleep state after receiving the high-level sleep signal, and the asynchronous clock generation circuit also generates a sleep control signal according to the high-level sleep signal;
and the enabling end of the dynamic comparator is also connected with the output end of the asynchronous clock generation circuit, and the dynamic comparator enters a sleep state after receiving the sleep control signal.
2. The analog-to-digital conversion circuit of claim 1, wherein the asynchronous clock generation circuit comprises an exclusive-or gate, a first delay circuit, and a nor gate;
the first input end and the second input end of the exclusive-OR gate are respectively used as the first input end and the second input end of the asynchronous clock generation circuit and are connected with the first output end and the second output end of the dynamic comparator;
The output end of the exclusive-OR gate is connected with the input end of the first delay circuit, and the output end of the first delay circuit is connected with the first input end of the NOR gate;
the second input end of the NOR gate is connected with the second output end of the successive approximation logic circuit and receives a dormancy signal;
and the output end of the NOR gate is used as the output end of the asynchronous clock generation circuit and is connected with the enabling end of the dynamic comparator and the third input end of the successive approximation logic circuit.
3. The analog-to-digital conversion circuit of claim 1, wherein said successive approximation logic circuit comprises a plurality of logic cells and a second delay circuit;
the first input end and the second input end of each logic unit are used as the first input end and the second input end of the successive approximation logic circuit and are connected with the first output end and the second output end of the dynamic comparator, and the third input end of each logic unit is used as the third input end of the successive approximation logic circuit and is connected with the output end of the asynchronous clock generation circuit;
the first output end of each logic unit is used as the first output end of the successive approximation logic circuit to output a converted digital signal;
The logic units are sequentially connected end to end, the second output end of each logic unit is connected with the fourth input end of the next logic unit, and the latch signal output by the logic unit is input into the next logic unit;
the third output end and the fourth output end of each logic unit are used as the third output end and the fourth output end of the successive approximation logic circuit to respectively output a first switch control signal and a second switch control signal, and the first switch control signal and the second switch control signal are input into the sampling array;
the second output end of the last logic unit is connected with the input end of the second delay circuit, a latch signal is input into the second delay circuit, and the second delay circuit delays the latch signal to generate a dormant signal;
and the output end of the second delay circuit is used as the second output end of the successive approximation logic circuit to output the dormancy signal.
4. An analog to digital conversion circuit according to claim 3, wherein each logic cell comprises a signal generator, a signal latch and a buffer circuit;
the first input end of the signal generator is used as a fourth input end of the logic unit and is connected with the second output end of the previous logic unit;
The second input end of the signal generator is used as a third input end of the logic unit and is connected with the output end of the asynchronous clock generation circuit;
the output end of the signal generator is connected with the third input end of the signal latch, and the output end of the signal generator is also used as the second output end of the logic unit to output a latch signal;
the first input end and the second input end of the signal latch are respectively used as the first input end and the second input end of the logic unit and are connected with the first output end and the second output end of the dynamic comparator, the first output end of the signal latch is used as the first output end of the logic unit to output a digital signal, and the second output end of the signal latch is connected with the input end of the buffer circuit;
the first output end and the second output end of the buffer circuit are respectively used as a third output end and a fourth output end of the logic unit to output a first switch control signal and a second switch control signal.
5. The analog-to-digital conversion circuit of claim 1, wherein the dynamic comparator is configured to start comparing the voltage of the amplified signal at the first input terminal with the voltage of the amplified signal at the second input terminal at a rising edge time of the strobe signal;
If the voltage of the amplified signal of the first input end is larger than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a high-level comparison signal, and the second output end outputs a low-level comparison signal;
if the voltage of the amplified signal of the first input end is smaller than that of the amplified signal of the second input end, the first output end of the dynamic comparator outputs a low-level comparison signal, and the second output end outputs a high-level comparison signal;
at the time of the falling edge of the gating signal, the voltages of the first output end and the second output end of the dynamic comparator are both pulled up, the connection between the dynamic comparator and the internal power supply is disconnected, and the dynamic comparator does not consume power consumption.
6. The analog-to-digital conversion circuit of claim 1, wherein the sampling array comprises a first sampling capacitor array, a second sampling capacitor array, a first upper plate switch array, and a second upper plate switch array, the first sampling capacitor array comprising a plurality of first sampling capacitors, the second sampling capacitor array comprising a plurality of second sampling capacitors, the first upper plate switch array comprising a plurality of first upper plate switches, the second upper plate switch array comprising a plurality of second upper plate switches;
The first upper pole plate switches are used for selecting a first target voltage end from a plurality of first voltage ends according to a first switch control signal output by the successive approximation logic circuit and connecting the first target voltage end with upper pole plates of the first sampling capacitors, and the first voltage ends are voltage positive input ends, reference voltage ends and grounding ends;
the lower polar plates of the first sampling capacitors are used as first output ends of the sampling arrays and are connected with the first input ends of the preamplifiers;
the plurality of second upper pole plate switches are used for selecting a second target voltage end from a plurality of second voltage ends according to a second switch control signal output by the successive approximation logic circuit and connecting the second target voltage end with upper pole plates of the plurality of second sampling capacitors, and the plurality of second voltage ends are voltage negative input ends, reference voltage ends and grounding ends;
the lower polar plates of the second sampling capacitors are used as second output ends of the sampling arrays and are connected with the second input ends of the preamplifiers;
the first sampling capacitor array and the second sampling capacitor array are used for generating successive approximation voltage based on a switch control signal output by the successive approximation logic circuit.
7. The analog-to-digital conversion circuit of claim 1, wherein the sampling array further comprises a first bottom plate switch and a second bottom plate switch;
one end of the first lower polar plate switch is connected with a reference voltage end, and the other end of the first lower polar plate switch is connected with a first input end of the preamplifier;
one end of the second lower polar plate switch is connected with a reference voltage end, and the other end of the second lower polar plate switch is connected with a second input end of the preamplifier.
8. The analog-to-digital conversion circuit of claim 6, wherein in the sampling array, a capacitance value of a next first sampling capacitor is half a capacitance value of a previous first sampling capacitor in an arrangement order of the plurality of first sampling capacitors;
according to the arrangement sequence of the plurality of second sampling capacitors, the capacitance value of the next second sampling capacitor is half of that of the previous second sampling capacitor.
9. The analog-to-digital conversion circuit of claim 6, wherein the number of the first sampling capacitors is equal to the number of the second sampling capacitors, and N is N-1, where N is the number of bits of the digital signal converted in one sampling period.
10. An analog to digital conversion circuit according to claim 3, wherein the number of the plurality of logic cells in the successive approximation logic circuit is N.
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