CN114095027A - Asynchronous successive approximation type analog-to-digital converter device with low voltage and low power consumption - Google Patents

Abstract

The invention discloses a low-voltage low-power-consumption asynchronous successive approximation type analog-to-digital converter device, which comprises an asynchronous successive approximation type analog-to-digital converter and an output buffer circuit, wherein the asynchronous successive approximation type analog-to-digital converter is connected with the output buffer circuit. The invention relates to an analog-digital converter with medium-low speed, medium-high precision and low power consumption. The asynchronous successive approximation type analog-to-digital converter device with low voltage and low power consumption can be widely applied to the field of digital-to-analog hybrid integrated circuit design.

Description

Asynchronous successive approximation type analog-to-digital converter device with low voltage and low power consumption

Technical Field

The invention relates to the field of digital-analog hybrid integrated circuit design, in particular to a low-voltage low-power-consumption asynchronous successive approximation type analog-digital converter device.

Background

In the age of information today, various signals exist in our lives in different forms, and a signal containing specific data may represent any information in the real physical world, such as audio, images, and the like. From a formal point of view, the signal can be divided into: analog signals and digital signals. In nature, most signals are analog signals, and are characterized in that the amplitude of the signals continuously changes along with time; while digital signals are discrete, for example, in electronic products, the signals transmitted and processed are mostly binary numbers, i.e., "0" or "1". It can be seen that the Analog signal and the digital signal are not "seamless", and a medium called Analog-to-digital converter (ADC) is born in order to transfer the Analog signal to the digital signal processing system. Nowadays, science and technology are gradually changing day by day and electronic equipment is widely used, an analog-to-digital converter (ADC) plays a crucial role, and meanwhile, various countries have strong competition in various high and new fields such as biotechnology, medical equipment, aerospace field and the like, and the performance requirements on the ADC are gradually improved. The existing analog-to-digital converter is difficult to achieve low power consumption when higher precision is achieved, and the problems that the speed, the power consumption and the precision cannot be balanced exist.

Disclosure of Invention

In order to solve the above technical problems, an object of the present invention is to provide a low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device, which has an analog-to-digital converter with medium-low speed (1k-10MS/s sampling rate), medium-high precision (8-12bits resolution) and low power consumption.

The technical scheme adopted by the invention is as follows: the low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device comprises an asynchronous successive approximation type analog-to-digital converter and an output buffer circuit, wherein the asynchronous successive approximation type analog-to-digital converter is connected with the output buffer circuit, and the asynchronous successive approximation type analog-to-digital converter device is characterized by comprising a sample and hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator and asynchronous successive approximation type (SAR) logic, wherein the sample and hold circuit is connected with the N-bit capacitor array and is connected with the asynchronous dynamic comparator, and the asynchronous dynamic comparator is connected with the asynchronous SAR logic.

Preferably, the signal part comprises a differential input signal, a sampling clock, an input clock of the parallel-to-serial circuit and a 3-channel parallel-to-serial circuit output signal.

Preferably, the sample-and-hold circuit is a dual voltage sample-and-hold circuit, and the asynchronous successive approximation analog-to-digital converter operates as follows:

the sampling phase begins, the sampling clock is high level, the following sampling is carried out, when the low level arrives, the switch of the sampling hold circuit is disconnected at the moment, and the sampling phase is ended;

starting a conversion stage, transmitting a sampled signal to a capacitor of an N-bit capacitor array (CDAC) for storage, performing first comparison, transmitting a comparison result to asynchronous SAR logic, executing a binary search algorithm to control the on-off of the CDAC, and performing dichotomy operation;

and circulating the sampling phase and the conversion phase to obtain data with N bits.

Preferably, the asynchronous dynamic comparator comprises a comparator of a ring oscillator, a first phase inverter, a second phase inverter, an exclusive or gate, a third phase inverter, a first capacitor, a fourth phase inverter, a second capacitor, a fifth phase inverter and a first NMOS transistor, the comparator of the ring oscillator is respectively connected with the first phase inverter, the second phase inverter and the fifth phase inverter, the first phase inverter and the second phase inverter are respectively connected with the exclusive or gate, the third phase inverter and the fourth phase inverter are sequentially connected, the first capacitor, the third phase inverter and the fourth phase inverter are connected, the second capacitor is connected with the fourth phase inverter, the fifth phase inverter is respectively connected with the comparator of the ring oscillator and the first NMOS transistor, the exclusive or gate and the third phase inverter are connected.

Preferably, the comparator of the ring oscillator is composed of two nand gates and a voltage-controlled delay unit.

Preferably, the xor gate comprises a first PMOS transistor, a second PMOS transistor and a second NMOS transistor, a gate of the first PMOS transistor is connected to a drain of the second PMOS transistor, a gate of the second PMOS transistor is connected to a drain of the first PMOS transistor, and a source of the first PMOS transistor, a source of the second NMOS transistor and a drain of the second NMOS transistor are connected.

Preferably, the N-bit capacitor array employs top plate sampling of the capacitor array.

Preferably, the output buffer circuit adopts a parallel-to-serial circuit, and the working process of the parallel-to-serial circuit is as follows:

parallel data are sampled by a K-path D trigger, and sampling control is performed by a first clock signal;

controlled by a second clock signal through K/2 alternative MUXs;

the second clock signal is a divide-by-two of the first clock signal;

then the signal is controlled by a third clock signal through a K/2-path alternative MUX;

the third clock signal is a quarter frequency of the first clock signal;

and finally, outputting the data through a three-to-one MUX.

The method and the system have the beneficial effects that: the invention maintains the characteristic of self-adaptive adjustment of power consumption by adding the asynchronous dynamic comparator, can improve the conversion rate and the sampling rate to a certain extent, and in addition, the comparator can not only operate under the low-voltage condition but also has simple structure by taking the low-voltage exclusive-OR gate as the comparator, thereby reducing the overall power consumption.

Drawings

Fig. 1 is an overall structural view of a low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device of the present invention;

FIG. 2 is a block diagram of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an asynchronous dynamic comparator according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a comparator of a ring oscillator according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of edge propagation in a voltage controlled delay cell according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating the operation of an asynchronous dynamic comparator according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an XOR gate according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an N-bit capacitor array according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a common mode level generating circuit according to an embodiment of the present invention;

FIG. 10 is a timing diagram illustrating the operation of a parallel-to-serial circuit according to an embodiment of the present invention;

FIG. 11 is a diagram of an implementation of the serial DATA output of the parallel to serial circuit DATA according to an embodiment of the present invention.

Reference numerals: S/H, a sample-and-hold circuit; an N-bit DAC, an N-bit capacitor array; comparator, asynchronous dynamic Comparator; SAR logic, asynchronous SAR logic; vin _ p, Vin _ n, differential input signal; CLKs, sampling clock; CLKc, an input clock of the parallel-to-serial circuit; DATA, CLK _ out, V _ pulse, 3-way parallel-serial circuit output signal; COMP1, comparator of ring oscillator; inv1, a first inverter; inv2, second inverter; XOR, XOR gate; inv3, third inverter; c1, a first capacitance; inv4, fourth inverter; c2, a second capacitance; inv5, fifth inverter; m1, a first NMOS transistor; NAND, NAND gate; a Delay cell, a voltage-controlled Delay unit; m2, a first PMOS tube; m3, a second PMOS tube; m0, a second NMOS tube; vcm generator, common mode level generating circuit; a Data register, a Data register; shift register, Shift register.

Detailed Description

The invention is described in further detail below with reference to the figures and the specific embodiments. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

The invention designs an ADC with medium and low speed (1k-10MS/s sampling rate), medium and high precision (8-12bit resolution) and low power consumption, and provides an asynchronous successive approximation type analog-to-digital converter of a dynamic comparator for binary weight capacitor DAC, Vcm-based capacitor switch switching and self-adaptive power consumption adjustment based on 0.5V power supply voltage.

Referring to fig. 1, the invention provides a low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device, which comprises an asynchronous successive approximation type analog-to-digital converter (asynchronous SAR adc) and an output Buffer circuit (Buffer), wherein the asynchronous successive approximation type analog-to-digital converter is connected with the output Buffer circuit, and the asynchronous successive approximation type analog-to-digital converter device is characterized by comprising a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator and an asynchronous SAR logic, wherein the sample-and-hold circuit is connected with the N-bit capacitor array and is connected with an asynchronous dynamic comparator, and the asynchronous dynamic comparator is connected with the asynchronous SAR logic.

Further as a preferred embodiment of the present device, the device further comprises a signal section, wherein the signal section comprises a differential input signal, a sampling clock, an input clock of the parallel-to-serial circuit, and a 3-way parallel-to-serial circuit output signal.

Specifically, the sampling clock CLKs input is first distributed all the way to two sample-and-hold circuits, converts the continuous-time input differential signal into a discrete-time differential signal, and then passes to a comparator, which compares the sampled input signal with the output voltage generated by the internal CDAC. The other sampling clock CLKs is distributed to the asynchronous SAR logic circuit and is controlled to execute step conversion of each period: triggering the binary search algorithm conversion of each period. The N-bit ADC needs N steps to analyze an input signal, converts the input signal into N bits of DATA D < N:0>, and finally serially outputs the DATA (DATA, CLK _ out and V _ pulse) through a parallel-to-serial circuit.

Further as a preferred embodiment of the method, the sample-and-hold circuit adopts a dual voltage type sample-and-hold circuit, and the asynchronous successive approximation analog-to-digital converter works as follows:

the sampling phase begins, the sampling clock is high level, the following sampling is carried out, when the low level arrives, the switch of the sampling hold circuit is disconnected at the moment, and the sampling phase is ended;

starting a conversion stage, transmitting a sampled signal to a capacitor of an N-bit capacitor array CDAC for storage, carrying out first comparison, transmitting a comparison result to an SAR logic circuit, executing a binary search algorithm to control the switching of the CDAC, and carrying out dichotomy operation;

and circulating the sampling phase and the conversion phase to obtain the data of N bits.

Specifically, the specific structure of the asynchronous successive approximation type analog-to-digital converter refers to fig. 2, wherein, because the power supply voltage is designed to be low voltage, in order to make the sampling MOS transistor conduct better, a double boost type sample-and-hold circuit is adopted, and the operation of the double boost type sample-and-hold circuit comprises two stages, namely a sampling stage and a conversion stage.

Further as a preferred embodiment of the method, the asynchronous dynamic comparator includes a comparator of a ring oscillator, a first inverter, a second inverter, an exclusive or gate, a third inverter, a first capacitor, a fourth inverter, a second capacitor, a fifth inverter and a first NMOS transistor, the comparator of the ring oscillator is respectively connected to the first inverter, the second inverter and the fifth inverter, the first inverter and the second inverter are respectively connected to the exclusive or gate, the third inverter and the fourth inverter are sequentially connected, the first capacitor, the third inverter and the fourth inverter are connected to each other, the second capacitor is connected to the fourth inverter, the fifth inverter is respectively connected to the comparator of the ring oscillator and the first NMOS transistor, the exclusive or gate and the third inverter are connected to each other.

Specifically, the structure diagram of the asynchronous dynamic comparator refers to fig. 3.

As a further preferred embodiment of the present device, the comparator of the ring oscillator is composed of two nand gates and a voltage-controlled delay unit.

Specifically, fig. 4 shows a structure of a comparator COMP1 of a ring oscillator, which is composed of two NAND gates NAND and a voltage-controlled Delay cell Delay. When the signal CLK _ in is at a low level, the comparator is in a quiescent state; when the signal CLK _ in changes from low to high, the triggered comparator starts working, injecting two propagating rising edge edges into the oscillator and moving around the ring comparator until one edge exceeds the other and ends. The differential input signals Vin _ p and Vin _ n alternately control the current limiting transistors at the top and the bottom of the delay unit, and adjust the pull-up and pull-down edge propagation delay. If Vin _ p increases, one edge will propagate faster and the other slower (Vin _ n and vice versa), as shown in fig. 5. When one propagating edge exceeds the other, the output of the comparator will be stable at VDD or GND, and the output result depends on how fast the two edges are. Besides, when a large voltage difference exists at the differential input of the comparator COMP1 of the ring oscillator, the comparator does not oscillate and directly outputs a result, so that a large amount of power consumption is saved; if the differential input voltage difference is small, ring oscillation is formed, and the number of cycles required by decision making is automatically increased along with the reduction of the voltage difference. Therefore, when the differential pressure is large, the comparator can quickly obtain a comparison result, the power consumption is low, and the required decision time and the power consumption are correspondingly increased along with the reduction of the input differential pressure.

In addition, the comparator cannot determine when the comparison is completed, and therefore, the comparator is generally only applied to synchronous analog-to-digital converters. The design is improved according to the characteristic, so that the design can be used in an asynchronous ADC. The design is realized by adding a result judgment circuit at the output of the comparator: an inverter is added to each of Voutp and Voutn, and an exclusive or gate XOR is cascaded, and the circuit is shown in fig. 3. Then, after the output results of Voutp and Voutn are stable, the output of the xor gate changes from 0 to 1, and the first MOS transistor M1 is added to add a reset function, where the gate terminal is at a low level during voltage conversion, and the gate terminal changes from a low level to a high level after voltage conversion, so as to perform reset. At low input pressure differentials, the outputs of Voutp and Voutn will initially rise and fall equally, and gradually pull apart over a distance as several cycles follow. Note that, because the precision of the xor gate is limited, if the voltage difference between the inputs a and b is small, an erroneous determination that the comparison is completed is made in advance when the comparator actually determines the result, but this time is small, and the following delay unit cancels the previous delay time, so that the erroneous determination does not affect the circuit, and the timing chart of the operation is shown in fig. 6.

Further as a preferred embodiment of the present device, the xor gate includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor, a gate of the first PMOS transistor is connected to a drain of the second PMOS transistor, a gate of the second PMOS transistor is connected to a drain of the first PMOS transistor, and a source of the first PMOS transistor, a source of the second NMOS transistor, and a drain of the second NMOS transistor are connected to each other.

In particular, the conventional xor gate is difficult to operate normally under a low power voltage, and the number of stacked transistors is large, which results in large dynamic power consumption. In order to obtain better power consumption, the design adopts a low-voltage design, as shown in fig. 7, the XOR comprises 2 PMOS transistors and 1 NMOS transistor, and finally two inverters are connected as an output buffer stage. When the input a and b are both low level, the two PMOS tubes M2 and M3 are conducted, a weak low level signal can be transmitted because the drain ends of the tubes are in cross connection with a and b, and a small voltage close to 0 can be output at the moment because the NMOS tube M0 is in a diode connection mode and is equivalent to a resistor; when one of the a and the b is high level and the other is low level, one PMOS tube is conducted to transmit high level, one point of the PMOS tube is connected with an NMOS tube connected with a diode, and a resistor is connected in series, so that a small part of voltage is divided, and a voltage close to the high level is output at the moment; when a and b are both high, M2 and M3 turn off but a slight leakage current will flow through the diode-connected NMOS transistor, outputting a voltage close to low. Although the output voltage is not full swing in all cases, the desired effect can still be obtained by waveform recovery through the two-stage inverter. The XOR structure is beneficial to low-voltage design, the total number of pipes is less than that of the traditional structure, and the power consumption is lower.

Further as a preferred embodiment of the apparatus, the N-bit capacitor array employs top plate sampling of the capacitor array.

Specifically, the design provides a circuit structure of a DAC, and referring to fig. 8, a top plate of a capacitor array is used for sampling, and the advantage of sampling by using the top plate is that the layout area of the capacitor array is smaller, a CDAC converted for N times only needs one unit capacitor, and if sampling by using a bottom plate, one unit capacitor is needed. In the sampling phase, due to the symmetry of the sampling capacitor arrays of the respective Vinp and Vimn, the combined voltage of the bottom plate is Vdd/2(═ Vcm) in the sampling phase according to the conservation of charge. In particular, there is a drift in the common mode level in the charge sharing part, and the design uses dynamic diode division to generate the common mode voltage Vcm, as shown in fig. 9. A dynamic control clock VC is adopted for control, when sampling and conversion are finished, the VC is set to be at a low level, and a Vcm generation circuit does not work; during ADC conversion, VC is set high, generating a voltage of Vdd/2.

Further as a preferred embodiment of the present device, the output buffer circuit adopts a parallel-to-serial circuit, and the working process of the parallel-to-serial circuit is as follows:

parallel data are sampled through a K-path D trigger, and sampling control is performed through a first clock signal;

controlled by a second clock signal through K/2 alternative MUXs;

the second clock signal is a divide-by-two of the first clock signal;

then the signal is controlled by a third clock signal through a K/2-path alternative MUX;

the third clock signal is a quarter frequency of the first clock signal;

and finally, outputting the data through a three-to-one MUX.

Specifically, the output buffer circuit is a parallel-to-serial circuit, and the operation timing is shown in fig. 10. The K bit parallel DATA output by the ADC is converted into one-way serial DATA, and then a clock cycle CLK _ out is output corresponding to each bit, in each cycle T, the first half cycle is at a low level, a transition from the low level to a high level is started at T/2, and the second half cycle is kept at a high level. Meanwhile, in order to discriminate the DATA sampled every time, a pulse V _ pulse is added before the DATA output.

In the DATA serial DATA output implementation, as shown in fig. 11, Kbit parallel DATA D < K-1:0> is sampled by a K-way D flip-flop, and sampling control is performed by a clock Clk 1. Then through K/2 two-out MUX, controlled by clock Clk2, then through K/2 two-out MUX, the control clock is two divisions of clock Clk2 (four divisions of clock Clk 1), finally through one three-out MUX, DATA DATA is output.

The beneficial effects of the invention are as follows:

in the whole framework of ADC, in order to make whole consumption reduce, design whole SARADC circuit under low mains voltage condition, every module all adopts the low-voltage design, for example the sample hold circuit is for making the sampling pipe switch on better, and the circuit that adopts two steps up increases sampling pipe grid voltage Vg, the XOR gate adopts a neotype low pressure structure etc. can be better realizing the circuit function, satisfies the requirement of low pressure environment.

The power consumption of the dynamic comparator used in the invention is not changed linearly any more, and self-adaptive adjustment is carried out along with the magnitude of the input pressure difference. When the differential input voltage is larger, the result is directly output, and the power consumption is lower; when the differential input voltage is low, the comparison time is increased. The structure is generally used in an ADC (analog to digital converter) with synchronous time sequence, the design adds a decision circuit, keeps self-adaptive adjustment of power consumption and high precision, improves the sampling rate, and is suitable for a successive approximation type analog-to-digital converter with medium and low speed and medium high precision.

The invention uses a DAC circuit structure which generates Vcm by dynamic diode voltage division. In the DAC switch time sequence, the traditional bottom plate sampling N bit DAC needs 2^NUnit capacitance, if the probability of occurrence of each digital code is the same, the average power consumption is

The design adopts a DAC shared by capacitors, and N bit only needs 2^N-1The unit capacitor reduces half of the layout area and the generated power consumption

Compared with the traditional bottom plate sampling DAC, the power consumption is reduced by 87%. Besides, the common-mode voltage Vcm is obtained by dividing voltage in a MOS tube diode connection mode, a bonding pad does not need to be added externally, extra common-mode voltage does not need to be input, and the area of a chip can be reduced. Meanwhile, the designed Vcm generation circuit is controlled by a dynamic time sequence, has no static power consumption, and reduces the power consumption of the circuit to a certain extent.

The invention uses a circuit for converting output parallel data into serial data. Generally, an N-bit ADC generates N-bit data, N pads are required on a chip, and if the chip is a high-precision chip (more than 12 bits), a large number of pads are required, which results in a great increase in chip area.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. The low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device comprises an asynchronous successive approximation type analog-to-digital converter and an output buffer circuit, wherein the asynchronous successive approximation type analog-to-digital converter is connected with the output buffer circuit, and the asynchronous successive approximation type analog-to-digital converter device is characterized by comprising a sample-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator and asynchronous successive approximation type logic, wherein the sample-hold circuit is connected with the N-bit capacitor array and is connected with the asynchronous dynamic comparator, and the asynchronous dynamic comparator is connected with the asynchronous successive approximation type logic.

2. A low voltage low power consumption asynchronous successive approximation analog-to-digital converter device according to claim 1, characterized by further comprising a signal section, said signal section comprising a differential input signal, a sampling clock, an input clock of a parallel-to-serial circuit and a 3-way parallel-to-serial circuit output signal.

3. The low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device as claimed in claim 2, wherein said sample-and-hold circuit is a dual voltage type sample-and-hold circuit, and the operation process of said asynchronous successive approximation type analog-to-digital converter is as follows:

the sampling phase begins, the sampling clock is high level, the following sampling is carried out, when the low level arrives, the switch of the sampling hold circuit is disconnected at the moment, and the sampling phase is ended;

starting a conversion stage, transmitting a sampled signal to a capacitor of an N-bit capacitor array for storage, performing first comparison, transmitting a comparison result to asynchronous successive approximation logic, executing a binary search algorithm to control a switch of a digital-to-analog conversion capacitor array, and performing dichotomy operation;

and circulating the sampling phase and the conversion phase to obtain the data of N bits.

4. The low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device as claimed in claim 3, wherein said asynchronous dynamic comparator comprises a comparator of a ring oscillator, a first inverter, a second inverter, an exclusive-or gate, a third inverter, a first capacitor, a fourth inverter, a second capacitor, a fifth inverter and a first NMOS transistor, said comparator of said ring oscillator is connected with said first inverter, said second inverter and said fifth inverter respectively, said first inverter and said second inverter are connected with said exclusive-or gate respectively, said exclusive-or gate, said third inverter and said fourth inverter are connected in turn, said first capacitor, said third inverter and said fourth inverter are connected, said second capacitor is connected with said fourth inverter, said fifth inverter is connected with said comparator of said ring oscillator and said first NMOS transistor respectively, said first NMOS transistor, said second NMOS transistor, The exclusive-or gate is connected to the third inverter.

5. The low voltage low power consumption asynchronous successive approximation type analog-to-digital converter device as claimed in claim 4, wherein said ring oscillator comparator is composed of two NAND gates and a voltage-controlled delay unit.

6. The low-voltage low-power asynchronous successive approximation type analog-to-digital converter device as claimed in claim 5, wherein said exclusive-or gate comprises a first PMOS transistor, a second PMOS transistor and a second NMOS transistor, a gate of said first PMOS transistor is connected to a drain of said second PMOS transistor, a gate of said second PMOS transistor is connected to a drain of said first PMOS transistor, and a source of said first PMOS transistor, a source of said second NMOS transistor and a drain of said second NMOS transistor are connected.

7. The low voltage low power consumption asynchronous successive approximation analog-to-digital converter device as claimed in claim 6, wherein said N-bit capacitor array employs top plate sampling of capacitor array.

8. The low-voltage low-power consumption asynchronous successive approximation type analog-to-digital converter device as claimed in claim 7, wherein said output buffer circuit adopts a parallel-to-serial circuit, and the operation process of said parallel-to-serial circuit is as follows:

parallel data are sampled by a K-path D trigger, and sampling control is performed by a first clock signal;

controlled by a second clock signal through K/2 alternative MUXs;

the second clock signal is a divide-by-two of the first clock signal;

then the signal is controlled by a third clock signal through a K/2-path alternative MUX;

the third clock signal is a quarter frequency of the first clock signal;

and finally, outputting the data through a three-to-one MUX.

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