CN111030692A - High-speed analog-to-digital conversion circuit and control method thereof - Google Patents
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Abstract
The invention relates to a high-speed analog-to-digital conversion circuit and a control method thereof, wherein the circuit comprises: the high-precision sampling switch receives the differential input signal and the sampling clock and outputs a sampling voltage; the switch capacitor array receives the sampling voltage and the setting control signal and outputs a setting voltage; the high-speed comparator receives the set voltage and the comparison clock and outputs a comparison signal; the successive approximation time sequence control module receives the comparison signal and outputs a setting control signal and a process angle adjusting signal; the latch decoding module receives the setting control signal, converts the setting control signal into a digital signal and outputs the digital signal; and the dynamic duty ratio clock adjusting module receives the process angle adjusting signal and the input clock, automatically adjusts the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip and outputs the clocks. According to the invention, the duty ratio of the clock is dynamically adjusted by detecting the process angle, so that the duty ratio of the clock is reduced, the high-level sampling time is reduced, the low-level comparison and conversion time is increased, and the optimal time sequence is achieved.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a high-speed analog-to-digital conversion circuit and a control method thereof.
Background
In recent years, the communication rate of a communication system (general communication system) is increasing, and in the communication system, an analog-to-digital converter is used to perform baseband signal processing, convert to an intermediate frequency or a high frequency, and then perform subsequent signal processing or data transmission, so that a high-speed analog-to-digital converter (a/D converter, or ADC for short) is required, and the requirement for the high-speed analog-to-digital converter is increasing.
A successive approximation analog-to-digital converter (SAR ADC) is a high-speed analog-to-digital converter, and generally consists of a sequential pulse generator, a successive approximation register, a digital-to-analog converter, a voltage comparator, and the like. The method has the advantages of medium precision, small size, low power consumption, low cost and the like, and is widely applied to occasions such as consumer electronics and signal acquisition.
Systems on chip that integrate high speed analog to digital converters are generally biased toward using deep sub-micron digital processes (deep sub-micron processes for short) for cost reduction and speed enhancement. Under a deep submicron process, the successive approximation type analog-to-digital converter has obvious advantages in power consumption, speed, integration level and process mobility compared with a pipeline analog-to-digital converter, and is paid more and more attention.
An asynchronous clock successive approximation analog-to-digital converter (also called asynchronous successive approximation analog-to-digital converter, asynchronous SAR ADC) is widely used in high-speed situations because it does not need a high-speed clock several times as high as the throughput rate (the voltage comparator inside the asynchronous SAR ADC is controlled by an asynchronous clock signal, so that each comparison period can be different, and thus a faster speed can be achieved).
Generally, an asynchronous clock successive approximation analog-to-digital converter utilizes one clock cycle, and in the high level of the clock, the sampling circuit completes signal sampling, and in the low level of the clock, the voltage comparator completes signal comparison and digital domain conversion of N-bit. However, due to the variation of the process Corner (PVT Corner, PVT refers to process, voltage, and temperature), the voltage comparator cannot complete the signal comparison and digital domain conversion of N-bit at the slower process Corner (referred to as the slow process Corner, for example, the very slow process Corner ss, the fast and slow process Corner fs, and the slow and fast process Corner sf), which may limit the operating speed of the analog-to-digital converter.
Therefore, under the slow process corner, the problem of insufficient switching time needs to be solved.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a high-speed analog-to-digital conversion circuit and a control method thereof, which realize the purposes of reducing the duty ratio of a clock, reducing the high-level sampling time, increasing the low-level comparison and conversion time and achieving the optimal time sequence by detecting a process angle and dynamically adjusting the duty ratio of the clock.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a high speed analog to digital conversion circuit, comprising:
the high-precision sampling switch is used for receiving the differential input signal, receiving the sampling clock and outputting sampling voltage under the control of the sampling clock;
the switch capacitor array is used for receiving the sampling voltage, receiving the setting control signal and outputting the setting voltage under the control of the setting control signal;
the high-speed comparator is used for receiving the setting voltage, receiving the comparison clock and outputting a comparison signal under the control of the comparison clock;
the successive approximation time sequence control module is used for receiving the comparison signal, outputting a setting control signal and outputting a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
the latch decoding module is used for receiving the setting control signal, converting the setting control signal into a digital signal and outputting the digital signal;
and the dynamic duty ratio clock adjusting module is used for receiving the process angle adjusting signal, receiving the input clock, automatically adjusting the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip, and outputting the sampling clock and the comparison clock.
Further, the successive approximation timing control module includes:
n sets the control logic, N is the conversion digit number of analog to digital converter, specifically divide into:
k-position bit control logic for generating a k-th position bit control signal, k being N, N-1, N-2 … … 1;
the k-position control logic sequentially comprises the following steps from left to right: high position control logic, second high position control logic, … … second low position control logic, low position control logic;
accordingly, from left to right, in turn: a high position control signal, a next high position control signal … … a next low position control signal, a low position control signal;
wherein:
the low position control logic completes setting, outputs a second setting completion indication signal rdy, transmits to the dynamic duty cycle clock adjustment module,
setting of the rest of the setting control logics except the low position control logic is completed, a first setting completion indicating signal crdy is output and transmitted to the dynamic duty ratio clock adjusting module,
the second set completion indication signal rdy and the first set completion indication signal crdy are process corner adjustment signals.
Further, the dynamic duty cycle clock adjustment module includes: a counter, a controllable delay chain, nand control logic, an output buffer, and pass/divide control logic;
a counter for receiving the second set completion indication signal rdy and the first set completion indication signal crdy, and for receiving the fixed frequency reference clock;
the input of the controllable delay chain is respectively connected with the output of the counter and the high-speed sampling clock;
the input of the direct connection/frequency division control logic is connected with a high-speed sampling clock;
and the input of the NAND control logic is respectively connected with the output of the controllable delay chain and the output of the through/frequency division control logic, and the output of the NAND control logic is connected with the output buffer.
A control method for a high-speed analog-to-digital conversion circuit, applied to the high-speed analog-to-digital conversion circuit, comprising:
sending the differential input signal to a high-precision sampling switch, wherein the high-precision sampling switch outputs sampling voltage under the control of a sampling clock;
sending the sampling voltage to a switched capacitor array, wherein the switched capacitor array outputs a set voltage under the control of a set control signal;
sending the set voltage to a high-speed comparator, wherein the high-speed comparator outputs a comparison signal under the control of a comparison clock;
after passing through a successive approximation sequential control module, the comparison signal is finally sent to a latching decoding module and converted into a digital signal to be output;
the successive approximation sequential control module outputs a setting control signal;
the successive approximation sequential control module outputs a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
and the dynamic duty ratio clock adjusting module automatically adjusts the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip to realize time sequence optimization, thereby improving the conversion rate of the converter.
Further, in the dynamic duty cycle clock adjustment module, the rising edge delay Td of the crdy and rdy signals is clocked by the divided clock of the input clock: using a fixed frequency reference clock, and calculating the periodicity of the delay time of the crdy and the rdy through a counter;
when the timing is greater than or equal to a fixed value, indicating that the chip processes the slow process corner;
when the timing is smaller than a fixed value, indicating a chip processing speed process corner;
when a slow process corner is processed, the duty ratio of a sampling clock is reduced, so that the comparison time is more sufficient: the control signal output by the counter can increase the delay time of the delay chain, so that the duty ratio of the output sampling clock is reduced;
when a fast process corner is processed, the duty ratio of a sampling clock is increased, so that the sampling time is increased, and the establishment time and the establishment precision of signals are ensured: the control signal output by the counter can reduce the delay time of the delay chain, and further the duty ratio of the output sampling clock is improved.
Further, the fixed value may be any number from 1 to positive infinity, and the value is related to the period of the fixed-frequency reference clock according to the selected delay time of the crdy and rdy.
Further, the implementation of the timing optimization means that the comparison time is increased as much as possible when the sampling time is satisfied.
Further, in the case that the sampling time is satisfied, the determination is made by: after sampling is complete, the signal can be built to the required accuracy.
The invention has the beneficial effects that: by detecting the process angle and dynamically adjusting the duty ratio of the clock, the duty ratio of the clock is reduced, the high-level sampling time is reduced, the low-level comparison and conversion time is increased, and the optimal time sequence is achieved.
The successive approximation analog-digital converter adopting the high-speed analog-digital conversion circuit can work at higher frequency under the full process angles (tt, ss, ff, sf and fs), and the conversion speed of the analog-digital converter is improved.
Drawings
FIG. 1 is a schematic diagram of a high speed analog to digital conversion circuit according to the present invention.
FIG. 2 is a schematic diagram of a successive approximation timing control module.
FIG. 3 is a schematic diagram of a dynamic duty cycle clock adjustment module.
Fig. 4 shows a delay diagram of signals.
FIG. 5 is a schematic diagram of a duty cycle adjustment sequence.
FIG. 6 is a schematic diagram illustrating the effect of the embodiment.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1, the high-speed analog-to-digital conversion circuit according to the present invention includes:
the high-precision sampling switch is used for receiving the differential input signal, receiving the sampling clock and outputting sampling voltage under the control of the sampling clock;
the switch capacitor array is used for receiving the sampling voltage, receiving the setting control signal and outputting the setting voltage under the control of the setting control signal;
the high-speed comparator is used for receiving the setting voltage, receiving the comparison clock and outputting a comparison signal under the control of the comparison clock;
the successive approximation time sequence control module is used for receiving the comparison signal, outputting a setting control signal and outputting a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
the latch decoding module is used for receiving the setting control signal, converting the setting control signal into a digital signal and outputting the digital signal;
and the dynamic duty ratio clock adjusting module is used for receiving the process angle adjusting signal, receiving the input clock, automatically adjusting the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip, and outputting the sampling clock and the comparison clock.
The high-precision sampling switch, the switched capacitor array, the high-speed comparator and the latch decoding module can be implemented by adopting the prior art and are not detailed.
On the basis of the above technical solution, as shown in fig. 2, the successive approximation timing control module includes:
n sets the control logic, N is the conversion digit number of analog to digital converter, specifically divide into:
k-position bit control logic for generating a k-th position bit control signal, k being N, N-1, N-2 … … 1;
the k-position control logic sequentially comprises the following steps from left to right: high position control logic, second high position control logic, … … second low position control logic, low position control logic;
accordingly, from left to right, in turn: a high position control signal, a next high position control signal … … a next low position control signal, a low position control signal;
wherein:
the low position control logic finishes setting, outputs a second setting finish indication signal rdy (ready), transmits the second setting finish indication signal rdy to the dynamic duty ratio clock adjusting module,
setting of the rest of the setting control logics except the low position control logic is completed, a first setting completion indicating signal crdy is output and transmitted to the dynamic duty ratio clock adjusting module,
the second set completion indication signal rdy and the first set completion indication signal crdy are process corner adjustment signals.
On the basis of the above technical solution, as shown in fig. 3, the dynamic duty cycle clock adjusting module includes: a counter, a controllable delay chain, nand control logic, an output buffer, and pass/divide control logic;
a counter for receiving the second set completion indication signal rdy and the first set completion indication signal crdy, and for receiving the fixed frequency reference clock; the fixed frequency reference clock is a high-speed sampling clock, or is the frequency division of an input high-speed sampling clock, or is an independent reference clock independently provided for the system;
the input of the controllable delay chain is respectively connected with the output of the counter and the high-speed sampling clock;
the input of the direct connection/frequency division control logic is connected with a high-speed sampling clock;
and the input of the NAND control logic is respectively connected with the output of the controllable delay chain and the output of the through/frequency division control logic, and the output of the NAND control logic is connected with the output buffer.
If the input sampling clock is a clock signal with the same frequency as the output sampling clock, the input high-speed sampling clock is directly communicated and then output to one end of the non-control logic, and in some application occasions, the input sampling clock with the frequency 2 times that of the output sampling clock can be provided to obtain a better duty ratio, and then the input high-speed sampling clock is output to one end of the non-control logic after frequency division;
the counter reads the second setting completion indication signal rdy and the first setting completion indication signal crdy from the successive approximation timing control module, the counter takes a fixed frequency reference clock as a reference, the counter decodes the reference and outputs a control signal to the delay chain, the clock output by the delay chain is sent to the other end of the NAND control logic,
the two input clocks output clock signals with the adjusted duty ratio under the conversion of the NAND control logic, and then the clock signals are output as sampling clocks through the output buffer.
Based on the high-speed analog-to-digital conversion circuit, the invention further provides a control method of the high-speed analog-to-digital conversion circuit, which comprises the following steps:
sending the differential input signal to a high-precision sampling switch, wherein the high-precision sampling switch outputs sampling voltage under the control of a sampling clock;
sending the sampling voltage to a switched capacitor array, wherein the switched capacitor array outputs a set voltage under the control of a set control signal;
sending the set voltage to a high-speed comparator, wherein the high-speed comparator outputs a comparison signal under the control of a comparison clock;
after passing through a successive approximation sequential control module, the comparison signal is finally sent to a latching decoding module and converted into a digital signal to be output;
the successive approximation sequential control module outputs a setting control signal;
the successive approximation sequential control module outputs a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
and the dynamic duty ratio clock adjusting module automatically adjusts the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip to realize time sequence optimization, thereby improving the conversion rate of the converter.
Based on the above technical solution, as shown in fig. 4, in the dynamic duty cycle clock adjustment module, the rising edge delay Td of the crdy and rdy signals is clocked by the frequency-divided clock of the input clock: using a fixed frequency reference clock, and calculating the periodicity of the delay time of the crdy and the rdy through a counter;
when the timing is greater than or equal to a fixed value, indicating that the chip processes the slow process corner;
when the timing is smaller than a fixed value, indicating a chip processing speed process corner;
the fixed numerical value can be any number from 1 to positive infinity, and the value is related to the period of the fixed-frequency reference clock according to the selected delay time of the crdy and rdy;
when a slow process corner is processed, the duty ratio of a sampling clock is reduced, so that the comparison time is more sufficient: the control signal output by the counter can increase the delay time of the delay chain, so that the duty ratio of the output sampling clock is reduced;
when a fast process corner is processed, the duty ratio of a sampling clock is increased, so that the sampling time is increased, and the establishment time and the establishment precision of signals are ensured: the control signal output by the counter can reduce the delay time of the delay chain, and further the duty ratio of the output sampling clock is improved.
Through the steps, the completeness of the comparison time can be ensured, and the data conversion can be normally completed.
On the basis of the technical scheme, the sum of the effective time of the sampling clock and the effective time of the comparison clock is the conversion period of N-bit,
the sampling of the signal is done within the sampling time,
the conversion process of N-bit is completed in the comparison time, therefore, the conversion time of multi-bit limits the conversion frequency of the analog-digital converter,
judging whether the process angle condition of the chip belongs to any one of a very slow process angle ss, a fast and slow process angle fs and a slow and fast process angle sf through a dynamic duty ratio clock adjusting module, if so, then:
under the condition that the sampling time is met, the comparison time is increased as much as possible, and the problems of low speed, large delay and insufficient conversion time of the comparator under a slow process angle are solved by increasing the comparison time.
On the basis of the technical scheme, under the condition that the sampling time is met, the judgment is carried out in the following mode: after sampling is complete, the signal can be built to the required accuracy.
In the conventional time sequence, a sampling clock (sampling time) Tsample and a comparison clock (comparison time) Tcompare equal, so that N comparison periods are compressed to a half of a conversion period Tconversion, wherein N is the comparison period of an analog-to-digital converter, N is equal to the resolution of a comparator for the conventional analog-to-digital converter, and N is greater than the resolution for the analog-to-digital converter with redundancy, and is the number of actual comparison and conversion periods;
fig. 5 shows a schematic diagram of a duty cycle adjustment timing sequence of the present invention, where Tconversion is a conversion period, Tsample is sampling time in the conversion period, Tcompare is comparison time in the conversion period, and Tcompare is composed of N sub-periods. By dynamically adjusting the duty ratio of the sampling clock and the comparison clock, the process angle offset result can be automatically detected, the proportion of Tsample and Tcompare is adjusted, the time sequence optimization is realized, and the speed of the converter is improved.
One embodiment is as follows.
Based on the architecture shown in fig. 1, in the successive approximation type analog-to-digital converter designed based on the SMIC40LL process, when a single-channel 125MHz sampling clock has an input signal frequency of 60.546875MHz, the effective bit number ENOB of the analog-to-digital converter can reach 11.65 bits, and the signal-to-noise ratio SNR can reach 71.87dB (SNDR ≈ SNR), which can achieve the expected effect, as shown in fig. 6.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (8)
1. A high speed analog to digital conversion circuit, comprising:
the high-precision sampling switch is used for receiving the differential input signal, receiving the sampling clock and outputting sampling voltage under the control of the sampling clock;
the switch capacitor array is used for receiving the sampling voltage, receiving the setting control signal and outputting the setting voltage under the control of the setting control signal;
the high-speed comparator is used for receiving the setting voltage, receiving the comparison clock and outputting a comparison signal under the control of the comparison clock;
the successive approximation time sequence control module is used for receiving the comparison signal, outputting a setting control signal and outputting a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
the latch decoding module is used for receiving the setting control signal, converting the setting control signal into a digital signal and outputting the digital signal;
and the dynamic duty ratio clock adjusting module is used for receiving the process angle adjusting signal, receiving the input clock, automatically adjusting the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip, and outputting the sampling clock and the comparison clock.
2. A high speed analog to digital conversion circuit as claimed in claim 1, wherein: the successive approximation timing control module comprises:
n sets the control logic, N is the conversion digit number of analog to digital converter, specifically divide into:
k-position bit control logic for generating a k-th position bit control signal, k being N, N-1, N-2 … … 1;
the k-position control logic sequentially comprises the following steps from left to right: high position control logic, second high position control logic, … … second low position control logic, low position control logic;
accordingly, from left to right, in turn: a high position control signal, a next high position control signal … … a next low position control signal, a low position control signal;
wherein:
the low position control logic completes setting, outputs a second setting completion indication signal rdy, transmits to the dynamic duty cycle clock adjustment module,
setting of the rest of the setting control logics except the low position control logic is completed, a first setting completion indicating signal crdy is output and transmitted to the dynamic duty ratio clock adjusting module,
the second set completion indication signal rdy and the first set completion indication signal crdy are process corner adjustment signals.
3. A high speed analog to digital conversion circuit as claimed in claim 1, wherein: the dynamic duty cycle clock adjustment module includes: a counter, a controllable delay chain, nand control logic, an output buffer, and pass/divide control logic;
a counter for receiving the second set completion indication signal rdy and the first set completion indication signal crdy, and for receiving the fixed frequency reference clock;
the input of the controllable delay chain is respectively connected with the output of the counter and the high-speed sampling clock;
the input of the direct connection/frequency division control logic is connected with a high-speed sampling clock;
and the input of the NAND control logic is respectively connected with the output of the controllable delay chain and the output of the through/frequency division control logic, and the output of the NAND control logic is connected with the output buffer.
4. A control method of a high-speed analog-to-digital conversion circuit applied to the high-speed analog-to-digital conversion circuit according to any one of claims 1 to 3, comprising:
sending the differential input signal to a high-precision sampling switch, wherein the high-precision sampling switch outputs sampling voltage under the control of a sampling clock;
sending the sampling voltage to a switched capacitor array, wherein the switched capacitor array outputs a set voltage under the control of a set control signal;
sending the set voltage to a high-speed comparator, wherein the high-speed comparator outputs a comparison signal under the control of a comparison clock;
after passing through a successive approximation sequential control module, the comparison signal is finally sent to a latching decoding module and converted into a digital signal to be output;
the successive approximation sequential control module outputs a setting control signal;
the successive approximation sequential control module outputs a process angle adjusting signal;
the process angle adjustment signal specifically includes: a second set completion indication signal rdy and a first set completion indication signal crdy;
and the dynamic duty ratio clock adjusting module automatically adjusts the duty ratios of the sampling clock and the comparison clock according to the process angle condition of the chip to realize time sequence optimization, thereby improving the conversion rate of the converter.
5. The control method of a high-speed analog-to-digital conversion circuit according to claim 4, characterized in that:
in the dynamic duty cycle clock adjustment module, the rising edge delay Td of the crdy and rdy signals is clocked by the divided clock of the input clock: using a fixed frequency reference clock, and calculating the periodicity of the delay time of the crdy and the rdy through a counter;
when the timing is greater than or equal to a fixed value, indicating that the chip processes the slow process corner;
when the timing is smaller than a fixed value, indicating a chip processing speed process corner;
when a slow process corner is processed, the duty ratio of a sampling clock is reduced, so that the comparison time is more sufficient: the control signal output by the counter can increase the delay time of the delay chain, so that the duty ratio of the output sampling clock is reduced;
when a fast process corner is processed, the duty ratio of a sampling clock is increased, so that the sampling time is increased, and the establishment time and the establishment precision of signals are ensured: the control signal output by the counter can reduce the delay time of the delay chain, and further the duty ratio of the output sampling clock is improved.
6. The control method of a high-speed analog-to-digital conversion circuit according to claim 5, characterized in that: the fixed value can be any number from 1 to positive infinity, and the value is related to the period of the fixed-frequency reference clock according to the selected delay time of the crdy and rdy.
7. The control method of a high-speed analog-to-digital conversion circuit according to claim 4, characterized in that: the implementation of the time sequence optimization means that the comparison time is increased as much as possible under the condition that the sampling time is satisfied.
8. The control method of a high-speed analog-to-digital conversion circuit according to claim 7, characterized in that: and when the sampling time is satisfied, judging by the following method: after sampling is complete, the signal can be built to the required accuracy.
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