CN220273668U - Circuit for converting parallel signal into serial signal - Google Patents

Abstract

The utility model provides a circuit for converting parallel signals into serial signals, which relates to the technical field of circuits, and comprises: the device comprises M triggers, M AND gate modules and OR gate modules; the trigger comprises a first input end, a second input end and a first output end; the first input end is used for inputting an enabling signal, and the second input end is used for inputting a clock signal; the first output end of any trigger is connected with the first input end of the target trigger; the AND gate module comprises a third input end, a fourth input end and a second output end; the first output end is connected with the third input end, and the fourth input end is used for inputting parallel signals; the OR gate module comprises a fifth input end and a third output end; the second output end is connected with the fifth input end, and the third output end is used for outputting serial signals. The parallel signals are connected with the OR gate according to the bit sum, the corresponding trigger is continuously activated through the enabling signal, the OR gate is utilized to output the serial signals, the critical path delay is reduced, and the output speed of the circuit is improved.

Description

Circuit for converting parallel signal into serial signal

Technical Field

The utility model relates to the technical field of circuits, in particular to a circuit for converting parallel signals into serial signals.

Background

The parallel-serial circuit is an important digital signal transmission path, and most of the parallel-serial circuits based on field programmable gate arrays (Field Programmable Gate Array, FPGA) are realized by adopting a counter method, so that the critical path delay of the mode is long, and the output speed of the whole hardware circuit is low.

Therefore, how to reduce the critical path delay and increase the output speed of the circuit is a problem to be solved.

Disclosure of Invention

The utility model provides a circuit for converting parallel signals into serial signals, which is used for reducing critical path delay and further improving the output speed of the circuit.

The utility model provides a circuit for converting parallel signals into serial signals, which comprises: m triggers, M AND gate modules and OR gate modules, wherein M is an integer greater than or equal to 2;

the trigger comprises a first input end, a second input end and a first output end; the first input end is used for inputting an enabling signal, and the second input end is used for inputting a clock signal; the first output end of any trigger is connected with the first input end of a target trigger, and the target trigger is cascaded with any trigger;

the AND gate module comprises a third input end, a fourth input end and a second output end; the first output end is connected with the third input end, and the fourth input end is used for inputting parallel signals; any trigger corresponds to 1 AND gate module.

Optionally, the flip-flop is a D flip-flop.

Optionally, the second input is connected to a clock generator.

Optionally, M of the flip-flops are arranged in a cascade.

Optionally, the first input end of the first trigger is used for inputting an enable signal, the second input end of the first trigger is used for inputting a clock signal, the first output end of the first trigger is connected with the third input end of the first and gate module, the fourth input end of the first and gate module is used for inputting a parallel signal, the second output end of the first and gate module is connected with the fifth input end of the or gate module, the third output end of the or gate module is used for outputting a serial signal, and the first and gate module corresponds to the first trigger;

the first input end of the second trigger is connected with the first output end of the first trigger, the second input end of the second trigger is used for inputting a clock signal, the first output end of the second trigger is connected with the third input end of the second AND gate module, the fourth input end of the second AND gate module is used for inputting a parallel signal, the second output end of the second AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting a serial signal, and the second AND gate module corresponds to the second trigger;

the first input end of the Mth trigger is connected with the first output end of the Mth trigger, the second input end of the Mth trigger is used for inputting clock signals, the first output end of the Mth trigger is connected with the third input end of the Mth AND gate module, the fourth input end of the Mth AND gate module is used for inputting parallel signals, the second output end of the Mth AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting serial signals, and the Mth AND gate module corresponds to the Mth trigger.

The circuit for converting the parallel signals into the serial signals is characterized in that the parallel signals are connected with an AND gate according to the bit, corresponding triggers are continuously activated along the cascade direction through enabling signals, and finally the OR gate module is connected, so that the OR gate module outputs the serial signals; the circuit for converting parallel signals into serial signals has simple structure and good expandability, and can reduce the critical path delay and further improve the output speed of the circuit.

Drawings

In order to more clearly illustrate the utility model or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a circuit for converting parallel signals into serial signals according to the present utility model;

FIG. 2 is a schematic diagram of a circuit for converting parallel signals into serial signals according to a second embodiment of the present utility model;

FIG. 3 is a third schematic diagram of a circuit for converting parallel signals into serial signals according to the present utility model;

fig. 4 is a schematic waveform diagram of converting parallel signals into serial signals according to the present utility model.

Reference numerals:

100: a circuit for converting parallel signals into serial signals; 101: a first trigger; 1011: a first input of the first flip-flop; 1012: a second input of the first flip-flop; 1013: a first output of the first flip-flop;

102: an mth flip-flop; 1021: a first input of the mth flip-flop; 1022: a second input of the mth flip-flop; 1023: a first output of the mth flip-flop;

103: a first AND gate module; 1031: a third input of the first AND gate module; 1032: a fourth input of the first AND gate module; 1033: a second output of the first AND gate module;

104: an Mth AND gate module; 1041: a third input of the Mth AND gate module; 1042: a fourth input of the Mth AND gate module; 1043: a second output end of the Mth AND gate module;

200: a circuit for converting parallel signals into serial signals; 201: a first trigger; 2011: a first input of the first flip-flop; 2012: a second input of the first flip-flop; 2013: a first output of the first flip-flop;

202: a second trigger; 2021: a first input of the second flip-flop; 2022: a second input of the second flip-flop; 2023: a first output of the second flip-flop;

203: a first AND gate module; 2031: a third input of the first AND gate module; 2032: a fourth input of the first AND gate module; 2033: a second output of the first AND gate module;

204: a second AND gate module; 2041: a third input of the second AND gate module; 2042: a fourth input of the second AND gate module; 2043: a second output of the second AND gate module;

300: a circuit for converting parallel signals into serial signals; 301: a first trigger; 3011: a first input of the first flip-flop; 3012: a second input of the first flip-flop; 3013: a first output of the first flip-flop;

302: a second trigger; 3021: a first input of the second flip-flop; 3022: a second input of the second flip-flop; 3023: a first output of the second flip-flop;

303: a third trigger; 3031: a first input of the third flip-flop; 3032: a second input of the third flip-flop; 3033: a first output of the third flip-flop;

304: a fourth trigger; 3041: a first input of a fourth flip-flop; 3042: a second input of the fourth flip-flop; 3043: a first output of the fourth flip-flop;

305: a fifth trigger; 3051: a first input of a fifth flip-flop; 3052: a second input of the fifth flip-flop; 3053: a first output of the fifth flip-flop;

306: a sixth trigger; 3061: a first input of a sixth flip-flop; 3062: a second input of the sixth flip-flop; 3063: a first output of the sixth flip-flop;

307: a seventh flip-flop; 3071: a first input of a seventh flip-flop; 3072: a second input of the seventh flip-flop; 3073: a first output of the seventh flip-flop;

308: an eighth flip-flop; 3081: a first input of an eighth flip-flop; 3082: a second input of the eighth flip-flop; 3083: a first output of the eighth flip-flop;

309: a first AND gate module; 3091: a third input of the first AND gate module; 3092: a fourth input of the first AND gate module; 3093: a second output of the first AND gate module;

310: a second AND gate module; 3101: a third input of the second AND gate module; 3102: a fourth input of the second AND gate module; 3103: a second output of the second AND gate module;

311: a third AND gate module; 3111: a third input of the third AND gate module; 3112: a fourth input of the third AND gate module; 3113: a second output of the third AND gate module;

312: a fourth AND gate module; 3121: a third input of the fourth AND gate module; 3122: a fourth input of the fourth AND gate module; 3123: a second output of the fourth AND gate module;

313: a fifth AND gate module; 3131: a third input of the fifth AND gate module; 3132: a fourth input of the fifth AND gate module; 3133: a second output of the fifth AND gate module;

314: a sixth AND gate module; 3141: a third input of the sixth AND gate module; 3142: a fourth input of the sixth AND gate module; 3143: a second output of the sixth AND gate module;

315: a seventh AND gate module; 3151: a third input of the seventh AND gate module; 3152: a fourth input of the seventh AND gate module; 3153: a second output of the seventh AND gate module;

316: an eighth AND gate module; 3161: a third input of the eighth AND gate module; 3162: a fourth input of the eighth AND gate module; 3163: a second output of the eighth AND gate module;

317: an OR gate module; 3171: a fifth input of the OR gate module; 3172: and a third output of the OR gate module.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, the technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the utility model. Furthermore, the present utility model may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present utility model provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

The utility model provides a circuit for converting parallel signals into serial signals, which comprises: m triggers, M AND gate modules, OR gate modules, M is the integer more than or equal to 2.

The trigger comprises a first input end, a second input end and a first output end; the first input end is used for inputting an enabling signal, and the second input end is used for inputting a clock signal; the first output end of any trigger is connected with the first input end of a target trigger, and the target trigger is cascaded with any trigger;

the AND gate module comprises a third input end, a fourth input end and a second output end; the first output end is connected with the third input end, and the fourth input end is used for inputting parallel signals; any trigger is correspondingly provided with 1 AND gate module;

the OR gate module comprises a fifth input end and a third output end; the second output end is connected with the fifth input end, and the third output end is used for outputting serial signals.

Fig. 1 is a schematic diagram of a circuit for converting parallel signals into serial signals according to the present utility model. The circuit 100 for converting parallel signals into serial signals in fig. 1 includes: a first flip-flop 101, an mth flip-flop 102, a first and gate module 103, an mth and gate module 104, and an or gate module 105.

The first flip-flop 101 includes a first input 1011, a second input 1012, and a first output 1013; the mth flip-flop 102 includes a first input 1021, a second input 1022, and a first output 1023; the first and gate module 103 includes a third input terminal 1031, a fourth input terminal 1032, and a second output terminal 1033; the mth and gate module 104 includes a third input terminal 1041, a fourth input terminal 1042, and a second output terminal 1043; the or gate module 105 includes a fifth input module 1051 and a third output module 1052.

A first input 1011 of the first flip-flop 101 is for inputting an enable signal, and a second input 1012 of the first flip-flop 101 is for inputting a clock signal; the first output 1013 of the first flip-flop 101 is connected to the first input of a second flip-flop, which is cascaded with the first flip-flop; the second input end of the second trigger is used for inputting a clock signal;

the first output 1013 of the first flip-flop 101 is connected to the third input 1031 of the first and gate module 103, and the fourth input 1032 of the first and gate module 103 is used for inputting the parallel signal d [1]; the second output module 1033 of the first and gate module 103 is connected to the fifth input 1051 of the or gate module 105;

the first output 1023 of the mth flip-flop 102 is connected to the third input 1041 of the mth and gate module 104, and the fourth input 1042 of the mth and gate module 104 is used for inputting the parallel signal dM; the second output module 1043 of the mth and gate module 104 is connected to the fifth input 1051 of the or gate module 105;

the third output 1052 of the or-gate module 105 is used for outputting the serial signal.

In the above-described circuit, the first flip-flop 101, the second flip-flop, & gt, the mth flip-flop 102 may employ D flip-flops, and the M flip-flops are arranged in a cascade form.

The second input 1012 of the first flip-flop 101, the second input of the second flip-flop, &..and the second input 1022 of the mth flip-flop 102 are connected to a clock generator, thereby obtaining a clock signal.

In practical application, enable signal E=1000_0000, parallel signal d [1] -dM is connected with AND gate module; the rising of the clock CLK collects the enabling signal from the D end (i.e. the first input end) to the Q end (i.e. the first output end) of the trigger, then sequentially activates the corresponding AND gates, outputs the corresponding parallel signals to the OR gate module, and finally serially outputs the signals.

Fig. 2 is a second schematic diagram of a parallel signal to serial signal circuit according to the present utility model, in which 2 flip-flops, 2 and gate modules and 1 or gate module are disposed in the parallel signal to serial signal circuit 200 in fig. 2, the circuit includes: a first flip-flop 201, a second flip-flop 202, a first and-gate module 203, a second and-gate module 204, and an or-gate module 205.

The first flip-flop 201 includes a first input 2011, a second input 2012, and a first output 2013; the second flip-flop 202 includes a first input 2021, a second input 2022, and a first output 2023; the first and gate module 203 includes a third input 2031, a fourth input 2032, and a second output 2033; the second and gate module 204 includes a third input terminal 2041, a fourth input terminal 2042, and a second output terminal 2043; the or gate module 205 includes a fifth input module 2051 and a third output module 2052.

A first input 2011 of the first flip-flop 201 is used for inputting an enable signal, and a second input 2012 of the first flip-flop 201 is used for inputting a clock signal; the first output 2011 of the first flip-flop 201 is connected to the first input 2021 of the second flip-flop 202, and the second flip-flop 202 is cascaded with the first flip-flop 201; a second input 2022 of the second flip-flop 202 is used for inputting a clock signal;

the first output terminal 2013 of the first flip-flop 201 is connected to the third input terminal 2031 of the first and gate module 203, and the fourth input terminal 2032 of the first and gate module 203 is used for inputting the parallel signal d [0]; the second output module 2033 of the first and gate module 203 is connected to the fifth input 2051 of the or gate module 205;

the first output 2023 of the second flip-flop 202 is connected to the third input 2041 of the second and gate module 204, and the fourth input 2042 of the second and gate module 204 is used for inputting the parallel signal d [1]; the second output module 2043 of the second AND gate module 204 is connected to the fifth input 2051 of the OR gate module 205; the third output 2052 of the or gate module 205 is for outputting a serial signal.

In the above-described circuit, the first flip-flop 201 and the second flip-flop 202 may employ D flip-flops.

The second input 2012 of the first flip-flop 201 and the second input 2022 of the second flip-flop 202 are connected to a clock generator, thereby obtaining a clock signal.

In practical application, enable signal E=1000_0000, parallel signal d [0] -d [1] is connected with AND gate module; the rising of the clock CLK collects the enabling signal from the D end (i.e. the first input end) to the Q end (i.e. the first output end) of the trigger, then sequentially activates the corresponding AND gates, outputs the corresponding parallel signals to the OR gate module, and finally serially outputs the signals.

Alternatively, in a possible implementation manner of the present utility model, the number of the triggers may be set according to actual needs.

Optionally, the first input end of the first trigger is used for inputting an enable signal, the second input end of the first trigger is used for inputting a clock signal, the first output end of the first trigger is connected with the third input end of the first and gate module, the fourth input end of the first and gate module is used for inputting a parallel signal, the second output end of the first and gate module is connected with the fifth input end of the or gate module, the third output end of the or gate module is used for outputting a serial signal, and the first and gate module corresponds to the first trigger;

the first input end of the second trigger is connected with the first output end of the first trigger, the second input end of the second trigger is used for inputting a clock signal, the first output end of the second trigger is connected with the third input end of the second AND gate module, the fourth input end of the second AND gate module is used for inputting a parallel signal, the second output end of the second AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting a serial signal, and the second AND gate module corresponds to the second trigger;

the first input end of the Mth trigger is connected with the first output end of the Mth trigger, the second input end of the Mth trigger is used for inputting clock signals, the first output end of the Mth trigger is connected with the third input end of the Mth AND gate module, the fourth input end of the Mth AND gate module is used for inputting parallel signals, the second output end of the Mth AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting serial signals, and the Mth AND gate module corresponds to the Mth trigger.

Taking the number of flip-flops as 8 as an example, fig. 3 is a third schematic diagram of a parallel signal to serial signal circuit according to the present utility model, where the parallel signal to serial signal circuit 300 includes 8 flip-flops, which are respectively a first flip-flop 301, a second flip-flop 302, a third flip-flop 303, a fourth flip-flop 304, a fifth flip-flop 305, a sixth flip-flop 306, a seventh flip-flop 307, and an eighth flip-flop 308, and are connected in cascade.

The first input terminal 3011 of the first flip-flop 301 is used for inputting an enable signal, the second input terminal 3012 of the first flip-flop 301 is used for inputting a clock signal, the first output terminal 3013 of the first flip-flop 301 is connected with the third input terminal 3091 of the first and gate module 309, the fourth input terminal 3092 of the first and gate module 309 is used for inputting a parallel signal d [0], the second output terminal 3093 of the first and gate module 309 is connected with the fifth input terminal 3171 of the or gate module 317, the third output terminal 3172 of the or gate module 317 is used for outputting a serial signal, and the first and gate module 309 corresponds to the first flip-flop 301;

the first input end 3021 of the second flip-flop 302 is connected to the first output end 3013 of the first flip-flop 301, the second input end 3022 of the second flip-flop 302 is used for inputting a clock signal, the first output end 3023 of the second flip-flop 302 is connected to the third input end 3101 of the second and gate module 310, the fourth input end 3102 of the second and gate module 310 is used for inputting a parallel signal d [1], the second output end 3103 of the second and gate module 310 is connected to the fifth input end 3171 of the or gate module 317, the third output end 3172 of the or gate module 317 is used for outputting a serial signal, and the second and gate module 310 corresponds to the second flip-flop 302;

the first input terminal 3031 of the third flip-flop 303 is connected to the first output terminal 3023 of the second flip-flop 302, the second input terminal 3032 of the third flip-flop 303 is used for inputting a clock signal, the first output terminal 3033 of the third flip-flop 303 is connected to the third input terminal 3111 of the third and gate module 311, the fourth input terminal 3112 of the third and gate module 311 is used for inputting a parallel signal d2, the second output terminal 3113 of the third and gate module 311 is connected to the fifth input terminal 3171 of the or gate module 317, the third output terminal 3172 of the or gate module 317 is used for outputting a serial signal, and the third and gate module 311 corresponds to the third flip-flop 303;

the first input terminal 3041 of the fourth flip-flop 304 is connected to the first output terminal 3033 of the third flip-flop 303, the second input terminal 3042 of the fourth flip-flop 304 is used for inputting a clock signal, the first output terminal 3043 of the fourth flip-flop 304 is connected to the third input terminal 3121 of the fourth and gate module 312, the fourth input terminal 3122 of the fourth and gate module 312 is used for inputting a parallel signal d [3], the second output terminal 3123 of the fourth and gate module 312 is connected to the fifth input terminal 3171 of the or gate module 317, the third output terminal 3172 of the or gate module 317 is used for outputting a serial signal, and the fourth and gate module 312 corresponds to the fourth flip-flop 304;

the first input 3051 of the fifth flip-flop 305 is connected to the first output 3043 of the fourth flip-flop 304, the second input 3052 of the fifth flip-flop 305 is used for inputting a clock signal, the first output 3053 of the fifth flip-flop 305 is connected to the third input 3131 of the fifth and gate module 313, the fourth input 3132 of the fifth and gate module 313 is used for inputting a parallel signal d [4], the second output 3133 of the fifth and gate module 313 is connected to the fifth input 3171 of the or gate module 317, the third output 3172 of the or gate module 317 is used for outputting a serial signal, and the fifth and gate module 313 corresponds to the fifth flip-flop 305;

the first input 3061 of the sixth flip-flop 306 is connected to the first output 3053 of the fifth flip-flop 305, the second input 3062 of the sixth flip-flop 306 is used for inputting a clock signal, the first output 3063 of the sixth flip-flop 306 is connected to the third input 3141 of the sixth and gate module 314, the fourth input 3142 of the sixth and gate module 314 is used for inputting a parallel signal d [5], the second output 3143 of the sixth and gate module 314 is connected to the fifth input 3171 of the or gate module 317, the third output 3172 of the or gate module 317 is used for outputting a serial signal, and the sixth and gate module 314 corresponds to the sixth flip-flop 306;

the first input terminal 3071 of the seventh flip-flop 307 is connected to the first output terminal 3063 of the sixth flip-flop 306, the second input terminal 3072 of the seventh flip-flop 307 is used for inputting a clock signal, the first output terminal 3073 of the seventh flip-flop 307 is connected to the third input terminal 3151 of the seventh and gate module 315, the fourth input terminal 3152 of the seventh and gate module 315 is used for inputting a parallel signal d [6], the second output terminal 3153 of the seventh and gate module 315 is connected to the fifth input terminal 3171 of the or gate module 317, the third output terminal 3172 of the or gate module 317 is used for outputting a serial signal, and the seventh and gate module 315 corresponds to the seventh flip-flop 307;

the first input terminal 3081 of the eighth flip-flop 305 is connected to the first output terminal 3073 of the seventh flip-flop 307, the second input terminal 3082 of the eighth flip-flop 308 is used for inputting a clock signal, the first output terminal 3083 of the eighth flip-flop 308 is connected to the third input terminal 3161 of the eighth and gate module 316, the fourth input terminal 3162 of the eighth and gate module 316 is used for inputting a parallel signal d [7], the second output terminal 3163 of the eighth and gate module 316 is connected to the fifth input terminal 3171 of the or gate module 317, the third output terminal 3172 of the or gate module 317 is used for outputting a serial signal, and the eighth and gate module 316 corresponds to the eighth flip-flop 308.

In practical application, enable signal E=1000_0000, parallel signal d [0] -d [7] is connected with AND gate module; the rising of the clock CLK collects the enabling signal from the D end (i.e. the first input end) to the Q end (i.e. the first output end) of the trigger, then sequentially activates the corresponding 8 AND gates, outputs the corresponding parallel signals to the OR gate module, and finally serially outputs the signals.

Fig. 4 is a schematic waveform diagram of converting parallel signals into serial signals according to the present utility model. In fig. 4, D1 represents a first flip-flop; d2 represents a second flip-flop; d3 represents a third flip-flop; d4 represents a fourth flip-flop; d5 represents a fifth flip-flop; d6 represents a sixth flip-flop; d7 represents a seventh flip-flop; d8 represents an eighth flip-flop;

CLK represents a clock signal; e represents an enable signal; OUT represents a serial signal output by a third output end of the OR gate module; "1" means a high level, and "0" means a low level.

The circuit for converting the parallel signals into the serial signals is characterized in that the parallel signals are connected with an AND gate according to the bit, corresponding triggers are continuously activated along the cascade direction through enabling signals, and finally the OR gate module is connected, so that the OR gate module outputs the serial signals; the circuit for converting parallel signals into serial signals can reduce critical path delay and improve circuit output speed.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims (5)

1. A circuit for converting parallel signals to serial signals, comprising: m triggers, M AND gate modules and OR gate modules, wherein M is an integer greater than or equal to 2;

the trigger comprises a first input end, a second input end and a first output end; the first input end is used for inputting an enabling signal, and the second input end is used for inputting a clock signal; the first output end of any trigger is connected with the first input end of a target trigger, and the target trigger is cascaded with any trigger;

the AND gate module comprises a third input end, a fourth input end and a second output end; the first output end is connected with the third input end, and the fourth input end is used for inputting parallel signals; any trigger is correspondingly provided with 1 AND gate module;

the OR gate module comprises a fifth input end and a third output end; the second output end is connected with the fifth input end, and the third output end is used for outputting serial signals.

2. The parallel to serial signal circuit of claim 1, wherein the flip-flop is a D flip-flop.

3. The parallel to serial signal circuit of claim 1, wherein the second input is coupled to a clock generator.

4. A parallel to serial signal circuit according to any one of claims 1 to 3 wherein M of said flip-flops are arranged in a cascade.

5. The circuit for converting parallel signals to serial signals according to claim 4, wherein a first input terminal of a first flip-flop is used for inputting an enable signal, a second input terminal of the first flip-flop is used for inputting a clock signal, a first output terminal of the first flip-flop is connected with a third input terminal of a first and gate module, a fourth input terminal of the first and gate module is used for inputting a parallel signal, a second output terminal of the first and gate module is connected with a fifth input terminal of the or gate module, a third output terminal of the or gate module is used for outputting a serial signal, and the first and gate module corresponds to the first flip-flop;

the first input end of the second trigger is connected with the first output end of the first trigger, the second input end of the second trigger is used for inputting a clock signal, the first output end of the second trigger is connected with the third input end of the second AND gate module, the fourth input end of the second AND gate module is used for inputting a parallel signal, the second output end of the second AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting a serial signal, and the second AND gate module corresponds to the second trigger;

the first input end of the Mth trigger is connected with the first output end of the Mth trigger, the second input end of the Mth trigger is used for inputting clock signals, the first output end of the Mth trigger is connected with the third input end of the Mth AND gate module, the fourth input end of the Mth AND gate module is used for inputting parallel signals, the second output end of the Mth AND gate module is connected with the fifth input end of the OR gate module, the third output end of the OR gate module is used for outputting serial signals, and the Mth AND gate module corresponds to the Mth trigger.