CN112217498A - Multi-bit pulse latch circuit - Google Patents
Multi-bit pulse latch circuit Download PDFInfo
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- CN112217498A CN112217498A CN202011020794.XA CN202011020794A CN112217498A CN 112217498 A CN112217498 A CN 112217498A CN 202011020794 A CN202011020794 A CN 202011020794A CN 112217498 A CN112217498 A CN 112217498A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a multi-bit pulse latch circuit, which comprises a pulse generator, a plurality of latches and a scanning test circuit, wherein the output end of the pulse generator is respectively connected with the clock input ends of the latches; the scan test circuit has a data input function and a scan input function, the multi-bit pulse latch circuit starts a test function mode when the scan test circuit performs data input, and the multi-bit pulse latch circuit starts a scan chain function mode when the scan test circuit performs scan input. The invention not only has the scanning and testing functions, but also reduces the complexity of the realization of the pulse latch circuit.
Description
Technical Field
The invention relates to a multi-bit pulse latch circuit, and belongs to the technical field of electronic circuits.
Background
Flip-flops and latches are units with storage functions, which are often used in digital circuit design, and the application scenarios in circuit design are different due to the difference of the mechanisms of the two. The flip-flop unit samples input data at the rising edge or the falling edge of a clock edge, the stored data changes, and the data is kept stable at other times. The latch unit samples input data when the enable signal is high or low, the stored data changes, and the output is kept stable when the enable signal is invalid.
The register unit triggered by the clock edge has the advantages of unified design mode, simple and easily realized time sequence check, high tool support degree and the like, and occupies a leading position in the field of integrated circuit design. In contrast, the level-triggered latch unit, although smaller in area and less in power consumption, has not been widely used due to the disadvantages of non-uniform design flow, complex timing check, and poor tool support. For a flip-flop cell, the data of the previous clock edge needs to arrive at the flip-flop before the setup time, and the data of the current clock edge needs to arrive at the flip-flop after the hold time. As shown in fig. 1, for the latch unit, the data that is enabled to be stored effectively before the setup time needs to reach the latch, and the data that is enabled to be sampled effectively at present needs to reach the latch after the hold time, that is, the data is output after the latch of the previous stage is enabled to be valid, and the data can reach the latch of the next stage after a short time after the enable is completed. If we use a 50% duty cycle clock signal to drive the circuit, the hold time for the latch circuit will be slightly more than half a cycle, which can be very difficult to meet. The pulse latch unit is added with a pulse generating circuit on the basis of the latch circuit, and is used for generating a narrow pulse signal so as to reduce the holding time required to be met.
Pulse latch circuits have certain requirements on the load of the pulse generating circuit to meet the integrity of the clock signal arriving at the latch. The load of the pulse generating circuit comprises two parts, one part is the input capacitance of the latch, the part is the product of the input capacitance of the single latch and the number of the latches, the other part is the capacitance of the trace, and the part is uncertain. On the one hand, the distance influences the capacitance value, and on the other hand, the interference between signals also influences the capacitance value. Because the pulse signal generated by the pulse generating circuit is not adjustable, the load of the pulse generating circuit needs to be calculated for each pulse generating circuit and the latch circuit driven by the pulse generating circuit, and whether the clock meets the requirement is judged according to the load, and the uncertainties cause the complexity of the implementation of the latch circuit.
As shown in fig. 2, since the pulse generator occupies a certain area and also causes a certain power consumption, the larger the number of latches loaded, the lower the average area and power consumption per memory cell as a whole. Although the external pulse generator scheme can increase the number of loads of the pulse generator, the load is large, which causes clock signal distortion, and cannot meet the minimum pulse width, thereby causing data transmission errors. Especially for physical implementation tools, the number of loads and the distance between the loads can affect the pulse signal. On the other hand, in order for the tool to recognize the pulse generator, it is necessary to know the tool and have a rich timing check experience to calculate the pulse width output by the pulse generator and to perform a correct timing check on the latch based on the calculated pulse width. Therefore, the above points increase the complexity of the implementation of the pulse latch circuit.
Disclosure of Invention
In order to solve the above problems, the present invention provides a multi-bit pulse latch circuit, which can reduce the complexity of the implementation of the pulse latch circuit.
The technical scheme adopted for solving the technical problems is as follows:
the embodiment of the invention provides a multi-bit pulse latch circuit, which comprises a pulse generator, a plurality of latches and a scanning test circuit, wherein the output end of the pulse generator is respectively connected with the clock input ends of the latches; the scan test circuit has a data input function and a scan input function, the multi-bit pulse latch circuit starts a test function mode when the scan test circuit performs data input, and the multi-bit pulse latch circuit starts a scan chain function mode when the scan test circuit performs scan input.
As a possible implementation manner of this embodiment, the pulse generator includes a pulse and gate, a phase inverter, and multiple buffers, one path of a clock input signal of the pulse generator is directly connected to one input end of the pulse and gate, the other path of the clock input signal passes through the phase inverter and then the multiple buffers to be connected to the other input end of the pulse and gate, and output ends of the pulse and gate are respectively connected to clock input ends of the multiple latches.
As a possible implementation manner of this embodiment, the scan test circuit includes a data input terminal, a scan input terminal, and a scan enable terminal, where the scan enable terminal is connected to the enable signal output terminal of the corresponding latch, and the output terminal of the latch is connected to the scan input terminal of the scan test circuit corresponding to the latch behind.
As a possible implementation manner of this embodiment, the plurality of latches includes 2 latches, 4 latches, 8 latches, or 16 latches.
As a possible implementation manner of this embodiment, the other input terminal of the and gate inputs an enable signal, and the enable signal is the same as the enable signal of the scan enable terminal.
As a possible implementation manner of this embodiment, when the multi-bit pulse latch circuit starts the test function mode, the clock signal generates a narrow pulse signal through the pulse generator and sends the narrow pulse signal to each latch, the scan test circuit is connected to the enable signal of the latch, and data is input through the data input end of each latch and output through the output end of each latch.
As a possible implementation manner of this embodiment, when the multi-bit pulse latch circuit starts a scan chain function mode, a clock generates a narrow pulse signal through a pulse generator and sends the narrow pulse signal to each latch, data is input through a scan input terminal of a first scan test circuit, an output terminal of the first scan test circuit is connected to a scan input terminal of a second scan test circuit through a corresponding latch, outputs of latches other than the last latch are respectively connected to a scan input terminal of a subsequent scan test circuit, and an output of the last latch and an enable signal are output after performing a logical and operation.
The technical scheme of the embodiment of the invention has the following beneficial effects:
the invention not only has the scanning and testing functions, but also reduces the complexity of the realization of the pulse latch circuit. Under the condition that the load quantity is determined, the problem that an external pulse generator causes pulse signal deformation along with the increase of the load quantity is solved; the multi-bit pulse latch is regarded as a basic unit, so that the defect that signals are easily interfered in the process of layout and wiring of an external pulse generator is avoided, and the advantages of small area and low power consumption of the pulse latch are fully embodied; the pulse latch technology is combined with the multi-bit register technology, and the multi-bit pulse latch is described as the function and the time sequence information similar to those of the multi-bit register, so that the design flow is simplified, and the time sequence analysis is simple.
Description of the drawings:
FIG. 1 is a clock signal schematic of a prior art latch cell;
FIG. 2 is a circuit diagram of a prior art external pulse generator;
FIG. 3 is a block diagram illustrating a multi-bit pulse latch circuit in accordance with an exemplary embodiment;
fig. 4 is a circuit diagram illustrating a pulse generator according to an example embodiment.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
in order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
As shown in fig. 3, taking a 4-bit pulse Latch as an example, the multi-bit pulse Latch circuit provided by the embodiment of the present invention includes a pulse generator PG, 4 latches (Latch1, Latch2, Latch3, Latch4) and a scan test circuit (Smcs1, Smcs2, Smcs3, Smcs4), where output terminals of the pulse generator are respectively connected to clock input terminals G of the latches, an input terminal of each Latch is connected to one scan test circuit, the latches are connected in series through the scan test circuit, and an output terminal of a last Latch in the series connection is connected to an and gate; the scan test circuit has a data input function and a scan input function, the multi-bit pulse latch circuit starts a test function mode when the scan test circuit performs data input, and the multi-bit pulse latch circuit starts a scan chain function mode when the scan test circuit performs scan input. The pulse generator is used for providing a narrow pulse clock signal for the plurality of latches; the latch samples data when the clock signal level is active and holds data when the clock signal level is inactive. The scan test circuit provides additional circuits for connection of scan chains, which can be used for machine testing. The multi-bit pulse latch circuit can contain different numbers of latches according to actual needs.
As a possible implementation manner of this embodiment, the pulse generator includes a pulse and gate, an inverter, and a plurality of buffers, one path of a clock input signal clk of the pulse generator is directly connected to one input end of the pulse and gate, the other path of the clock input signal clk passes through the inverter inv and then the plurality of buffers buf to be connected to the other input end of the pulse and gate, and output ends of the pulse and gate are respectively connected to clock input ends of the plurality of latches. As shown in fig. 4, the clock signal clk is divided into two paths, the first path is directly connected to one end of the and gate, the second path is connected to the other end of the and gate through the inverter inv and the buffers buf, and the clock signal genclk with a certain pulse width is output after passing through the and gate.
As a possible implementation manner of this embodiment, the scan test circuit includes a data input terminal, a scan input terminal, and a scan enable terminal, where the scan enable terminal is connected to the enable signal output terminal of the corresponding latch, and the output terminal of the latch is connected to the scan input terminal of the scan test circuit corresponding to the latch behind. As shown in fig. 3, four scan test circuits Smcs1, Smcs2, Smcs3 and Smcs4 each have a data input D0, D1, D2 and D3, a scan input SI and a scan enable SE, and the output of four latches Latch1, Latch2, Latch3 and Latch4 are Q0, Q1, Q2 and Q3, respectively.
As a possible implementation manner of this embodiment, the plurality of latches includes 2 latches, 4 latches, 8 latches, or 16 latches, and even more latches. The multi-bit pulse latch circuit can be in various forms, and is different from the multi-bit pulse latch circuit which comprises a plurality of latches, and various multi-bit pulse latch circuits can be designed according to the requirements of practical application.
As a possible implementation manner of this embodiment, the other input terminal of the and gate inputs an enable signal, and the enable signal is the same as the enable signal of the scan enable terminal.
As a possible implementation manner of this embodiment, when the multi-bit pulse latch circuit starts the test function mode, the clock signal generates a narrow pulse signal through the pulse generator and sends the narrow pulse signal to each latch, the scan test circuit is connected to the enable signal of the latch, and data is input through the data input end of each latch and output through the output end of each latch. As shown in FIG. 3, the clock signal clk generates a narrow pulse signal through a pulse generator, is connected to the enable signal of the latch, and data is input through D0/D1/D2/D3 and output through Q0/Q1/Q2/Q3.
As a possible implementation manner of this embodiment, when the multi-bit pulse latch circuit starts a scan chain function mode, a clock generates a narrow pulse signal through a pulse generator and sends the narrow pulse signal to each latch, data is input through a scan input terminal of a first scan test circuit, an output terminal of the first scan test circuit is connected to a scan input terminal of a second scan test circuit through a corresponding latch, outputs of latches other than the last latch are respectively connected to a scan input terminal of a subsequent scan test circuit, and an output of the last latch and an enable signal are output after performing a logical and operation. As shown in fig. 3, in the scan chain mode, the clock signal clk generates a narrow pulse signal through the pulse generator, data is input through the scan input terminal SI of the scan test circuit Smcs1, the output terminals Q0/Q1/Q2 of the latches 3, 1, 2, 3 are respectively connected to the scan input terminal SI of the next-stage Smcs2, Smcs3, and Smcs4 scan test circuit, and the output terminal Q3 of the Latch4 is an SO output through the and gate after logical and operation with the SE.
Under the condition that the load quantity is determined, the problem that an external pulse generator causes pulse signal deformation along with the increase of the load quantity is solved; the multi-bit pulse latch is regarded as a basic unit, so that the defect that signals are easily interfered in the process of layout and wiring of an external pulse generator is avoided, and the advantages of small area and low power consumption of the pulse latch are fully embodied; the pulse latch technology is combined with the multi-bit register technology, and the multi-bit pulse latch is described as the function and the time sequence information similar to those of the multi-bit register, so that the design flow is simplified, and the time sequence analysis is simple.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (7)
1. A multi-bit pulse latch circuit is characterized by comprising a pulse generator, a plurality of latches and a scanning test circuit, wherein the output end of the pulse generator is respectively connected with the clock input ends of the latches, the input end of each latch is connected with one scanning test circuit, the latches are connected in series through the scanning test circuit, and the output end of the last latch in series connection is connected with an AND gate; the scan test circuit has a data input function and a scan input function, the multi-bit pulse latch circuit starts a test function mode when the scan test circuit performs data input, and the multi-bit pulse latch circuit starts a scan chain function mode when the scan test circuit performs scan input.
2. A multi-bit pulse latch circuit according to claim 1, wherein said pulse generator comprises a pulse and gate, an inverter and a plurality of buffers, one path of a clock input signal of the pulse generator is directly connected to one input end of the pulse and gate, the other path of the clock input signal passes through the inverter and then the plurality of buffers to be connected to the other input end of the pulse and gate, and output ends of the pulse and gate are respectively connected to clock input ends of the plurality of latches.
3. A multi-bit pulse latch circuit as claimed in claim 1, wherein said scan test circuit comprises a data input, a scan input and a scan enable, said scan enable being connected to the enable signal output of the respective latch, the output of said latch being connected to the scan input of the scan test circuit corresponding to the following latch.
4. A multi-bit pulsed latch circuit as claimed in claim 1, wherein said plurality of latches comprises 2 latches, 4 latches, 8 latches or 16 latches.
5. A multi-bit pulse latch circuit as claimed in claim 1, wherein an enable signal is input to the other input terminal of said and gate, said enable signal being the same as the enable signal at the scan enable terminal.
6. A multi-bit pulse latch circuit according to any one of claims 1 to 5, wherein the clock signal is passed through the pulse generator to generate the narrow pulse signal and sent to each latch when the multi-bit pulse latch circuit is in the test mode, the scan test circuit being coupled to the enable signal for the latch, data being input via the data input of each latch and output via the output of each latch.
7. A multi-bit pulse latch circuit according to any one of claims 1 to 5, wherein when the multi-bit pulse latch circuit is enabled to scan a chain function mode, a clock generates a narrow pulse signal by the pulse generator and sends it to each latch, data is input through the scan input of a first scan test circuit, the output of the first scan test circuit is connected to the scan input of a second scan test circuit through the corresponding latch, the outputs of the latches other than the last are connected to the scan input of the subsequent scan test circuit, respectively, and the output of the last latch and the enable signal are output after logical AND operation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011020794.XA CN112217498B (en) | 2020-09-24 | 2020-09-24 | Multi-bit pulse latch circuit |
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| CN202011020794.XA CN112217498B (en) | 2020-09-24 | 2020-09-24 | Multi-bit pulse latch circuit |
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| CN112217498A true CN112217498A (en) | 2021-01-12 |
| CN112217498B CN112217498B (en) | 2023-04-14 |
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| CN108463734A (en) * | 2015-11-24 | 2018-08-28 | 密克罗奇普技术公司 | For the scanning logic with latch and the circuit design of trigger |
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2020
- 2020-09-24 CN CN202011020794.XA patent/CN112217498B/en active Active
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| CN1702968A (en) * | 2004-05-28 | 2005-11-30 | 三星电子株式会社 | Semiconductor integrated circuit device having scan flip-flop circuit |
| US20080133989A1 (en) * | 2006-12-05 | 2008-06-05 | Sony Computer Entertainment Inc. | Method And Apparatus For Scan Chain Circuit AC Test |
| CN101627314A (en) * | 2007-03-08 | 2010-01-13 | 晶像股份有限公司 | Circuitry to prevent peak power problems during scan shift |
| CN103607199A (en) * | 2013-11-27 | 2014-02-26 | 东南大学 | Quick delay locked loop of full-digital successive approximation register |
| CN104375078A (en) * | 2014-11-06 | 2015-02-25 | 北京时代民芯科技有限公司 | Scan test latch macrocell and scan test method |
| CN106556792A (en) * | 2015-09-28 | 2017-04-05 | 飞思卡尔半导体公司 | The integrated circuit of security sweep can be carried out |
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