KR100294718B1 - Linear Feedback Shift Registers and Semiconductor Integrated Circuit Devices - Google Patents

Abstract

An object of the present invention is to provide a linear feedback shift register and a semiconductor integrated circuit device having the same, including F / F operated by different clocks, and satisfying a condition of pseudo random number generation or linear feedback.

The present invention includes a plurality of pairs of F / Fs 101, 102, and 103 that operate in synchronization with different clocks CLK1, CLK2, and CLK3, and generates a random number or linear feedback between the pairs of F / Fs 101, 102, and 103. An F / F (1) which satisfies the above condition, or an F / F (2) connected in series and a delay circuit 3 are inserted. With this configuration, even if the pairs 101, 102 and 103 of the F / F operate in synchronization with different clocks CLK1, CLK2 and CLK3, the output from the desired pair of F / Fs can be delayed. As a result, signals propagated between pairs 101, 102, and 103 of the F / F satisfy the condition of pseudo random number generation or linear feedback.

Description

Linear Feedback Shift Registers and Semiconductor Integrated Circuits

1 is a configuration diagram of a linear feedback shift register according to Embodiment 1 of the present invention.

2 is a timing chart of a linear feedback shift register according to Embodiment 1 of the present invention.

3 (a) is a configuration diagram for explaining a latch circuit included in the linear feedback shift register according to the second embodiment of the present invention.

FIG. 3 (b) is a circuit diagram of a clocked inverter shown in FIG. 3 (a).

4 is a configuration diagram of a linear feedback shift register according to Embodiment 3 of the present invention.

5 is a configuration diagram of a semiconductor integrated circuit device according to Embodiment 4 of the present invention.

6 is a configuration diagram of one bit of a basic circuit that constitutes a boundary scan circuit included in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

7 is a block diagram of a clock generation circuit provided in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

8 is a timing chart of the clock generation circuit shown in FIG.

9 is a block diagram showing the configuration of the BILBO.

10 (a) is a configuration diagram of a conventional linear feedback shift register, and a configuration diagram of a linear feedback shift register as a test data generation circuit.

10 (b) is a block diagram of a linear feedback shift register as a test result determination circuit.

* Explanation of symbols for main parts of the drawings

1, 2: flip-flop 3: delay circuit

10 to 16 flip-flop 20 to 25 exclusive OR gate

30 to 32 latch circuit 50 LSI

51: logic circuit block 52: input test data generation circuit

53 to 55: boundary scan circuit 56: clock generation circuit

101, 102, 103: pair of flip-flops 200: feedback circuit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear feedback shift register and a semiconductor integrated circuit device having the same. In particular, a large scale integrated circuit (LSI), and more particularly, a large large scale integration (VLSI) and an ultra large scale integration (ULSI), A linear feedback shift register useful for Design For Testability, particularly Built in Self Test, and a semiconductor integrated circuit having the same.

[Conventional Technology and Its Problems]

Rapid advances in semiconductor technology have led to the emergence of VLSIs with larger, more complex, and higher performance LSIs, and the emergence of ULSIs. Thus, the question of how to test these chips has become a very serious problem. In conventional LSI chips, testing with LSI testers using only functions defined by normal operation has been generally performed. However, in VLSI and ULSI, a large amount of test elements need to be prepared, and furthermore, these chips can be tested. LSI testers are increasingly limited to higher performance, and therefore more expensive. Furthermore, an objective determination of how well these test elements are testing the chip has to be performed separately, which requires a huge CPU cost.

For this reason, it is almost impossible to realistically test the chips of VLSI and ULSI by conventional techniques. As a solution to this serious problem, design for testability, which incorporates a test circuit for facilitating the test in advance inside the chip and completely tests it at low cost, has been noticed and spread.

A built-in self test (abbreviated as BIST), a kind of test-enabled design, is placed on a circuit block inside an LSI chip that is a device under test (abbreviated as DUT). The test data generation circuit and the test result judgment circuit are incorporated in the LSI chip to start the test with a signal from the outside, and after the test is completed, a positive judgment result signal or a test result for the judgment is output. In addition, the LSI tester is almost unnecessary, which is extremely effective for reducing test costs. In addition, the chip can be tested under the same conditions as in the real world, and even after it is built into the system. Many of these outstanding advantages are expected to play a very important role for BIST in the testing of VLSI and ULSI.

In such a BIST, the most basic technique is called a signature analysis. This technology is based on the Linear Feedback Shift Register (abbreviated LFSR).

First, the LFSR will be described.

LFSR (where the bit width is n) can be used both as a test data generation circuit and as a test result determination circuit. The LFSR (bit width n = 8) as the test data generating circuit is composed of n D flip-flops (hereinafter abbreviated as F / F) connected in series and a predetermined F / F as shown in FIG. 10 (a). A simple register circuit composed of a feedback circuit for generating an exclusive OR of the output Q of the output Q (hereinafter abbreviated as XOR) and inputting it to the D input of the first F / F of the serial connection. to be.

If all of the F / Fs are set to initial values other than 0 (the circuit for initialization is omitted in this LFSR) and then operated, then 2 ⁿ -1 (maximum number obtained from the LFSR) almost random data (pseudo random numbers) Repeat the output in a certain order. This pseudo-random number can be taken out sequentially using any one of the outputs of n F / Fs (Out _i ; i = 0, ..., 7), and can be taken out in parallel using all these outputs.

In the recent VLSI or ULSI where data processing is performed in a multi-bit width, the latter method is common and important.

And signature analysis is a technique which uses LFSR as a test result determination circuit. Also in this case, there are LFSRs in which the output from the DUT is serially input, and LFSRs in parallel input type called MISR (Multiple Input Signature Register), but the latter is overwhelmingly important in VLSI and ULSI. Therefore, after that, it demonstrates only to this. An example of an n-bit parallel input type LFSR is shown in FIG. 10 (b) (bit width n = 8). Bit i _{+ 1} via an XOR circuit to which the output Qi (= OUTi) of the F / F of bit i (i = 0,…, 6) in the LFSR and external data (IN _{i + 1} ) of bit i + 1 are added Is input to the D input of F / F, and the output FB (= Q0 XOR Q5 XOR Q6 XOR Q7) of the feedback circuit of the LFSR described above is input to the D input of F / F of bit 0 and external data of bit 0. It is input through XOR circuit. If the data created inside the LFSR is Q'i (i = 0, ..., 7) and these are expressed as equations,

Q′0 = INO XOR FB (Equation 1)

Q′i + 1 = INi XOR Qi (i = 0,…, 6) (Equation 2)

Where XOR is a symbol representing the XOR operation. For the above configuration, when the response output from the DUT is sequentially applied to the LFSR in which a certain value is stored, almost random data is formed in the internal F / F according to those values, and finally any unique Test result data is formed in LFSR. The data generated inside the LFSR is called a signature, and the operation of generating a signature by applying a response output from the DUT is called a signature compression or a signature analysis. The signature analysis performs signature validation on the response output from the DUT for a series of test data and finally compares the test result (signature) remaining in the LFSR with the expected value only once. It is an interpretation method.

In general, after the signature compression is performed with sufficient test data, the probability that the signature is correct is the same that the final signature (test result) becomes the same as the normal time even though there is an output different from the normal time. The probability of Alias is subtracted from 1 to 1-2 ^-n . Since the alias probability can generally be ignored when n becomes large (n> 24), the reliability of signature analysis is very high in VLSI and VLSI where multi-bit (n ≧ 32) width data processing is common.

On the other hand, although the above-described LFSRs are provided exclusively for BIST, many of them are dedicated to the use of the registers for normal operation in the sense of saving test circuits.

In the conventional example as described above, the LFSR was regarded as one circuit block, and as a result, only the operation of receiving a single clock from the outside was considered. BIST using LFSR has begun to apply from a regular structure such as ROM, RAM, and PLA. These are the circuit blocks "closed" by registers and F / F, and their output is usually a timing condition that is stored in the output register at the edge of the system clock. BIST uses this output register to LFSR and use it as a signature compression circuit. In addition, the inspection of the AC operation delay failure of the DUT can be realized simultaneously.

More generally, if a DUT having a "closed" structure as a register or F / F that changes at the edge of the system clock, rather than a circuit block having a regular structure as described above, is also possible in a so-called random logic, The BIST that can be inspected including the AC output delay can be effectively realized during the BIST period. Therefore, such a BIST is also used in some cases.

However, in the I / O (Input / Output) section of the general LSI, for example, the delay of the signal at the output terminal of the LSI is such that the predetermined time delay is less than one cycle based on the edge of the system clock. Therefore, when BIST using LFSR operating at the edge of the conventional system clock is applied to the output terminal of the LSI, it is possible to check the logic value at the timing (edge of the system clock) at which data sampling is performed in the LFSR. There was a problem that a delay failure of the AC output from the DUT could not be detected.

That is, there is a big problem that the conventional BIST application to the input / output terminals of the LSI can be realized only in the form of removing the important item of checking the AC output delay.

In the present and future, it is possible that design techniques for achieving high performance by mixing circuit blocks operating in synchronization with a plurality of clocks (including other edges of the same clock) in the VLSI or ULSI will become important. Very high. On the other hand, in the conventional BIST using LFSR, the alias probability must be configured with a sufficient bit width in order to suppress the negligible probability. Therefore, an extra F / F for each group of registers and F / Fs operating at each clock is required. There is a high possibility that LFSR must be formed by adding F, and consequently, the area has to be increased.

Moreover, it may be a situation to avoid this overhead and abandon the application of BIST itself.

[Purpose of invention]

The present invention has been made in view of the above, and includes a linear feedback shift register including a flip-flop operated by different clocks and satisfying a condition of pseudo random number generation or linear feedback, and a semiconductor integrated circuit device having the same. The purpose is to provide.

[Configuration of Invention]

In order to achieve the above object, the linear feedback shift register according to the present invention includes a plurality of pairs of flip-flops that operate in synchronization with different clocks, and the conditions of pseudo random number generation or linear feedback between the pairs of these flip-flops are determined. Characterized in that a means for establishing a satisfactory linear feedback condition is inserted.

[Action]

With the linear feedback shift register of the above arrangement, even if a pair of flip-flops operates in synchronization with different clocks, a establishing means for establishing a condition of pseudo random number generation or a linear feedback between the pairs of flip-flops is established. By inserting, a pair of plural flip-flops can cooperatively operate as one LFSR. Thus, this linear feedback shift register is allowed to operate in synchronization with a different clock for each flip-flop.

Such a linear feedback shift register can be effectively applied to a built-in magnetic test (BIST) or the like in LSI. For example, it is conceivable that the flip-flop group provided in the boundary scan circuit installed in the recent LSI is a set of the flip-flops which are operated in synchronization with a plurality of clocks. Since they operate with different clocks, signature compression is possible at different clock edges as well as the system clock edge of the LSI. As a result, it is possible to detect an AC output delay failure from the circuit under test when the LSI is applied to the input / output terminal portion of the LSI, which could not be achieved in a circuit synchronized with the system clock.

In addition, it is also possible to construct a boundary scan circuit by connecting the boundary scan circuit with each other while inserting a means for establishing a linear feedback condition as described above. In this way, a linear feedback shift register having a sufficient bit width that can ignore the alias probability can be obtained without adding a new flip-flop, thereby improving the area efficiency.

EXAMPLE

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing a parallel input type LFSR according to Embodiment 1 of the present invention. The LFSR shown in FIG. 1 is an n-bit-width parallel input type LFSR operating under a plurality (here, three types) of clocks CLK1, CLK2, and CLK3. This parallel input type LFSR is composed of the first set 101, the F / F (12, 13), which is composed of flip-flops (F / F: 10, 11) and operates in synchronization with the clock (CLK2). A second set 102 which operates in synchronism with CLK3, and a third set 103 which consists of F / Fs 14, ..., 15 and operate in synchronism with clock CLK1 are included. These jaws 101, 102 and 103 are connected in series. At the connection point where the first article 101 and the second article 102 are connected to each other, a delay circuit 3 and an F / F 2 connected in series with each other are inserted and provided. The third article 103 is connected to the first article 101 via the feedback circuit 200. The F / F 1 is inserted and provided at the connection point between the feedback circuit 200 and the first article 101. The feedback signal FB is input to the D terminal of the F / F 1. The Q terminal of the F / F 1 is connected to the first input of the XOR (exclusive logical sum) gate 20, and the second input of the XOR gate 20 is connected to the data signal terminal d0. The output of the XOR gate 20 is connected to the D terminal of the F / F 10. The Q terminal of the F / F 10 is connected to the first input of the XOR gate 21 and to the first input of the XOR gate 30 in the feedback circuit 200. The second input of the XOR gate 21 is connected to the data signal terminal d1. The output of the XOR gate 21 is connected to the D terminal of the F / F 11, and the Q terminal of the F / F 11 is connected to one end of the delay circuit 3. The other end of the delay circuit 3 is connected to the D terminal of the F / F 2, and the Q terminal of the F / F 2 is connected to the first input of the XOR gate 22, and the feedback circuit It is connected to the first input of the XOR gate 31 in the 200. The second input of the XOR gate 22 is connected to the data signal terminal d2. The output of the XOR gate 22 is connected to the D terminal of the F / F 12, and the Q terminal of the F / F 12 is connected to the first input of the XOR gate 23. The second input of the XOR gate 23 is connected to the data signal terminal d3 and its output is connected to the D terminal of the F / F 13. The Q terminal of the F / F 13 is connected to the first input of the XOR gate 24. The second input of the XOR gate 24 is connected to the data signal terminal d4, and its output is connected to the D terminal of the F / F 14. As shown in FIG. The Q terminal of the F / F 14 is connected to the first input of the XOR gate 32 in the feedback circuit 200, and is connected to the first input of the XOR gate (not shown) by the same connection as the other F / F tanks 101 and 102. It is connected to the first input. The output of the XOR gate (not shown) is connected to the D terminal of the F / F (not shown), and the Q terminal thereof is connected to the first input of the XOR gate 25 (this is based on the number of data signal terminals d). Therefore, two or more F / Fs may be present in the F / F tank). The second input of the XOR gate 25 is connected to the data signal terminal d _n-1 , and the output thereof is connected to the D terminal of the F / F 15. The Q terminal of the F / F 15 is connected to the second input of the XOR gate 32 and its output is connected to the second input of the XOR gate 31. The output of the XOR gate 31 is connected to the second input of the XOR gate 30. The output of the XOR gate 30 is connected to the D terminal of the F / F 1. The output of this XOR gate 30 is a feedback signal FB. In the present embodiment, the F / F output for generating the feedback signal FB is selected from the appropriate F / F for the operation described later.

The F / Fs (1, 2, 10 to 15) installed in the LFSR have the rising edges of the three types of clock signals (CLK1, CLK2, CLK3) (hereinafter abbreviated as CLK1 ↑, CLKE2 ↑, and CLK3 ↑, respectively). Latch the input to the terminal. Here, F / F (1,14, ..., 15) is from CLK1 ↑, F / F (10,11,2) is from CLK2 ↑, and F / F (12,13) is from CLK3 ↑ to D terminal. The input is latched (F / F for latching data on the rising edge of the clock signal is illustrated here, but F / F of other structures is not a problem). The timing relationship between these clocks CLK1, CLK2 and CLK3 is shown in FIG.

When the LFSR is operated by multiple clocks, it is easy to obscure which data from the DUT (test circuit) and which data in the LFSR are the signature compression. Otherwise, even if BIST is executed by using it as a signature compression circuit, the operating condition of signature compression is not satisfied, and there is a possibility that the expected high quality BIST cannot be realized.

Here, in general, considering that any synchronous logic circuit is designed to provide an output for a predetermined input defined according to each cycle of the system clock on which it is based, the set of data to be compressed can be clearly defined. . Based on this, in the LFSR shown in FIG. 1, there are data (d0, ..., d _n-1 ) from an unshown DUT which intends to compress the signature, and these data are shown in (1) to (3) below. In order, it is compressed to the corresponding F / F (XOR with other data, and latched will be expressed as being compressed).

(1) Data d4, ..., d _n-1 are compressed to F / F 14, ..., 15 by CLK1 ↑.

(2) Data (d0, d1) is compressed to F / F (10, 11) by CLK2 ↑.

(3) Data d2 and d3 are compressed to F / F 12 and 13 by CLK3 ↑.

Timing charts relating to these operations are shown in FIG.

The data sets d0, ..., d _n-1 correspond to the hatched portions and are compressed to the corresponding F / F at the time indicated by the downward solid line. Here, the part marked with "X" indicates that it is not valid data.

Then, as described in the prior art, signature compression was performed on data d0, ..., d _n-1 and F / F data q0, ..., q _{n-1 in the} LFSR. The data of F / F is q'0,... , q ' _n-1 , the following must be true.

q′0 = d0 XOR FB (Equation 3)

(FB = q0 XOR q1 XOR q4 XOR q _n-1 )

q′i = d _i XOR q _i-1 (i = 1,…, n-1) (Equation 4)

The operation of the above (1) to (3) will be described in detail with attention to the above.

First, in (1), d4, d _n-1 and q4,... , q _n-1 to q'4,... , q ' _n-1 is generated to satisfy (4) and stored in the corresponding F / Fs (14, ..., 15). It should be noted, however, that the feedback signal FB changes to FB '= q0 XOR q1 XOR q'4 XOR q'n-1.

Next, in (2), (4) is established between d1, q0, and q'1, and there is no problem (however, q1 related to latching of data in CLK3 ↑ is changed to q'1). Need to be careful). However, as to the equation (3), since the feedback signal FB has already changed to FB ', the configuration of the conventional LFSR becomes q'0 = d0 XOR FB' as it is, and the condition of signature compression is broken. Discarded. Therefore, in this embodiment, as shown in FIG. 1, the relationship of Expression (3) is satisfied by inserting the F / F (1) which latches and holds the feedback signal FB at CLK1 ↑.

Furthermore, in (3), (4) is satisfied between d3, q2, and q'3, and there is no problem. However, as in the case of (2), the structure of the conventional LFSR remains as q'2 = d1 XOR q'1, and the condition of signature compression is broken. Therefore, in the present embodiment, as in the case of (2), the F / F (2) which latches and holds data at CLK2 ↑ is inserted, so that the relationship of (Equation 3) can be satisfied. Here, the delay circuit 3 is provided so that the data of the F / F 11 can be correctly propagated to the F / F 2, but may be unnecessary (the invention may be necessary or unnecessary). It doesn't really matter here, so we won't go into detail here).

As described above, in the present embodiment, a plurality of F / F pairs operating in synchronization with different clocks are appropriately selected, and F / F (1,2) for temporarily holding data such that the linear feedback condition for signature compression is satisfied is appropriate. By inserting in the position, it can cooperatively operate as one LFSR.

Next, Example 2 of this invention is described with reference to FIGS.

The apparatus according to the second embodiment includes a circuit capable of realizing the role played by the F / F (1, 2) in a simpler circuit in the first embodiment. 3 (a) is a diagram showing the configuration of this simplified circuit.

As shown in FIG. 3 (a), the simplified circuit is basically a circuit which performs a latch operation. This circuit is denoted by reference numeral 40 and is referred to as a latch circuit.

The latch circuit 40 includes a clocked inverter 41 as an input portion connected to the terminal D, and an inverter as an output connected to the terminal DO, with the output of the clocked inverter 41 input thereto. (42) and a latched portion 44 connected to the clocked inverter 41 and the node 43 of the inverter 42. The latch unit 44 includes an inverter 45 having an input connected to the node 43, and a clocked inverter 46 to which an output of the inverter 45 is input. The output of the clocked inverter 46 is connected to the node 43. In FIG. 3 (b), the basic circuit configuration of the clocked inverters 41 and 46 is shown. There are three inputs, the control input 1, the control input 2, and the input, and have one output. In normal usage, the inverting of the control input 1 is used as the control input 2, and when the control input 1 = Low (hereinafter referred to as 0), the output is hi-z (high impedance) regardless of the input value. When control input 1 = High (hereinafter, denoted as 1), the logical operation is performed like an inverter. The clock signal is given to the terminal C and supplied to the control input 2 of the clocked inverter 41 and the control input 1 of the clocked inverter 46. In the latch circuit 40, an inverter 47 for generating an inverted signal of the clock signal given to the terminal C is provided. The outputs thereof are the control input 1 and the clocked signal of the clocked inverter 41. It is supplied to the control input 2 of the inverter 46. In the figure, black dots near the clocked inverters 41 and 46 indicate that the adjacent input is the control input 2.

Next, the operation in the case of assembling the latch circuit 40 in the LFSR shown in FIG. 1 will be described.

First, as can be seen from FIG. 2, it is during the period of CLK1 = 1 that data d0 and d1 are compressed in CLK2 ↑. That is, it is good to hold the feedback signal FB only in the period of CLK1 = 1.

The latch circuit 40 shown in FIG. 3 latches the input data to the D terminal at the rising edge of the clock signal inputted to the C terminal and holds it during the period of the clock signal = 1, and during the period of the clock signal = 0, The input to the terminal is propagated to the DO terminal. Therefore, this latch circuit 40 is provided in place of the F / F 1 shown in FIG. 1, and CLK1 is connected to the C terminal (D terminal and DO terminal to nodes (a and b in FIG. 1, respectively). It is understood that by the latch circuit of about half the circuit amount of the F / F 1, the purpose can be sufficiently fulfilled.

As can be seen from FIG. 2, CLK3 ↑ at which data d2 and d3 are compressed overlaps with CLK2 ↓ (falling edge of CLK2). Here, if the F / F (2) is to be replaced by the latch circuit 40 shown in Fig. 3 (a), it is set to the C terminal-CLK2, but if it is skewed between CLK2 and CLK3 at this time, If CLK3 ↑ is later than the propagation delay from the D terminal of the latch circuit 40 to the output of the XOR gate 22 in FIG. 1 with respect to CLK2 ↓, the data that has already changed ( There is a risk that q'1 is XORed with the data d1 from the DUT and latched in the F / F 12. However, if the timing design between CLK2 ↓ and CLK3 ↑ is made with sufficient attention to this point, the latch propagation time can be used because the propagation delay time is considerably longer than the attainable interclockwise skew. However, in practice, such a timing design is often cumbersome and involves some risk, so it is preferable to use the F / F (2) from the simplicity of the design and the certainty of the operation.

As will be understood from the above description, the essence of the present invention is that the F / F of the side that sends data when combining a set of a plurality of F / Fs operating in synchronization with different clocks to form one LFSR ( If the clock for operating the F / F (including the feedback signal generated from the Q output of the F / F) is ahead of the clock for operating the F / F on the receiving side of the data, the electronic signal is not broken. Is to insert an F / F or latch to temporarily hold data stored in the F / F. In view of this, in the above, an example in which each clock has the same period and differs only in phase has been described. However, the present invention can be applied to a case where clocks having different periods are mixed.

In the above-described embodiment, if the relative position between the outputs from the DUT can be freely changed, the number of F / Fs or latches to be inserted into the LFSR can be suppressed to at least one. For example, a group of F / Fs (1, 2, ...) whose data is changed by edges of a plurality of clocks CLK1, CLK2, ... sequentially assigned in time series to satisfy a signature compression operation condition. In the case where the structure is arranged in the opposite direction to the flow of the data (except the feedback data) inside the LFSR, only the F / F or the latch for holding the feedback signal may be inserted. By making good use of such information, it is possible to effectively reduce the amount of additional circuits in realization of reality.

Next, as Example 3, an example in which the LFSR according to the present invention is used as a pseudo random number generation circuit will be described.

As shown in FIG. 4, in the case of constructing the pseudo random number generation circuit, the XOR circuits 20 to 25 for signature compression of the output from the DUT are removed from the circuit shown in FIG. For this purpose, the delay circuit 3 may be added at an appropriate position (these delay circuits 3 may be unnecessary).

In Fig. 4, the same reference numerals as those in Fig. 1 are assigned to the same meanings. The clocks CLK1, CLK2, CLK3 also change at the same timing as shown in FIG.

The conditions for generating the pseudo random number of the maximum length ( ^2n- 1 cycle) handled in the conventional example are as follows (the feedback signal FB is configured to give the maximum length).

q′0 = FB = q0 XOR q1 XOR q4 XOR q _n-1

q ′ _i = q _i-1 (i = 1,…, n-1)

In the case of pseudorandom number generation, unlike in the case of signature compression, it is difficult to define which clock is the first. However, in view of the nature of the present invention described above, the LFSR is the same as the conventional one without any of these definitions. In general,

q ′ _i = q ′ _i-1 = q _i-2

It is easily understood that the above conditions are not satisfied. Therefore, it is most preferable to provide F / F (1, 2; or latch) as shown in FIG.

Next, as a fourth embodiment, a semiconductor integrated circuit device in which an LFSR according to the present invention is applied to an I / O (input / output) portion of an LSI will be described.

Originally, registers and F / Fs are not provided in I / O terminals of LSIs. Therefore, if the present invention is to be applied to this part, it is necessary to add F / F to each input / output terminal. It seems to be not realistic in terms of growth. First, technical background and practicality of the present embodiment will be described.

In recent years, due to the large size and complexity of LSIs, the test of boards having a plurality of LSIs has become significantly difficult. Therefore, a scan-operable F / F is arranged for the input / output terminals constituting the I / O portion of each LSI. The boundary scan method is proposed to facilitate the board-level test by observing the output data from the LSI directly from the outside of the board or supplying arbitrary data from the outside of the board to the LSI. Many years ago, IEE standard 1149.1 was reached. The nominal method of boundary scan is derived from the fact that such a scanable F / F (called boundary scan F / F) is arranged at the boundary of the LSI. In any case, from the standpoint of ease of board-level test, there is a high possibility that registers and F / Fs are placed in the I / O section of the LSI in the future. In such a situation, the embodiments described below are highly practical. It becomes.

As shown in FIG. 5, inside the LSI 50, a logic circuit block (DUT) 51, which is a BIST object, an input test data generation circuit block 52, and three kinds of boundary scan circuits (hereinafter, Blocks 53, 54, 55, and a clock generation circuit 56 are provided, respectively. Here, the test data generation circuit block 52 is, for example, an LFSR based on the configuration shown in FIG. 4 or 10 (a). The B.S.C blocks 53, 54, and 55 are connected to each other to form one LFSR based on the configuration shown in FIG. 1, for example, and function as a test result determination circuit 57. As shown in FIG. The logic circuit block 51 has an input terminal section 71, which is connected to the output terminal section 72 of the test data generation circuit. The logic circuit block 51 has an output terminal portion 73, 74, 75, the output terminal portion 73 is the input terminal portion 76 of the BSC block 53, and the output terminal portion 74 is the BSC block 54. The output terminal section 75 is connected to the input terminal section 77 of the BSC block 55, respectively.

When executing BIST, the logic circuit block 51 receives the output of the input test data generation circuit block 52 as the test input data, and outputs a response output based on the input data to the BSC blocks 53 to 55. It is supposed to give.

The BSC blocks 53 to 55 operate in synchronization with the other clock signals CLK1, CLK2, and CLK3 supplied from the clock generation circuit block 56 (described later) at the time of executing BIST. And constitutes the LFSR according to the present invention as a whole. Therefore, any one of these B.S.C.blocks incorporates a circuit element for satisfying the signature compression condition according to the present invention as shown in FIG. 1 (not shown). In addition, these B.S.C.blocks have an FBI (feedback signal input) terminal or an FBO (feedback signal output) terminal for forming a linear feedback circuit. It also has a BSI (Boundary Scan Input) terminal and a BSO (Boundary Scan Output) terminal for boundary scan transmission. Although the boundary scan output from another boundary scan circuit block (not shown) is connected to the BSI terminal of the B.S.C.block 53, the output for selecting the feedback signal is separated during the BIST operation. The BSO terminal of the B.S.C.block 55 is further connected to the BSI terminal of another B.S.C.block (not shown).

6 shows the internal structure (for one bit) of the B.S.C.blocks 53 to 55 (for output terminals).

As shown in FIG. 6, the F / F 60 is a boundary scan F / F used for boundary scan operation, and also serves as an F / F constituting an LFSR in parallel signature compression operation of the output from the DUT. Used. The clock signal from the clock generation circuit block 56 is supplied to the terminal C of this F / F. The output terminal of the DUT (test circuit, i.e., the logic circuit block 51) is connected to the DI terminal, and in the normal operation given by S2 = 0, the LSI 50 is connected via the multiplexer 63 and the DO terminal. Output to an output terminal (output pad: not shown).

When S0 = 0 and S1 = 1, the boundary scan operation is performed, and the contents of the F / F corresponding to the F / F 60 of each bit in the B.S.C.blocks 53 to 55 are serially transmitted. The output from the DUT (test circuit, i.e., logic circuit block 51) is directed to the input of the LFSR, and the signature in the BSC blocks 53, 54, 55 when CLK = CLK1 ↑, CLK2 ↑, CLK3 ↑. The compression operation is performed.

On the other hand, when S0 = 1 and S1 = 0, the outputs from the DUT can be latched in the B, 5.C. blocks 53, 54, and 55 respectively by CLK1 ↑, CLK2 ↑, and CLK3 ↑. have. The F / F 61 is intended to prevent accidental supply of data such as causing strange operation to the outside of the LSI during the transmission of the boundary scan data using the boundary scan F / F 60. The contents of the F / F 61 can be changed by first transferring data necessary for each boundary scan F / F 6 in the boundary scan operation mode, and then raising the updating clock CLKUD. It is.

In addition, the clock generation circuit 56 integrally multiplies the frequency of the basic clock input signal CLK0 from the outside of the LSI 50, and sets the period corresponding to the integer multiplied frequency to the minimum chopped width. A plurality of clocks CLK1, CLK2, and CLK3 are generated inside. An example of the structure of the circuit block 56 is shown in FIG. 7 (when the frequency of CLK0 is quadrupled).

As shown in FIG. 7, this circuit block is composed of a PLL (Phase Locked Loop) circuit 64, a 2-bit counter 65, and a 2-bit decoder 66. As shown in FIG. The PLL circuit is a circuit that integers the frequency of the basic clock input signal CLK0 from the outside. In this case, the clock signal CLK having a frequency four times that of the clock input signal CLK0 is generated. The counter 65 counts up by this signal CLK. The decoder 66 is configured to set only the clock outputs CLK1, CLK2, CLK3, and CLK4 to 1 with respect to the output values 00, 01, 10, and 11 of the counter 65, respectively, where CLK4 is in the LSI 50. Not used). The counter 65 is initialized such as outputting 11 by the reset signal RST = 1. The timing chart of the clock signal obtained by the circuit shown in FIG. 7 as described above is shown in FIG.

Strictly speaking, the signature compression at the three types of clock edges, as in this example, is considerably improved compared to the conventional example, but it is rather difficult to accurately check the AC output delay of the DUT. When a precise time resolution is required, for example, the PLL circuit inside the circuit block 56 generates a higher frequency clock signal CLK than in the above embodiment, and furthermore, the width of the time between edges of the clock is reduced. You need to thin it to use it for LFSR.

At this time, it is of course possible to realize a method in which the plurality of clocks supplied by the circuit block 56 are supplied from the outside of the LSI via a plurality of pins. Furthermore, although not specifically shown, it is of course also possible to realize a pseudo random number-producible linear shift register (LFSR) as shown in FIG. 4 as the test data generating circuit. At this time, the output of the test data generating circuit is led to the input terminal of the DUT.

The present invention can be applied to various circuits in addition to the embodiments described above. For example, the BILBO (Built-In Logic Block Observer) shown in FIG. 9 can also be realized. BIST supplies a large number of test data from the automatic test data generation circuit to the DUT (test circuit), compresses the DUT's multiple response outputs to the LFSR, and finally checks the result (signature) in the LFSR. It has a big advantage that it is possible to detect faults by simply doing it, but on the contrary, it can be difficult to diagnose faults that specify the fault part because the DUT does not know the cycle or abnormal data that the weird output is made. It has a weak point to say. BILBO attempts to overcome this weakness by adding a simple circuit to the LFSR to allow for both signature compression and scan operations. The operation of BILBO is defined by two kinds of control signals B1 and B2, as can be seen from FIG. Normal operation when B1 = 1 and B2 = 1 (each output from the DUT (Z1 to Z8) is latched to each D-type F / F), and when B1 = 1 and B2 = 0, it is a LFSR of parallel input. In operation, parallel signature compression is possible. In addition, when B1 = 0 and B2 = 0, a scanning operation is performed. If this BILBO is to be applied even when the internal F / F operates in synchronization with different clocks, it will be readily understood that the present invention may be utilized. All of the types to which the present invention is applied to the circuits based on such LFSR should be included in the scope of the present invention. Also, from the embodiment of the present invention, changes in the level of circuit elements such as logic gates and transistors, and various signals It is naturally within the scope of the present invention to be obtained by a change in the polarity or the like.

In the LFSR described in accordance with the above embodiment, it is possible to operate in synchronization with a different clock for each F / F to generate a pseudo random number or to perform signature compression. In the I / O section of the LSI whose internals and signals change at various timings, it is possible to construct a high-performance BIST that has high area efficiency and can detect an AC output delay failure of the DUT.

[Effects of the Invention]

As described above, according to the present invention, it is possible to provide a linear feedback shift register and a semiconductor integrated circuit device having the same, including F / F operated by different clocks and satisfying the condition of pseudo random number generation or linear feedback. have.

Claims (8)

A pair of a plurality of flip-flops operating in synchronization with a plurality of clocks generated from either inside or outside the semiconductor integrated circuit chip is connected in series, and a means for establishing a linear feedback condition is inserted between the pairs of flip-flops. A linear feedback shift register, the output of the linear feedback shift register is electrically coupled to a terminal functioning as at least an input terminal of a semiconductor integrated circuit portion provided inside the chip, so that the linear feedback shift register is used as a test data generation circuit. And said establishing means is a delay circuit for delaying an output signal output from the pair of flip-flops to establish a condition of linear feedback and inputting it into another pair of flip-flops. The semiconductor integrated circuit device according to claim 1, wherein the delay circuit comprises at least one of a flip flop and a latch circuit. The chip of claim 1, further comprising a clock generating means inside the chip which receives a supply of a base clock from outside of the semiconductor integrated circuit chip and generates a plurality of different clocks from the base clock. And a plurality of clocks are generated by multiplying the frequency of the base clock by an integer multiple and a period corresponding to the multipled frequency with a minimum chopped width. 4. The semiconductor integrated circuit device according to claim 3, wherein said clock generating means comprises a PLL circuit. A pair of a plurality of flip-flops operating in synchronization with a plurality of clocks generated from either inside or outside the semiconductor integrated circuit chip is connected in series, and a means for establishing a linear feedback condition is inserted between the pairs of flip-flops. A signature compression register, wherein the output of the signature compression register is electrically coupled to a terminal functioning as at least an output terminal of a semiconductor integrated circuit portion provided inside the chip, so that the signature compression register functions as a signature compression circuit of a test result. And said establishing means is a delay circuit for delaying an output signal output from a pair of flip-flops to establish a condition of linear feedback and inputting it to another pair of flip-flops. 6. The semiconductor integrated circuit device according to claim 5, wherein the delay circuit comprises at least one of a flip flop and a latch circuit. 6. The apparatus of claim 5, further comprising a clock generating means inside the chip which is supplied with a base clock from outside the semiconductor integrated circuit chip and generates a plurality of different clocks from the base clock. And a plurality of clocks are generated by multiplying the frequency of the base clock by an integer multiple and a period corresponding to the multipled frequency with a minimum chopped width. 8. The semiconductor integrated circuit device according to claim 7, wherein said clock generation means comprises a PLL circuit.