JP3594582B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a scan test circuit, and more particularly to a semiconductor device having a test circuit having a configuration in which one scan data input terminal is connected to a plurality of scan chains.
[0002]
[Prior art]
Tests are performed to determine whether the electrical characteristics, functions, and performance of the manufactured semiconductor devices meet specified standards, identify defective products in the manufacturing process, and conduct inspections to prevent the products from being put on the market. However, in recent years, the inspection cost required for the inspection has been greatly increased with an increase in the circuit scale of the semiconductor device. Normally, a semiconductor test device (hereinafter, referred to as an LSI tester) is used for testing the electrical characteristics, functions, and performances of the semiconductor device. However, as the circuit scale of the semiconductor device increases, the LSI tester used becomes expensive. In addition, the number of test patterns for testing a semiconductor device with an LSI tester has become enormous, and the test time required for each semiconductor device has been greatly increased. For this reason, most of the inspection cost of the semiconductor device is governed by the usage time of the LSI tester used in the test.
[0003]
As a technique for facilitating the test of a semiconductor device and reducing the number of test patterns, there is a scan method in which a circuit capable of setting and reading a value is added to a flip-flop (F / F) in an internal circuit of the semiconductor device. By the scanning method, the F / F in the internal circuit can be apparently used as a virtual external input terminal or a virtual external observation terminal, and an enormous number of times are required to set the internal state of the circuit to a predetermined state. Can often be handled as a combinational circuit that does not need to set an internal state. This facilitates automatic generation of test patterns used in the test.
[0004]
In the scan method, an F / F with a scan function (hereinafter, referred to as SF / F) in which a scan path test function is added to an F / F in a circuit is connected in the form of a shift register, and these SFs are connected from one external input terminal. / F can be set freely, and the SF / F values can be observed from one external output terminal. A state in which these SFs / Fs are connected in a shift register form is called a scan chain, and a set and observation of a value in the scan chain is performed using a pair of external input terminals and external output terminals per scan chain. I do.
[0005]
In recent years, there are large-scale circuits in which the number of SFs / Fs included in this scan chain is hundreds of thousands or more, and a value required for a test is set to the SF / Fs through the scan chain. , SF / F, the scan shift operation for observing the result of the test (hereinafter, referred to as SSF operation) is occupying most of the test time of the semiconductor device. If the time required for the SSF operation (hereinafter referred to as SSF time) can be reduced, the test time can be reduced, that is, the test cost can be reduced.
[0006]
As a conventional general method of shortening the SSF time, there is a method of setting a plurality of scan chains to reduce the number of SFs / Fs included in one scan chain, thereby shortening the SSF time as a whole. . In this method, as the number of scan chains increases, the number of external terminals connected to the scan chains needs to increase. However, in general, the number of scan chain external terminals that can be connected to an LSI tester is limited, and the number of external terminals of the circuit under test itself is limited, so that the number of scan chains cannot be increased unnecessarily.
[0007]
As one method for solving this problem, there is a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2000-258500 (hereinafter referred to as a known example). This provides a method of setting and observing values for a plurality of scan chains with a pair of external terminals. The number of SF / Fs per scan chain is effectively used by effectively using the limited external terminals for the scan chains. And reduce test time. FIG. 11 is a block diagram showing a circuit configuration example of a scan chain used in a conventional general scan method, and FIG. 12 is a waveform example of a main node of the scan chain in FIG. FIG. 13 is a block diagram showing a circuit configuration example of a scan chain disclosed in a known example, and FIG. 14 is a waveform example of a main node of the scan chain in FIG. Hereinafter, with reference to FIGS. 11 to 14, an outline of the configuration, operation, and effects of the scan chain disclosed in the known example will be described in comparison with a conventional general scan chain.
[0008]
In FIG. 11, the description of the logic unit not related to the scan chain of the semiconductor device 801 is omitted. The scan chain 810 includes SF / Fs 811, 812, 813, and 814. The scan chain 810 synchronizes with a clock signal supplied to an external input terminal 803 from a scan data input terminal 803. The signal is taken in, and the signal is taken out from a scan-out (hereinafter, Sout) external output terminal 805. Similarly, the scan chain 820 includes SF / Fs 821, 822, 823, and 824. The scan chain 820 fetches a signal from the scan data input terminal 804 in synchronization with a clock signal supplied to the SC external input terminal 803, and outputs the signal from the Sout external terminal. The signal is extracted from the output terminal 806.
[0009]
A part of a general SSF operation will be described with reference to a waveform example shown in FIG. FIG. 12 shows a clock signal waveform 120 applied to the SC external input terminal 803, a signal waveform 121 applied to the scan data input terminal 802, a signal waveform 122 on the SO output terminal of the SF / F 811, and a scan data input terminal 804. A signal waveform 123 to be given and a signal waveform 124 on the SO output terminal of the SF / F 821 are shown. The clock signal waveform 120 is a waveform that rises at times t1, t3, t5, and t7 and falls at times t2, t4, t6, and t8. It is assumed that all SFs / Fs 811, 812, 813, 814, 821, 822, 823, and 824 are positive edge type F / Fs that latch an input signal at a rising edge of a clock signal. At time t1, when the clock signal waveform 120 rises, the signal at the scan data input terminal 802 at that time has the logical value “1” from the waveform 121, and the logical value “1” is captured by the SF / F 811. The signal on the SO output terminal of the SF / F 811 is updated to the logical value “1”. Similarly, the signal on the SO output terminal of the SF / F 821 also takes in the signal of the scan data input terminal 804 at time t1, and becomes a logical value “0”. As described above, in synchronization with the SC external input terminal 803, the scan chains 810 and 820 fetch signals from the scan data input terminals 802 and 804, sequentially set a logical value to the SF / F, and make each SF / F A logical value is propagated to an internal circuit (not shown) of the semiconductor device 801 via the Q output terminal. At the same time as the scan-in operation, the state value of the internal circuit (not shown) of the semiconductor device 801 which has been taken into each SF / F via the D terminal of each SF / F before the SSF operation is output to the Sout external output terminal 805. And 806 are also output. At this time, if the semiconductor device 801 has a manufacturing defect, the influence of the defect is applied to one of the SF / Fs constituting the scan chain 810 or 820 via the SF / F D terminal before the SSF operation. If the signal propagates to the SF / F, the influence of the defect can be observed at the Sout external output terminal 805 or 806 through the SSF operation. For example, assuming that the SF / F 814 does not have a circuit manufacturing defect, a logical value “1” propagates through the Q output terminal as an expected value, and a logical value “0” propagates when a defect exists. , A logical value different from the expected value is observed at the Sout external output terminal 805, so that it is possible to identify that the semiconductor device 801 is defective.
[0010]
In the SFs / Fs 811, 812, 813, 814, 821, 822, 823, and 824, the signal held by the F / F is output to the SO output terminal and the Q output terminal. During the SSF operation, the logical value of the signal at the SI terminal is taken in by the F / F in synchronization with the clock signal input to the CLK terminal, and except during the SSF operation, the logical value of the signal at the D terminal is changed to the F / F. F is taken in.
[0011]
In the conventional general scan chain configuration shown in FIG. 11, it is possible to set a predetermined logical value to eight SFs / Fs using two scan data input terminals 802 and 804 with a clock signal for four cycles. it can. If only one scan data input terminal and one Sout external output terminal can be used in the LSI tester, only one scan chain can be used, and eight SF / Fs are connected to one scan chain. Therefore, a clock signal for eight periods is required. This means that the test time is doubled, which leads to a doubling of the test cost, which causes a problem of an increase in the test cost.
[0012]
To solve this problem, in a known example, signals are supplied to a plurality of scan chains from one scan data input terminal, and signals of a plurality of scan chains are collectively extracted from one Sout external output terminal. An increase in test time can be avoided, and an increase in test cost can be suppressed.
[0013]
FIG. 13 shows a configuration example of a known scan chain. 11 is different from the conventional example of FIG. 11 in that the scan data input terminal 804 for the scan chain 820 and the terminal corresponding to the Sout external output terminal 806 are eliminated, and the scan data input terminal 802 and the Sout external output terminal 805 for the scan chain 810 are connected. , For the scan chain 820. However, the Sout external output terminal is shared via an exclusive OR gate (hereinafter, referred to as EXOR) as a code compression circuit.
[0014]
Specifically, the scan chain 910 mounted on the semiconductor device 901 is composed of SF / Fs 911, 912, 913, and 914, and scans in synchronization with a clock signal given to the SC external input terminal 903. A signal is taken in from a data input terminal 902, and a signal is taken out from an Sout external output terminal 905 via an EXOR 941 as a code compression circuit. Similarly, the scan chain 920 also includes SF / Fs 921, 922, 923, and 924, and fetches a signal from the scan data input terminal 902 in synchronization with a clock signal supplied to the SC external input terminal 903. Similarly, a signal is extracted from the Sout external output terminal 905 via the EXOR 941. Note that, also in this case, the description of the logic unit not related to the scan chain of the semiconductor device 901 is omitted.
[0015]
With this configuration, it is possible to set and observe values for a plurality of scan chains 910 and 920 at one scan data input terminal 902 and one Sout external output terminal 905.
[0016]
Next, a part of the known SSF operation will be described with reference to FIG. The difference from FIG. 12 is that the signal waveform 220 at the SO output terminal of the SF / F 921 is exactly the same as the signal waveform 122 at the SO output terminal of the SF / F 911. As described above, in synchronization with the rise of the clock signal waveform 120 applied to the SC external input terminal 903 at times t1, t3, t5, and t7, the logical value of the signal at the scan data input terminal 902 at that time is extracted, and SF / The logical values of the signals at the SO output terminals of F911 and 921 are changed to the logical value “1” at the time t1, to the logical value “0” at the time t3, to the logical value “0” at the time t5, respectively. At t7, the logic value becomes "1". Also, at the Sout external output terminal 905, the exclusive OR of the logical values of the signals at the SO output terminals of the SFs / Fs 914 and 924 is observed as an expected value.
[0017]
If the semiconductor device 901 has a manufacturing defect and the influence of the defect has propagated to the D terminal of the SF / F of either of the scan chains 910 or 920 before the SSF operation, the SF / Since the signal propagates to the SO output terminal of F914 or 924, the logical value of the signal passing through the EXOR 941 is different from the logical value (expected value) of a correct signal propagating when there is no defect at the Sout external output terminal 905. It can be determined whether the semiconductor device 901 has a defect. For example, when there is no defect, when the logical values “0” and “1” propagate to the SO output terminals of the SF / Fs 914 and 924, respectively, the logical value “1” is observed as the expected value at the Sout external output terminal 905. I do. However, when there is a defect and the influence propagates to the SF / F 914 and the signal at the SO output terminal of the SF / F 914 becomes a logical value “1”, a logical value “0” is observed at the Sout external output terminal 905. That is, since the expected value is different from “1”, it can be identified that the semiconductor device 901 has a defect.
[0018]
In the scan chain configuration of the known example shown in FIG. 13, a predetermined logic value is set to eight SF / Fs 911 to 914 and 921 to 924 by using one scan data input terminal 902 and using a clock signal for four cycles. be able to. Even if only one scan data input terminal and one Sout external output terminal can be used in the LSI tester, signals can be set to all SF / Fs with four cycles of clock signals. Unlike the conventional general scan chain configuration as shown, the test time and therefore the test cost do not increase.
[0019]
[Problems to be solved by the invention]
In the semiconductor device disclosed in the above-mentioned known example, the SSF time can be sufficiently reduced, but there are two problems as follows.
[0020]
First, since a plurality of scan chains controlled by a pair of external terminals can only be set to exactly the same value, a test pattern generated by a general automatic test pattern generation (ATPG (Automatic Test Pattern Generation)) tool. If it is desired to freely set the value determined by the above method to the F / F of the internal circuit through the scan chain, there is a problem that it is difficult to apply the method of the known example.
[0021]
Secondly, since a plurality of scan chains controlled by a pair of external terminals can each be set to exactly the same value, the controllability of the internal circuit is reduced. However, there is a problem that more test patterns are required, and the effect of reducing the test time may not be obtained.
[0022]
The above two problems will be described with reference to FIG. FIG. 15A shows a sample circuit, a sample fault, and a test pattern for detecting the sample fault according to a conventional general scan chain configuration. 15A includes a scan data input terminal 851, internal circuits 852 and 853, buffers 854 and 856, inverters (hereinafter referred to as INV) 855 and 857, SF / Fs 858, 859, 860 and 861, and AND. The scan chain 869 includes a gate 862, an OR gate 863, external output terminals 864 and 865, and a Sout external output terminal 866. The four SF / Fs 858, 859, 860, and 861 configure a scan chain 869. If it is assumed that there is a stuck-at-0 fault 867 at the output terminal of the AND gate 862 and a stuck-at-1 fault 868 at the output terminal of the OR gate 863, these faults (for example, as a defect in manufacturing, a certain signal line is short-circuited to the power supply). To detect (1 degenerate) or short-circuit to ground (0 degenerate), the test pattern 870 is transmitted from the scan data input terminal 851 to four SF / What is necessary is just to scan in F858, 859, 860, and 861. Here, detecting a fault means that the logical value of the signal observed at the external output terminal only needs to be different between the case where the fault exists and the case where the fault does not exist.
[0023]
For example, the external output terminal 864 can observe the logical value “1” if the stuck-at-0 fault 867 does not exist, but observes the logical value “0” under the influence of the fault if the stuck-at-0 fault 867 exists. Therefore, it is possible to identify that the sample circuit has failed due to a manufacturing defect. The 1 stuck-at fault 868 can be similarly detected. In this way, the stuck-at-0 fault 867 and the stuck-at-1 fault 868 can be detected by setting one test pattern to SF / F with a clock signal of four cycles.
[0024]
On the other hand, in the scan chain configuration disclosed in the known example shown in FIG. 15B, the conventional scan chain 869 of FIG. 15A is divided into scan chains 969 and 970, and one test pattern is clocked for two cycles. Although signals can scan in four SF / Fs 958, 959, 960, and 961, two test patterns 971 and 972 are required to detect a stuck-at-0 fault 967 and a stuck-at-1 fault 968. That is, in the known scan chain configuration, the stuck-at-0 fault and the stuck-at-1 fault cannot be detected unless clock signals for a total of four cycles are used, and the same test time as the test time by the general scan chain configuration is used. It is necessary. That is, the effect of reducing the test time, which is the effect of the known example, that is, the effect of reducing the test cost cannot be obtained. The problem is that, because of the limitations on the configuration and operation of the scan chain of the semiconductor device disclosed in the known example, only the same logical value can be set to a plurality of scan chains connected to one scan data input terminal. What happens.
[0025]
Accordingly, an object of the present invention is to provide a semiconductor device having a test circuit capable of reducing the SSF time without deteriorating the controllability of the internal circuit section and greatly reducing the test time and the test cost. is there.
[0026]
[Means for Solving the Problems]
Therefore, a semiconductor device according to the present invention includes at least a plurality of scan chains including a plurality of scan path test flip-flops, and a scan data input terminal for inputting scan path test data,
The plurality of scan chains each include at least one of a first scan chain for inputting first scan data and a second scan chain for inputting second scan data different from the first scan data,
All the scan path test flip-flops included in the first scan chain latch their scan data at a first timing,
All the scan path test flip-flops included in the second scan chain latch respective scan data at a second timing different from the first timing,
Further, the scan data input terminal has at least one first scan data input terminal commonly connecting a scan data input terminal of the first scan chain and the second scan data input terminal.
[0027]
In this case, the apparatus further comprises a clock input terminal for externally inputting a first clock signal, wherein the first timing is a timing synchronized with a first edge of the first clock signal, and the second timing is the first clock. The timing may be synchronized with a second edge of the signal in a direction opposite to the first edge.
[0028]
In addition, a clock input terminal for inputting a first clock signal from the outside, a mode signal for setting the first clock signal and a scan shift operation mode are input, and a predetermined time is delayed from the first clock signal in the scan shift operation mode. Scan clock control means for outputting a second clock signal.
In the scan shift operation mode,
All the scan path test flip-flops included in the first scan chain latch scan data at a timing synchronized with the first clock signal,
All of the scan path test flip-flops included in the second scan chain may latch scan data at a timing synchronized with a second clock signal.
[0029]
Further, a signal delay unit may be further provided between a clock input terminal for externally inputting the first clock signal and the first scan chain.
[0030]
Further, another semiconductor device of the present invention includes a plurality of scan chains configured including a plurality of flip-flops for scan path test, and a scan data input terminal for inputting data for scan path test,
The plurality of scan chains each include at least one of a first scan chain for inputting first scan data and a second scan chain for inputting second scan data different from the first scan data,
All the scan path test flip-flops included in the first scan chain and the second scan chain latch respective scan data at a first timing,
Further, the scan data input terminal is connected to a scan data input terminal of the first scan chain and has at least one first scan data input terminal connected to the second scan data input terminal via predetermined latch means. It is characterized by having one.
[0031]
At this time, a data input terminal and a data output terminal of the latch unit are connected to the first scan data input terminal and the scan data input terminal of the second scan chain, respectively.
It is preferable that the latch unit latches an input signal at a timing different from a timing at which the scan path test flip-flop included in the second scan chain latches scan data.
[0032]
A clock input terminal for inputting the first clock signal;
All the scan path test flip-flops included in the first and second scan chains latch scan data at a timing synchronized with a first edge of the first clock signal,
The latch means may latch an input signal at a timing synchronized with a second edge of the first clock signal in a direction opposite to the first edge.
[0033]
A clock input terminal for inputting the first clock signal;
All the scan path test flip-flops included in the first and second scan chains latch scan data at a timing synchronized with the first clock signal,
The latch means may latch an input signal at a timing synchronized with an inverted signal of the first clock signal.
[0034]
A scanout external output terminal for outputting a signal indicating a logic state of a predetermined node of the internal circuit to the outside; and a data compression unit,
Connecting the scan data output terminals of all the scan chains connected to the first scan data input terminal to the input terminals of the data compression means;
An output terminal of the data compression unit may be connected to the scan-out external output terminal. At this time, the data compression means can be constituted by an exclusive OR circuit or a multiplexer.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0036]
FIG. 1 is a block diagram showing a configuration example of a scan chain of a scan path test circuit included in the first embodiment of the semiconductor device of the present invention. Referring to FIG. 1, a semiconductor device 10 of the present embodiment includes an internal circuit for realizing a desired function (not shown), a scan path test circuit 20, a scan data input terminal 112, an SC external input terminal 113, and a scan mode external input. At least a terminal 401 and a Sout external output terminal 115 are provided. The scan path test circuit 20 includes a scan chain 102 as a first scan chain, a scan chain 107 as a second scan chain, an EXOR 201 as code compression means, and an SC control circuit 402 as SC control means. I have. In the following description, the illustration and description of internal circuits and external connection terminals that are not related to the configuration and operation of the scan path test circuit 20 will be omitted as appropriate without particular notice.
[0037]
First, the SF / F configuring the scan chains 102 and 107 will be described. SF / F is an SI input terminal for inputting scan data, an SO output terminal for outputting scan data, a CLK input terminal for inputting a clock signal, and a D input terminal and a Q output connected to a predetermined node of an internal circuit unit. At the SSF operation mode, latches the signal at the SI input terminal in synchronization with the clock signal, and outputs the signal to the SO output terminal. In the normal operation mode other than the SSF operation mode, the D input terminal is synchronized with the clock signal. The present invention is not particularly limited as long as it has a function of latching the above signal and outputting it to the Q output terminal and the SO output terminal. FIG. 16 is a block diagram illustrating a specific configuration example of the SF / F that performs the SSF operation with one clock signal. Referring to FIG. 16, the multiplexed type SF / F50 includes a multiplexer (hereinafter, referred to as MUX) 51 and a normal F / F53. The D input terminal, the SI input terminal, the mode signal input terminal SE, and the CLK input terminal of the SF / F 50 are connected to the 0 selection input terminal, the 1 selection input terminal, the selection control input terminal of the MUX 51, and the clock input terminal of the F / F 53. The output terminals of the MUX 51 are connected to the D input terminal of the F / F 53, and the Q output terminal of the F / F 53 is connected to the Q output terminal and the SO output terminal of the SF / F 50. At the time of normal operation, the mode signal input to the mode signal input terminal SE is fixed to the logical value “0”, and the normal F / F operation is performed by the clock signal and the data signal input to the D input terminal. At the time of the SSF operation, the mode signal becomes a logical value “1”, the clock signal input to the CLK input terminal becomes the scan clock which is the first clock signal, and the scan-in data input to the SI input terminal is fetched to realize the SSF operation. .
[0038]
Note that all SF / Fs (SF / Fs 103 to 106 and SF / Fs 108 to 111) in the following description of the embodiments have the same operations and functions as the SF / F 50 described above. However, for the sake of simplicity, all the illustrations of the mode signal input terminal SE for inputting a mode signal for designating the normal operation mode or the SSF operation mode and the wiring connected to the mode signal input terminal SE are omitted. In the SSF operation mode, the signal at the SI input terminal is latched in synchronization with the rising edge of the clock signal input to the CLK input terminal and output to the SO output terminal. The signal at the input terminal is latched in synchronization with the rising edge of the clock signal input to the CLK input terminal, and is output to the SO output terminal and the Q output terminal.
[0039]
Next, the configuration of the scan chains 102 and 107 will be described. The scan chain 102 is configured to include SF / Fs 103, 104, 105, and 106, which are scan path test F / Fs. The SI input terminal and the SO output terminal of the first SF / F 103 are connected to the scan data input terminal 112 and the SI input terminal of the SF / F 104, respectively. The SO output terminal of the SF / F 104 is connected to the SI input terminal of the SF / F 105, the SO output terminal of the SF / F 105 is connected to the SI input terminal of the SF / F 106, and the SO output terminal of the final stage SF / F 106 is connected to one of the EXOR 201. Connected to the input terminals of Further, all the CLK input terminals of the SFs / Fs 103 to 106 are connected to the SC external input terminal 113, and all the mode signal input terminals (not shown) are connected to the scan mode external input terminal 401. With this configuration, in the SSF operation mode, the SSF operation of sequentially latching the signal that is the scan data input to the scan data input terminal 112 in synchronization with the first clock signal input from the SC external input terminal 113 is performed. Then, while setting a desired logical value to each SF / F configuring the scan chain 102, the state of a predetermined internal circuit unit of the semiconductor device 10 at the start of the SSF operation is changed via the EXOR 201 to the Sout external output terminal 115. Take out from.
[0040]
The scan chain 107 includes SF / Fs 108, 109, 110, and 111 that are scan path test F / Fs. The SI input terminal and the SO output terminal of the first SF / F 108 are connected to the scan data input terminal 112 and the SI input terminal of the SF / F 109, respectively. Also, the SO output terminal of the SF / F109 is the SI input terminal of the SF / F110, the SO output terminal of the SF / F110 is the SI input terminal of the SF / F111, and the SO output terminal of the final stage SF / F111 is the other end of the EXOR 201. Connected to the input terminals of Further, all the CLK input terminals of the SFs / Fs 108 to 111 are connected to a terminal 417 for outputting an SC2 signal, which is a second clock signal of the SC control circuit 402, which will be described later. Connect to the input terminals 401 respectively. With this configuration, in the SSF operation mode, the SSF operation of sequentially latching the signal that is the scan data input to the scan data input terminal 112 in synchronization with the second clock signal output from the SC control circuit 402 is performed. While setting a desired logical value to each SF / F constituting the scan chain 107, the state of a predetermined internal circuit portion of the semiconductor device 10 at the start of the SSF operation is output from the Sout external output terminal 115 via the EXOR 201. Take out.
[0041]
If necessary, for example, a delay adjusting circuit 403 is inserted between the SC external input terminal 113 and the scan chain 102 to adjust the timing between the first clock signal and the scan data signal input from the scan data input terminal 112. The matching is performed so that each SF / F of the scan chain 102 can reliably latch predetermined scan data.
[0042]
Next, the SC control circuit 402 will be described. The SC control circuit 402 receives a first clock signal input from the SC external input terminal 113 and a mode signal input from the scan mode external input terminal 401 to set the semiconductor device 10 to the SSF operation mode, and generates a second clock signal. Is output. FIG. 2 is a block diagram illustrating an example of the configuration of the SC control circuit 402. Referring to FIG. 2, the SC control circuit 402 includes a terminal 405 connected to the SC external input terminal 113 to input a first clock signal, a terminal 407 connected to the scan mode external input terminal 401 to input a mode signal, It comprises a terminal 417 for outputting an SC2 signal which is a two-clock signal, AND gates 410, 413 and 415, INVs 411 and 414, an F / F 412 with a negative edge type reset bar, and a multiplexer gate (hereinafter referred to as MUX) 416. ing. The first input terminal of each of the AND gates 410 and 413 and the input terminal of the INV 414 are all connected to the terminal 405, and the second input terminal of the AND gate 410 and the first input of the AND gate 415 are connected to the terminal 407. , The D input terminal and the reset input terminal of the F / F 412, and the input terminal of the INV 411. Also, the output terminal of INV 411 is the second input terminal of AND gate 413, the output terminal of AND gate 413 is the 0 selection input terminal of MUX 416, the output terminal of INV 414 is the 1 selection input terminal of MUX 416, and the output terminal of AND gate 410 is The output terminal is the clock input terminal of the F / F 412, the Q output terminal of the F / F 412 is the second input terminal of the AND gate 415, the output terminal of the AND gate 415 is the selection control input terminal 418 of the MUX 416, and the output of the MUX 416. The ends 419 are connected to the terminals 417, respectively. For example, the MUX 416 transmits the signal of the 0 selection input terminal to the output terminal when the signal input to the selection control input terminal 418 is a logical value “0”, and outputs the signal of the 1 selection input terminal to the output terminal when the signal input to the selection control input terminal 418 is a logical value “1”. To communicate. With this configuration, for example, when the signal input to the terminal 407 has the logical value “1”, the signal input to the terminal 405 changes from the logical value “1” to the logical value “0”, A signal that transitions to the logical value “1” is generated and output from the terminal 417. When the signal input to the terminal 407 has a logical value “0”, the signal input to the terminal 405 is output from the terminal 417 as it is.
[0043]
Next, the operation of the scan path test circuit 20 of the present embodiment will be described. FIG. 3 is a waveform diagram of main nodes for explaining the operation of the scan path test circuit 20. The signal waveforms 120, 420, 122, 421, 422, and 423 show the SC external input terminal 113 and the scan data input terminal 112. , SF / F103, the SO output terminal of SF / F108, the scan mode external input terminal 401, and the signal waveform at the terminal 417 of the SC control circuit 402. Hereinafter, description will be made with reference to FIGS. The scan path test circuit 20 included in the semiconductor device 10 of the present embodiment is a mode input from the scan mode external input terminal 401 in the SSF operation mode in which the state setting and the state read of the internal circuit unit (not shown) for the test are performed. The signal becomes a logical value “1” as shown by a signal waveform 422, for example, and the scan chains 102 and 107 perform the SSF operation. At this time, the first clock signal (signal waveform 120) input from the SC external input terminal 113 is supplied to each CLK input terminal of the SF / Fs 103 to 106 constituting the scan chain 102 as it is, but the scan chain 107 is constituted. A second clock signal (signal waveform 423) generated by the SC control circuit 402 is supplied to each CLK input terminal of the SFs / Fs 108 to 111. As described above, in the second clock signal generated by the SC control circuit 402 in the SSF operation mode, the first clock signal supplied from the SC external input terminal 113 transits from the logical value “1” to the logical value “0”. In this case, the waveform changes from the logical value “0” to the logical value “1”. Therefore, in the SSF operation mode, each SF / F constituting the scan chain 102 latches the signal of the respective SI input terminal at the rise of the first clock signal, and each SF / F constituting the scan chain 107 transmits the respective SI / F. The signal at the input terminal is latched when the first clock signal falls. Then, the SSF operation is performed by inputting the first clock signal a predetermined number of times, and the signal supplied to the scan data input terminal 112 is sequentially latched by each SF / F constituting the scan chains 102 and 107. At this time, a signal, which is scan data supplied from the outside to the scan data input terminal 112, is provided, if necessary, for one period of the first clock signal, for example, during a period when the first clock signal is at a high level and a period at a low level. If one is changed, different scan data can be set to the two scan chains 102 and 107 with one scan data input terminal 112.
[0044]
For example, assuming that the scan data supplied to the scan data input terminal 112 is a signal waveform 420 shown in FIG. 3, since the logical value is “1” at time t1, the logical value “1” is located at the top of the scan chain 102. Then, the signal is latched by the SF / F 103 via the SI input terminal of the SF / F 103 and the rising edge of the first clock signal supplied to the SC external input terminal 113, and the signal at the SO output terminal of the SF / F 103 has a signal waveform 122. Is updated to the logical value "1" as shown in FIG. Similarly, at time t2, the second clock signal output from SC control circuit 402 rises as shown by signal waveform 423, and the signal at scan data input terminal 112 at that time has the logical value “as shown by signal waveform 420”. Therefore, the logical value “0” is latched by the SF / F 108 via the SI input terminal of the SF / F 108 located at the head of the scan chain 107, and the signal at the SO output terminal of the SF / F 108 has a signal waveform. As indicated by reference numeral 421, the logical value is updated to “0”.
[0045]
Similarly, at time t3, t5, and t7, the SF / F 103 sequentially shifts the logic value of the signal latched earlier to each SF / F constituting the scan chain 102, and shifts the logic value of the signal at the scan data input terminal 112. Latch values sequentially. The SF / F 108 shifts the logical value of the signal at the scan data input terminal 112 while sequentially shifting the logical value of the previously latched signal to each SF / F constituting the scan chain 102 at times t4, t6, and t8. Latch sequentially. As a result, the signal at the SO output terminal of the SF / F 103 located at the head of the scan chain 102 forms a signal waveform 122, and the signal at the SO output terminal of the SF / F 108 located at the head of the scan chain 107 has a signal waveform 421. Form.
[0046]
In addition, since the SF / Fs 103 to 106 and SF / Fs 108 to 111 incorporate a logical value indicating the state of the internal circuit of the semiconductor device 10 at the start of the SSF operation, for example, at time t11 after the start of the SSF operation. , T12, t13, and t14, by observing the logical value of the signal output from the Sout external output terminal 115, it is possible to determine whether the state of the internal circuit unit of the semiconductor device 10 at the start of the SSF operation is normal. Specifically, for example, at the start of the SSF operation, the expected logical value of the signal latched by the SF / F 106 via the D input terminal of the SF / F 106 is a logical value “0”, and When the expected logical value of the signal latched by the SF / F 111 is the logical value “1”, the expected value observed at the Sout external output terminal 115 at the time t11 is the logical value “the exclusive OR value” of these. 1 ". When the semiconductor device 10 fails due to a manufacturing defect and the signal latched in the SF / F 106 at the start of the SSF operation is not “0” but “1”, the Sout external output is performed at time t11. The signal observed at the terminal 115 has a logical value “0”, which is different from the expected logical value “1” when no failure occurs, so that it can be identified that the semiconductor device 10 is defective. However, in this case, when the signal latched in the SF / F 111 at the start of the SSF operation is not a logical value “1” but a logical value “0”, the same result is obtained. It is not possible to identify whether the defect has propagated to the included SF / F.
[0047]
Next, a signal to be supplied to the scan data input terminal 112 is provided, if necessary, during one cycle of the first clock signal, for example, a period in which the first clock signal has a logic value “1” and a period in which the logic value is “0” A description will be given of a modulation circuit for changing the voltage. FIG. 4 is a block diagram showing an example of the modulation circuit. Note that the modulation circuit 440 exists on an external board that covers, for example, the LSI tester and the semiconductor device 10 that is the circuit under test. Referring to FIG. 4, the modulation circuit 440 includes a terminal 441 for supplying a signal to be latched to the scan chain 102, a terminal 444 for supplying a signal to be latched to the scan chain 107, a modulation clock (hereinafter, MCLK) signal. 442, a terminal 443 for inputting a reset signal for initializing the modulation circuit 440, an F / F 445 for latching a signal supplied to the scan chain 102 in synchronization with the MCLK signal, and a signal MCLK for supplying to the scan chain 107. The MUX 447 includes an F / F 446 that latches in synchronization with a signal, an MUX 447 that synthesizes a modulation waveform, and a buffer 448 that adjusts a supply timing of a selection control signal supplied to a selection control input terminal 458 of the MUX 447. Signal output from the output end 459 of 47, is supplied to the scan data input terminal 112 of the semiconductor device 10 as a circuit under test. These terminals connect the D input terminal, CLK input terminal, RS input terminal, and Q output terminal of the F / F 445 to one selected input terminal of the terminals 441, 442, 443, and MUX 447, respectively. The D input terminal, the inverted CLK input terminal, the RS input terminal, and the Q output terminal of the F446 are connected to the terminals 444, 442, 443, and the 0 selection input terminal of the MUX 447, respectively. Are connected to the terminal 442 and the selection control input terminal 458 of the MUX 447, respectively.
[0048]
Next, the operation of the modulation circuit 440 thus configured will be described. FIG. 5 is an example of a schematic waveform diagram showing a signal waveform of a main node together with a first clock signal waveform for explaining this operation. 4 and 5, the MCLK signal (signal waveform 453) input to the terminal 442 changes earlier than the first clock signal (signal waveform 120), and the signal waveform 451 of the signal supplied to the terminal 441 and the terminal A signal waveform 420 serving as scan data to be supplied to the scan data input terminal 112 is synthesized from the signal waveform 452 of the signal supplied to 444. For example, at time t21, the signal supplied to the terminal 441 has the logical value “1”, is latched by the F / F 445 at the rise of the MCLK signal, and the selection control signal of the MUX 447 becomes the logical value “1”. While the MCLK signal is at the logical value “1”, the logical value “1” latched by the F / F 445 is supplied to the scan data input terminal 112. Next, at time t22, when the MCLK signal falls, at this time, the signal supplied to the terminal 444 has a logical value “0”, which is latched by the F / F 446, and the selection control signal of the MUX 447 is at a logical value. Since the value becomes “0”, the logic value “0” latched by the F / F 446 is supplied to the scan data input terminal 112 while the MCLK signal is at the logic value “0”. Similarly, at times t23, t24, t25, t26, t27 and t28, the signal supplied to the terminal 441 as the signal waveform 451 and the signal supplied to the terminal 444 as the signal waveform 452 are supplied to the scan data input terminal 112. The signal waveform 420 is synthesized.
[0049]
Next, a method for testing the semiconductor device 10 of the present embodiment using an LSI tester will be described. FIG. 6 is a diagram for explaining a test method of the semiconductor device 10, and is a block diagram schematically illustrating a connection relationship between the modulation circuit 440, the LSI tester 471, and the semiconductor device 10. Referring to FIG. 6, an input signal from the LSI tester 471 to the semiconductor device 10 to be a circuit to be inspected is supplied to the semiconductor device 10 via an input signal bundle 473 passing through the inside of the external board 474. A part of the signal lines 475 of the input signal line bundle 473 is connected to the modulation circuit 440 existing on the external board 474, the modulation signal line 476 from the modulation circuit 440 is connected to the semiconductor device 10, and the modulated signal is transmitted. The data is supplied to, for example, a scan data input terminal 112 of the semiconductor device 10. The output signal of the semiconductor device 10 is returned to the LSI tester 471 via the output signal line bundle 472. The LSI tester 471 observes the logical value of the signal of the output signal bundle 472 and compares it with the expected value to determine whether the semiconductor device 10 has a failure.
[0050]
As described above, the scan chain of the scan path test circuit included in the semiconductor device according to the present embodiment shifts the latch timing among a plurality of scan chains sharing one scan data input terminal and one shared scan chain. By applying modulation to the signal applied to the scan data input terminal, it is possible to freely set logical values for a plurality of different scan chains, thereby reducing the test time without impairing the controllability of the internal circuit section. The remarkable effect is obtained.
[0051]
Next, a second embodiment of the semiconductor device of the present invention will be described. FIG. 7 is a block diagram showing a configuration example of a scan chain of a scan path test circuit included in the second embodiment of the semiconductor device of the present invention, and FIG. 8 is a diagram corresponding to FIG. 3 in the first embodiment. 4 is a waveform diagram of main nodes for explaining the operation of the scan path test circuit 21. Signal waveforms 120, 420, 122, 421, 422, and 423 are represented by SC external input terminal 113 and scan data input terminal 112. , SF / F103, the SO output terminal of SF / F108, the scan mode external input terminal 401, and the signal waveform at the terminal 417 of the SC control circuit 402. Referring to FIG. 7, a semiconductor device 11 of the present embodiment includes an internal circuit for realizing a desired function (not shown), a scan path test circuit 21, a scan data input terminal 112, an SC external input terminal 113, and a scan mode external input. At least a terminal 401 and a Sout external output terminal 115 are provided. The scan path test circuit 21 includes a scan chain 102 as a first scan chain, a scan chain 107 as a second scan chain, a MUX 210 as code compression means, and an SC control circuit 402 as SC control means. I have. The present embodiment is different from the first embodiment only in that the scan path test circuit 21 is configured by replacing the EXOR 201, which is the code compression means, included in the scan path test circuit 20 with the MUX 210. This is the same as the embodiment, and the description of the same part is omitted. The MUX 210 connects the 0 selection input terminal, 1 selection input terminal, output terminal 219, and selection control input terminal 218 to the SO output terminal of SF / F106, the SO output terminal of SF / F111, the Sout external output terminal 115, and the SC output terminal. Each is connected to the external input terminal 113.
[0052]
With this configuration, in the present embodiment, the information on the scan chain 102 side and the logical value are output to the Sout external output terminal 115 during the period in which the first clock signal has the logical value “1” in synchronization with the first clock signal. Since the information on the scan chain 107 side appears alternately during the period of “0”, by observing the signal waveform output from the Sout external output terminal 115, it is possible to identify in which SF / F the influence of the fault has propagated. . For example, the state value of the internal circuit unit latched by the SF / F 106 at the start of the SSF operation can be confirmed by observing the logical value of the signal of the Sout external output terminal 115 at time t11 in FIG. Can be confirmed by observing the logical value of the signal of the Sout external output terminal 115 at time t31. As described above, in the present embodiment, it is possible to specify which fault has propagated to which SF / F from the test result.
[0053]
Next, a third embodiment of the semiconductor device of the present invention will be described. FIG. 9 is a block diagram showing a configuration example of a scan chain of a scan path test circuit included in the third embodiment of the semiconductor device of the present invention, and FIG. 10 is a diagram corresponding to FIG. 3 in the first embodiment. FIG. 4 is a waveform diagram of main nodes for explaining the operation of the scan path test circuit 22. Signal waveforms 120, 420, 122, and 621 include an SC external input terminal 113, a scan data input terminal 112, and an SF / F103. 5 shows signal waveforms at the SO output terminal of the SF / F 108 and the SO output terminal of the SF / F 108, respectively. Referring to FIG. 9, a semiconductor device 12 of the present embodiment includes an internal circuit for realizing a desired function (not shown), a scan path test circuit 22, a scan data input terminal 112, an SC external input terminal 113, and a scan mode external input. At least a terminal 401 and a Sout external output terminal 115 are provided. The scan path test circuit 22 includes a scan chain 102 as a first scan chain, a scan chain 602 as a second scan chain, an EXOR 201 as a code compression unit, and a negative edge type F / F 601.
[0054]
In the first and second embodiments, the SC control circuit 402 is used to set different values for the two scan chains 102 and 107 from one scan data input terminal 112. By adopting such a scan chain configuration, the same effects as in the first and second embodiments can be obtained. The difference between the scan chain configuration of the present embodiment and the scan chain configuration of the first and second embodiments is that a scan chain 602 composed of SF / Fs 108, 109, and 111 is arranged instead of the scan chain 107, and the scan is performed. The point is that the negative edge type F / F 601 is inserted before the chain 602, and the SC control circuit 402 is deleted. In the present embodiment, similarly to the first and second embodiments, the modulation of the signal supplied to the scan data input terminal 112 uses the modulation circuit 440 on the external board.
[0055]
Referring to the signal waveform of FIG. 10, the SSF operation by the scan chain configuration is performed by setting a signal to be set in the scan chain 602 at the falling edge of the first clock signal supplied to the SC external input terminal 113 in advance. The signal is latched in the F / F 601 from the terminal 112 and propagated to the SF / F 108 at the next rising of the first clock signal. The SF / F constituting the scan chain 107 of the first and second embodiments apparently latches the signal supplied to the scan data input terminal 112 at the time of the falling of the first clock signal. In the embodiment, the SF / F of the scan chain 602 latches the signal captured in the F / F 601 at the fall of the first clock at the rise of the first clock signal.
[0056]
In the example of the present embodiment described above, the number of SFs / Fs in the scan chain 602 is smaller than in the first and second embodiments. As in the first and second embodiments, when the number of SFs / Fs of the scan chain 602 is the same as the number of SFs / Fs of the scan chain 102, in the SSF operation, a desired signal is supplied to the F / F 601. The SSF time is lengthened by one cycle of the clock for setting. However, in a large-scale circuit, the number of SFs / Fs included in the scan chain is very large. Therefore, even if the SSF time for one clock cycle increases, the effect on the overall test time drastically shortening effect is hardly affected. Absent.
[0057]
Note that the present invention is not limited to the description of the above embodiment, and various changes can be made within the scope of the gist. For example, in the above embodiment, an example was described in which the number of SFs / Fs constituting each scan chain is three or four. However, it is needless to say that this number can be arbitrarily increased according to the scale of the internal circuit unit. Further, in the above embodiment, the example in which the modulation circuit for performing the modulation is provided on the external board has been described. However, there are many LSI testers having a built-in modulation function. No on-board modulation circuitry is required.
[0058]
The SF / F forming the scan chain has been described as an example in which the SSF operation is performed by one clock signal in the SSF operation mode. The invention is applicable.
[0059]
For example, a clocked LSSD (Level Sensitive ScanDesign) type SF / F shown in FIG. 17 is an example of an SF / F configured to perform an SSF operation using two clock signals in the SSF operation mode. Referring to FIG. 17, a clocked LSSD SF / F 70 includes D-type latches 71, 73, and 75, and a D input terminal and a CLK input terminal for inputting a data signal and a normal operation clock signal in a normal operation, respectively. A Q output terminal for outputting a data signal in a normal operation, an SI input terminal, an SC1 input terminal for inputting a scan data signal, a first scan clock signal, and a second scan clock signal in an SSF operation mode, respectively. And an SC2 input terminal, and an SO output terminal for outputting a scan data signal in the SSF operation mode. During normal operation, the first and second scan clock signals are fixed at a logical value “0”, and only the normal operation clock signal input to the CLK input terminal is used. Functions as F / F. In the SSF operation mode, the normal operation clock signal input to the CLK input terminal is fixed to the logical value “0”, and the SSF operation is realized by the first and second scan clock signals input to the SC1 input terminal and the SC2 input terminal. I do. In the SSF operation, during one cycle, first, a first scan clock signal is supplied to the SC1 input terminal, and the scan data signal input to the SI input terminal is latched by the D-type latch 73. Thereafter, the second clock signal is input to the SC2 input terminal, the data signal latched by the D-type latch 73 is latched by the D-type latch 75, and the signal is propagated to the next stage SF / F.
[0060]
Next, a configuration example of a scan chain using such a clocked LSSD type SF / F will be described. FIG. 18 is a block diagram showing a configuration example of a scan chain using a clocked LSSD type SF / F. The scan chain of the scan path test circuit included in the semiconductor device of the third embodiment shown in FIG. In this configuration, the SF / F to be used is replaced with the above-described clocked LSSD type SF / F. The test circuit 25 included in the semiconductor device 15 includes a scan chain 710 including clocked LSSD SF / Fs 706, 707, 708, and 709, a negative edge F / F 711, and a clocked LSSD SF / F 712. A scan chain 715 including 713 and 714, a negative edge F / F 716, a scan chain 720 including clocked LSSD SF / Fs 717, 718 and 719, and a negative edge F / F 721; It includes a scan chain 725 composed of clocked LSSD type SF / Fs 722, 723, and 724, and further supplies an SIN1 input terminal 702 for supplying a scan data signal to these scan chains, and first and second scan clock signals. SC1 to supply Input terminal 704, SC2 input terminal 705, CLK input terminal 703 for inputting a normal operation clock signal during normal operation, EXORs 726, 727, and 728 for compressing scan data, and scan data output terminal 729 for outputting a scan data signal. It has. As described above, by configuring the scan chain using the clocked LSSD type SF / F, unlike the third embodiment, four scan chains 710, 715, and 720 are connected from one SIN1 input terminal 702. , 725 can be supplied with independent data signals.
[0061]
Next, an outline of the SSF operation will be described. FIG. 19 is a schematic waveform diagram for explaining the SSF operation of the scan chain included in the test circuit 25 of FIG. Hereinafter, description will be made with reference to FIGS. In the SSF operation mode, the normal operation clock signal is fixed at the logical value “0”, and the first and second scan clock signals realize the SSF operation. The first SF / F 706 of the scan chain 710 latches the scan data signal (signal waveform 732) input from the SIN1 input terminal 702 at the rise of the first scan clock signal (signal waveform 730). On the other hand, before the scan chains 715, 720, and 725, the F / F 711 that latches the scan data signal at the falling edge of the first scan clock signal and the scan data signal at the rising edge of the second scan clock signal, respectively. The F / F 716 that connects the scan data signal at the falling edge of the second scan clock signal and the F / F 721 that latches the scan data signal at the fall of the second scan clock signal are connected. The signals (signal waveforms 735, 738, and 741) latched by each F / F are taken into each SF / F 712, 717, and 722 at the rise of the first scan clock signal in the next cycle. Accordingly, each scan chain can take in the data signals input to the SIN1 input terminal 702 at four points during one cycle, and the SSF operation for different scan data can be performed in each scan chain. The signal waveforms 733, 736, 739, and 742 in the waveform diagram of FIG. 19 are signal waveforms of portions corresponding to the outputs of the D-type latch 73 in FIG. 17 of the SF / Fs 706, 712, 717, and 722, respectively. , Signal waveforms 732, 737, 740, and 743 indicate signal waveforms corresponding to the output of the D-type latch 75.
[0062]
【The invention's effect】
As described above, the semiconductor device of the present invention has a remarkable effect that the SSF time can be reduced without lowering the controllability of the internal circuit portion, and the test time and test cost can be significantly reduced. .
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a scan chain of a scan path test circuit included in a first embodiment of a semiconductor device of the present invention.
FIG. 2 is a block diagram illustrating an example of a configuration of an SC control circuit in FIG. 1;
FIG. 3 is a waveform diagram of main nodes for describing an operation of the scan path test circuit of FIG. 1;
FIG. 4 is a block diagram illustrating an example of a modulation circuit.
FIG. 5 is an example of a schematic waveform diagram showing a signal waveform of a main node together with a first clock signal waveform for explaining an operation of the modulation circuit of FIG. 4;
FIG. 6 is a diagram illustrating a test method of the semiconductor device according to the first embodiment, and is a block diagram schematically illustrating a connection relationship between a modulation circuit, an LSI tester, and the semiconductor device.
FIG. 7 is a block diagram illustrating a configuration example of a scan chain of a scan path test circuit included in a second embodiment of the semiconductor device of the present invention.
8 is a waveform diagram of a main node for describing an operation of the scan path test circuit of FIG. 7;
FIG. 9 is a block diagram illustrating a configuration example of a scan chain of a scan path test circuit included in a third embodiment of the semiconductor device of the present invention.
FIG. 10 is a waveform diagram of main nodes for describing an operation of the scan path test circuit of FIG. 9;
FIG. 11 is a block diagram showing a circuit configuration example of a scan chain used in a conventional general scan method.
FIG. 12 is a waveform example of a main node of the scan chain of FIG. 11;
FIG. 13 is a block diagram illustrating a circuit configuration example of a scan chain disclosed in Japanese Patent Application Laid-Open No. 2000-258500.
FIG. 14 is a waveform example of a main node of the scan chain in FIG. 13;
15A and 15B are diagrams for explaining an example in which a test pattern for detecting a failure using a sample circuit and a sample failure is set by a scan chain, and FIG. 15A illustrates a conventional general scan chain. FIG. 4B shows a test pattern, and FIG. 4B shows a test pattern in the case of the scan chain disclosed in Japanese Patent Application Laid-Open No. 2000-258500.
FIG. 16 is a block diagram illustrating a specific configuration example of an SF / F that performs an SSF operation with one clock signal.
FIG. 17 is a block diagram illustrating a configuration example of a clocked LSSD SF / F.
FIG. 18 is a block diagram illustrating a configuration example of a scan chain using a clocked LSSD type SF / F.
FIG. 19 is a schematic waveform diagram for explaining an SSF operation of a scan chain included in the test circuit of FIG. 18;
[Explanation of symbols]
10, 11, 12, 15 semiconductor device
20,21,22,25 test circuit
50 SF / F
51, 210, 416, 447 MUX
53,412 F / F
70 Clocked LSSD SF / F
71, 73, 75 D-type latch
102, 107, 602 scan chain
710,715,720,725 scan chain
103, 104, 105, 106 SF / F
108, 109, 110, 111 SF / F
112 Scan data input terminal
113 SC external input terminal
115 Sout external output terminal
201, 726, 727, 728 EXOR
218, 418, 458 Selection control input terminal
219, 419, 459 Output end
401 scan mode external input terminal
402 SC control circuit
403 Delay adjustment circuit
405,407,417,441,442,443,444 terminal
410, 413, 415 AND gate
411,414 INV
440 Modulation circuit
445,446,711,716,721 F / F
448 buffer
471 LSI Tester
472 output signal bundle
473 input signal bundle
474 external board
475 signal line
601 F / F
702 SIN1 input terminal
703 CLK input terminal
704 SC1 input terminal
705 SC2 input terminal
706,707,708,709,712,713,714,717,718,719,722,723,724 SF / F
729 scan data output terminal

Claims (11)

A plurality of scan chains configured including a plurality of scan path test flip-flops, and a scan data input terminal for inputting scan path test data, at least,
The plurality of scan chains each include at least one of a first scan chain for inputting first scan data and a second scan chain for inputting second scan data different from the first scan data,
All the scan path test flip-flops included in the first scan chain latch their scan data at a first timing,
All the scan path test flip-flops included in the second scan chain latch respective scan data at a second timing different from the first timing,
Further, the scan data input terminal has at least one first scan data input terminal commonly connecting a scan data input terminal of the first scan chain and the second scan data input terminal. . A clock input terminal for inputting a first clock signal from outside;
The first timing is timing synchronized with a first edge of the first clock signal, and the second timing is timing synchronized with a second edge of the first clock signal in a direction opposite to the first edge. The semiconductor device according to claim 1, wherein A clock input terminal for externally inputting a first clock signal, a first clock signal and a mode signal for setting a scan shift operation mode, and a second signal delayed by a predetermined time from the first clock signal in the scan shift operation mode Scan clock control means for outputting a clock signal,
In the scan shift operation mode,
All the scan path test flip-flops included in the first scan chain latch scan data at a timing synchronized with the first clock signal,
2. The semiconductor device according to claim 1, wherein all the scan path test flip-flops included in the second scan chain latch scan data at a timing synchronized with a second clock signal. 4. The semiconductor device according to claim 1, further comprising a signal delay unit between the first scan chain and a clock input terminal for externally inputting the first clock signal. 5. A plurality of scan chains configured to include a plurality of scan path test flip-flops, and a scan data input terminal for inputting scan path test data,
The plurality of scan chains each include at least one of a first scan chain for inputting first scan data and a second scan chain for inputting second scan data different from the first scan data,
All the scan path test flip-flops included in the first scan chain and the second scan chain latch respective scan data at a first timing,
Further, the scan data input terminal is connected to a scan data input terminal of the first scan chain and has at least one first scan data input terminal connected to the second scan data input terminal via predetermined latch means. A semiconductor device comprising: A data input terminal and a data output terminal of the latch means are connected to the first scan data input terminal and a scan data input terminal of the second scan chain, respectively;
6. The semiconductor device according to claim 5, wherein said latch means latches an input signal at a timing different from a timing at which said scan path test flip-flop included in said second scan chain latches scan data. A clock input terminal for inputting a first clock signal is further provided, and all the scan path test flip-flops included in the first and second scan chains cause scan data to be applied to a first edge of the first clock signal. Latch at synchronized timing,
6. The semiconductor device according to claim 5, wherein said latch means latches an input signal at a timing synchronized with a second edge of said first clock signal in a direction opposite to said first edge. A clock input terminal for inputting a first clock signal, wherein all of the scan path test flip-flops included in the first and second scan chains latch scan data at a timing synchronized with the first clock signal; And
6. The semiconductor device according to claim 5, wherein said latch means latches an input signal at a timing synchronized with an inverted signal of said first clock signal. A scan-out external output terminal for outputting a signal representing a logic state of a predetermined node of the internal circuit to the outside, and further comprising a data compression unit,
Connecting the scan data output terminals of all the scan chains connected to the first scan data input terminal to the input terminals of the data compression means;
9. The semiconductor device according to claim 1, wherein an output terminal of said data compression means is connected to said scan-out external output terminal. 10. The semiconductor device according to claim 9, wherein said data compression means comprises an exclusive OR circuit. 10. The semiconductor device according to claim 9, wherein said data compression means comprises a multiplexer.

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