JP6221433B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit.

  In a scan test of a semiconductor integrated circuit, a clock having one frequency is often used as a scan clock used for a scan shift operation. Scan clocks are increasing in speed to reduce test time.

  In addition, there is a technique for supplying a plurality of scan clocks having different phases to scan flip-flops connected in series (flip-flops with a scan function (hereinafter referred to as scan FFs)) in order to suppress malfunction due to skew.

Japanese Patent Laid-Open No. 3-46821 Japanese Patent Laid-Open No. 7-84011 JP 2006-3317 A JP 2011-59028 A

  When the frequency of the scan clock is increased to shorten the scan test time, the power consumption in the scan FF increases. Accordingly, there is a concern that the operation of the semiconductor integrated circuit becomes unstable due to heat generation of the semiconductor integrated circuit, or the semiconductor integrated circuit is damaged beyond the rating.

  According to one aspect of the invention, frequency-divided clock generation that receives a scan clock, performs frequency division and phase adjustment of the scan clock, and generates frequency-divided scan clocks of N (≧ 2) types of frequency division numbers N or less N scan chains that include the same number of scan flip-flops, and that receive serially input data at different timings using the N types of frequency-divided scan clocks, and perform N-parallel shift operations, There is provided a semiconductor integrated circuit having a selection circuit for selecting outputs of N scan chains one by one and outputting them as serial data.

  According to the disclosed semiconductor integrated circuit, an increase in power consumption can be suppressed.

1 is a diagram illustrating an example of a semiconductor integrated circuit according to a first embodiment; It is a figure which shows an example of the semiconductor integrated circuit of 2nd Embodiment. 6 is a timing chart illustrating an operation of an example of a semiconductor integrated circuit according to a second embodiment during a scan test in a shift mode. It is a figure which shows an example of the semiconductor integrated circuit which formed one scan chain. 6 is a timing chart showing an example of an operation during a scan test in a shift mode of a semiconductor integrated circuit having one scan chain. It is a figure which shows an example of the semiconductor integrated circuit of 3rd Embodiment. FIG. 10 is a timing chart illustrating an operation of an example of a semiconductor integrated circuit according to a third embodiment during a scan test in a shift mode (part 1); FIG. 10 is a timing chart illustrating an operation of an example of a semiconductor integrated circuit according to the third embodiment during a scan test in a shift mode (part 2); It is a figure which shows an example of the semiconductor integrated circuit of 4th Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor integrated circuit according to the first embodiment.

  The semiconductor integrated circuit 1 includes two scan chains 5 including a combinational circuit 2, a divided clock generation unit 3, and scan FFs 4-1, 4-2, 4-3, 4-4, 4-5 and 4-6. 1,5-2.

  The frequency-divided clock generation unit 3 receives the scan clock SCK input to the semiconductor integrated circuit 1 via the terminal P4. Then, the frequency-divided clock generation unit 3 performs frequency division and phase adjustment of the scan clock SCK, and generates two different types of frequency-divided scan clocks SCK1 and SCK2.

  For example, the divided scan clock SCK2 is obtained by dividing the scan clock SCK by 2, and the divided scan clock SCK1 is obtained by dividing the scan clock SCK by 2 and performing phase adjustment.

  Each of the scan chains 5-1 and 5-2 includes the same number of scan FFs. In the example of FIG. 1, the scan chain 5-1 includes scan FFs 4-1, 4-3, and 4-5, and the scan chain 5-2 includes scan FFs 4-2, 4-4, and 4-6.

  In the present embodiment, the scan FFs 4-1 to 4-6 are arranged in a line, and every other output chain Q and scan-in terminal SIN are connected to form two scan chains 5- 1,5-2 are formed. Note that the scan-in terminals SIN of the scan FFs 4-1 and 4-2 in the forefront stage of the scan chains 5-1 and 5-2 are serial numbers that are test patterns input to the semiconductor integrated circuit 1 via the terminal P2. Data SDI is input. The output terminals Q of the scan FFs 4-1 to 4-5 are also connected to the combinational circuit 2, and the outputs of the scan FFs 4-5 and 4-6 at the last stage of the scan chains 5-1 and 5-2. The terminal Q is connected to the selection circuit 6.

  The scan chains 5-1 and 5-2 take in the serial data SDI with the above-described two types of the divided scan clocks SCK 1 and SCK 2 at different timings, and perform the shift operation by parallelizing them. The frequency-divided scan clock SCK1 is input to the clock terminals CK of the scan FFs 4-1, 4-3, and 4-5 of the scan chain 5-1. The frequency-divided scan clock SCK2 is input to the scan FFs 4-2, 4-4, and 4-6 of the scan chain 5-2.

  Data used in the normal operation mode is input from the terminal P1 to the data input terminal D of the scan FF4-1. The data input terminals D of the scan FFs 4-2 to 4-6 are connected to the combinational circuit 2, and data from the combinational circuit 2 is input thereto. A shift enable signal indicating whether or not to enable the shift operation is input from the terminal P3 to the shift enable terminals S of the scan FFs 4-1 to 4-6. When the scan shift operation is valid, data input to the scan-in terminal SIN is selected, and data input to the data input terminal D is not selected.

  The selection circuit 6 selects the outputs of the two scan chains 5-1 and 5-2 one by one and outputs them as serial data SDO via the terminal P5. In the example of the present embodiment, the selection circuit 6 uses the divided scan clock SCK2 as the selection signal.

Hereinafter, an example of the shift operation during the scan test of the semiconductor integrated circuit 1 according to the first embodiment will be described.
During the scan test shift operation, the shift enable signal becomes valid, and a selector (not shown) in the scan FFs 4-1 to 4-6 selects to capture data input to the scan-in terminal SIN.

  When the scan clock SCK is input from the terminal P4, the frequency-divided clock generation unit 3 performs frequency division and phase adjustment of the scan clock SCK, and generates two different frequency-divided scan clocks SCK1 and SCK2. For example, the frequency-divided clock generation unit 3 divides the scan clock SCK into two and adjusts the phase by dividing it by two and delaying it. In the example of the semiconductor integrated circuit 1 according to the present embodiment, the phase of the frequency-divided scan clock SCK1 is adjusted so that the scan FF4-1 can capture odd-numbered data d1, d3, d5. The frequency-divided scan clock SCK2 is phase-adjusted so that the scan FF4-2 can take in even-numbered data d2, d4... (An example of the phase adjustment method will be described later).

  Then, in synchronization with the rise (or fall) of the divided scan clock SCK1, the foremost scan FF4-1 of the scan chain 5-1 receives the odd-numbered data d1, d3, d5. In order. Then, these data are shifted to the scan FFs 4-3 and 4-5 in the subsequent stage of the scan chain 5-1, in synchronization with the rise (or fall) of the next divided scan clock SCK1.

  On the other hand, in synchronization with the rise (or fall) of the divided scan clock SCK2, the scan FF 4-2 at the forefront stage of the scan chain 5-2 sequentially outputs even-numbered data d2, d4,. take in. Then, these data are shifted to the scan FFs 4-4 and 4-6 in the subsequent stage of the scan chain 5-2 in synchronization with the rising (or falling) of the next divided scan clock SCK2.

  The selection circuit 6 receives the outputs of the scan FFs 4-5 and 4-6. Then, the selection circuit 6 alternately selects the outputs of the scan FFs 4-5 and 4-6 in synchronization with the rising (or falling) of the divided scan clock SCK2 which is the selection signal, and outputs the terminal P5 as serial data SDO. Output via.

  According to the semiconductor integrated circuit 1 as described above, even if a high-speed scan clock SCK is input, it is divided / phase-adjusted, and two types of divided scan clocks SCK 1 and SCK 2 are generated. Then, the semiconductor integrated circuit 1 parallelizes the serial data SDI with the clock, shifts it with the two scan chains 5-1 and 5-2, and returns it to serial after the shift operation. Thereby, power consumption can be reduced without degrading performance.

  Therefore, even if the scan clock during the scan shift operation is speeded up, an increase in the chip temperature can be suppressed and a stable yield can be expected. Further, since the scan clock can be speeded up while suppressing an increase in power consumption, the test time is shortened and the test cost is reduced.

  Further, the frequency-divided clock generation unit 3 generates the frequency-divided clocks SCK1 and SCK2 adjusted as described above, and alternately selects the outputs of the scan FFs 4-5 and 4-6 to the selection circuit 6 according to the selection signal. Let As a result, the same expected scan-out value as when the scan shift operation is performed with one scan chain is obtained.

  Further, when the scan FFs 4-1 to 4-6 arranged in a row are connected every other line to form two scan chains, a scan shift operation is performed with one scan chain. The same expected scan-out value can be easily obtained. Also, the scan FFs can be arranged in the same arrangement as in the case of performing the scan shift operation with one scan chain, and can be easily parallelized only by changing the connection destination of the wiring.

In the above description, the number of scan FFs included in the scan chains 5-1 and 5-2 is three, but may be two or four or more.
In the above description, the case where the scan clock is divided / phase-adjusted to generate two types of divided scan clocks, the serial data is parallelized by the two clocks, and shifted by two scan chains has been described. However, it is not limited to this. The scan clock is divided / phase-adjusted to generate N (≧ 3) types of divided scan clocks with a frequency division number of N or less, and serial data is N-paralleled by that clock and shifted by N scan chains. You may make it do.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor integrated circuit according to the second embodiment. The same elements as those in the first embodiment shown in FIG.

Similarly to the semiconductor integrated circuit 1 shown in FIG. 1, the semiconductor integrated circuit 1a of the second embodiment also has two scan chains 5-1 and 5-2.
Further, the semiconductor integrated circuit 1a according to the second embodiment has a frequency-divided clock generation unit 3a as described below.

The frequency-divided clock generation unit 3a includes frequency dividers 10 and 11, an inverter circuit 12, and selectors 13 and 14.
The frequency divider 10 divides the scan clock SCK input to the semiconductor integrated circuit 1a via the terminal P4 by two. The frequency divider 11 divides the scan clock SCK, which is input to the semiconductor integrated circuit 1a via the terminal P4 and whose logic level is inverted by the inverter circuit 12, by two. Thus, in the present embodiment, the phase adjustment is performed by the inverter circuit 12.

  The selector 13 selects either the scan clock SCK or the output of the frequency divider 10 according to the scan mode signal input from the terminal P6, and supplies it to the scan FFs 4-2, 4-4, and 4-6. Output as a selection signal supplied to the selection circuit 6.

  The selector 14 selects either the scan clock SCK or the output of the frequency divider 11 according to the scan mode signal input from the terminal P6, and supplies it to the scan FFs 4-1, 4-3, and 4-5. Output as a clock.

  The scan mode signal is a signal for instructing whether to enable or disable the frequency division and phase adjustment. When the scan mode signal instructs invalidation of the frequency division and phase adjustment, a clock input from the terminal P5 is output from the frequency-divided clock generation unit 3a instead of the frequency-divided scan clock. For example, this clock is used when not in the scan test shift operation.

Hereinafter, an example of the operation of the semiconductor integrated circuit 1a of the second embodiment will be described.
FIG. 3 is a timing chart showing an operation of an example of the semiconductor integrated circuit according to the second embodiment during the scan test in the shift mode.

  In FIG. 3, in addition to the scan clock SCK and serial data SDI input to the semiconductor integrated circuit 1a via the terminal P2, examples of input clocks (divided scan clocks SCK1 and SCK2) of the scan FFs 4-1 to 4-6. The situation is shown. Further, an example of outputs of the scan FFs 4-1 to 4-6, a selection signal (frequency-divided scan clock SCK2), two inputs (input A and input B) of the selection circuit 6, and an output of the selection circuit 6 is shown. ing. The input A of the selection circuit 6 is an output of the scan FF 4-5, and the input B of the selection circuit 6 is an output of the scan FF 4-6.

The serial data SDI is input to the semiconductor integrated circuit 1a in the order of data d1, d2, d3, d4, d5, d6... In synchronization with the scan clock SCK.
At timing t1, the input clock (frequency-divided scan clock SCK1) of the scan FF4-1 rises to the H (High) level. In synchronization with this rise timing, the data d1 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF4-1 at that time is taken into the scan FF4-1 and output.

  On the other hand, at timing t2, the input clock (frequency-divided scan clock SCK2) of the scan FF4-2 rises to the H level. In synchronization with this rise timing, the data d2 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF4-2 at that time is taken into the scan FF4-2 and output.

  At timing t3, the input clock (frequency-divided scan clock SCK1) of the scan FF 4-3 rises to the H level. In synchronization with this rise timing, the data d1 that is the output of the scan FF4-1 is taken into the scan FF4-3 and output.

  At timing t3, the input clock (frequency-divided scan clock SCK1) of the scan FF4-1 also rises to the H level. Thereby, the data d3 supplied to the scan-in terminal SIN of the scan FF4-1 at that time is taken into the scan FF4-1 and output.

  At timing t4, the input clock (frequency-divided scan clock SCK2) of the scan FF 4-4 rises to the H level. In synchronization with this rise timing, the data d2 that is the output of the scan FF4-2 is taken into the scan FF4-4 and output.

  At timing t4, the input clock (frequency-divided scan clock SCK2) of the scan FF4-2 also rises to the H level. Thereby, the data d4 supplied to the scan-in terminal SIN of the scan FF4-2 at that time is taken into the scan FF4-2 and output.

  At timing t5, the input clock (frequency-divided scan clock SCK1) of the scan FF 4-5 rises to the H level. In synchronization with this rise timing, the data d1 that is the output of the scan FF 4-3 is taken into the scan FF 4-5 and output. Thereby, the input A of the selection circuit 6 becomes the data d1. The selection circuit 6 selects and outputs the input A, that is, the data d1 at the timing t6 when the selection signal (frequency-divided scan clock SCK2) becomes the L (Low) level.

  Further, the scan FF 4-1 captures and outputs the data d 5 supplied to the scan-in terminal SIN at the timing t 5. The scan FF 4-3 captures and outputs the data d3 output from the scan FF 4-1 at timing t5.

  At timing t7, the input clock (frequency-divided scan clock SCK2) of the scan FF 4-6 rises to the H level. In synchronization with this rising timing, the data d2 that is the output of the scan FF 4-4 is taken into the scan FF 4-6 and output. As a result, the input B of the selection circuit 6 becomes data d2. At timing t7, the selection signal (frequency-divided scan clock SCK2) is at the H level, and the selection circuit 6 selects and outputs the input B, that is, the data d2.

  Further, the scan FF4-2 takes in and outputs the data d6 supplied to the scan-in terminal SIN at the timing t7. The scan FF 4-4 takes in and outputs the data d4 output from the scan FF 4-2 at the timing t7.

Thereafter, the same scan shift operation is performed, and data d3, d4, d5, d6.
By using the frequency-divided clock generator 3a as described above, the semiconductor integrated circuit 1a can obtain the same effects as those of the semiconductor integrated circuit 1 described in the first embodiment.

Next, as a comparative example, an example of a semiconductor integrated circuit in which scan FFs 4-1 to 4-4 are connected in series to form one scan chain is shown.
(Comparative example)
FIG. 4 is a diagram illustrating an example of a semiconductor integrated circuit in which one scan chain is formed. The same elements as those of the semiconductor integrated circuits 1 and 1a shown in FIGS.

  In the semiconductor integrated circuit 1b, the scan-in terminal SIN of the scan FF4-1 is connected to a terminal P2 to which serial data is input. The scan-in terminals SIN of the scan FFs 4-2 to 4-6 are connected to the output terminals Q of the scan FFs 4-1 to 4-5 in the previous stage, so that one scan chain is formed. Further, the same scan clock is input from the terminal P4 to the clock terminals CK of the scan FFs 4-1 to 4-6 without being divided.

Hereinafter, an example of the operation at the time of the scan test shift operation of the semiconductor integrated circuit 1b will be described.
FIG. 5 is a timing chart showing an example of an operation during a scan test in a shift mode of a semiconductor integrated circuit having one scan chain.

  FIG. 5 shows an example of an input clock (scan clock SCK) of the scan FFs 4-1 to 4-6 in addition to the scan clock SCK and serial data SDI input to the semiconductor integrated circuit 1b via the terminal P2. ing. Further, an example of the output of the scan FFs 4-1 to 4-6 is shown.

The serial data SDI is input to the semiconductor integrated circuit 1b in the order of data d1, d2, d3, d4, d5, d6... In synchronization with the scan clock SCK.
At timing t10, the input clock (scan clock SCK) of the scan FF4-1 rises to the H level. In synchronization with this rise timing, the data d1 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF4-1 at that time is taken into the scan FF4-1 and output.

  In synchronization with the rising of the input clock (scan clock SCK) of the scan FF 4-2 to the H level at the timing t 11, the data d 1 that is the output of the scan FF 4-1 is taken into the scan FF 4-2 and output. The

  Thereafter, the same scan shift operation is performed, and data d1, d2, d3, d4, d5, d6... Are sequentially output from the last scan FF 4-6 in synchronization with the rising edge of the scan clock SCK from timing t12. And output from the terminal P5.

  In such a semiconductor integrated circuit 1b, the scan FF4-1 to FF4-6 operate with the same scan clock SCK. Therefore, when the frequency of the scan clock SCK increases, the power consumption increases. On the other hand, in the semiconductor integrated circuit 1a of the second embodiment, as shown in FIG. 3, the scan FFs 4-1 to 4-6 are divided by the divided scan clocks SCK1 and SCK2 obtained by dividing the scan clock SCK by two. Therefore, an increase in power consumption can be suppressed.

  In the operation of the semiconductor integrated circuit 1b shown in FIG. 5, the scan clock from when the data d1 is taken into the scan FF4-1 at the foremost stage of the scan chain until it is output from the terminal P5 (t10 to t12). It takes 5 SCK cycles.

  On the other hand, in the operation of the semiconductor integrated circuit 1a shown in FIG. 3, the data d1 is taken into the scan FF4-1 at the foremost stage of the scan chain 5-1 until it is output from the terminal P5 (t1 to t6). ), 4.5 scan clock cycles are required.

  In other words, even if the scan clock supplied to the scan FFs 4-1 to 4-6 is divided by 2, the scan chain is parallelized, and the data is shifted at the timing shown in FIG. The test speed of the scan test in the mode can also be increased.

(Third embodiment)
The semiconductor integrated circuit according to the third embodiment generates four types of divided scan clocks by dividing / phase-adjusting the scan clock, serializing the serial data into four in parallel with the clocks, and shifting with four scan chains. To do.

  FIG. 6 is a diagram illustrating an example of a semiconductor integrated circuit according to the third embodiment. Elements similar to those of the semiconductor integrated circuit 1a of the second embodiment shown in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.

  In the semiconductor integrated circuit 1c according to the third embodiment, the frequency-divided clock generation unit 3c divides the scan clock SCK by 4 / phase and generates four different frequency-divided scan clocks.

The frequency-divided clock generation unit 3c includes frequency-divided clock generation counters 20, 21, inverter circuits 22, 23, 24, and selectors 25, 26, 27, 28.
The divide-by-4 clock generation counter 20 divides the scan clock SCK input to the semiconductor integrated circuit 1c via the terminal P4 by four. The divide-by-4 clock generation counter 20 is, for example, a 2-bit counter including two FFs. The initial value is “00”. The divide-by-4 clock generation counter 20 supplies a 2-bit count value cnt to the selection circuit 6c as a selection signal.

  The divide-by-4 clock generation counter 21 divides the scan clock SCK, which is input to the semiconductor integrated circuit 1c via the terminal P4 and whose logic level is inverted by the inverter circuit 22, by four. The divide-by-4 clock generation counter 21 is also a 2-bit counter including two FFs, for example, and its initial value is “00”.

  The selector 25 selects either the scan clock SCK or the output of the divide-by-4 clock generation counter 20 according to the scan mode signal input from the terminal P6, and supplies it to the scan FFs 4-2 and 4-6. Output as a clock.

  The selector 26 selects either the scan clock SCK or the output of the divide-by-4 clock generation counter 20 whose logic level is inverted by the inverter circuit 23 in accordance with the scan mode signal, and scan FFs 4-4, 4-8. Output as a clock to be supplied.

  The selector 27 selects either the scan clock SCK or the output of the divide-by-4 clock generation counter 21 whose logic level is inverted by the inverter circuit 24 in accordance with the scan mode signal, and scans FF4-1, 4-5. Output as a clock to be supplied.

  The selector 28 selects either the scan clock SCK or the output of the divide-by-4 clock generation counter 21 according to the scan mode signal and outputs it as a clock to be supplied to the scan FFs 4-3 and 4-7.

The semiconductor integrated circuit 1c according to the third embodiment includes eight scan FFs 4-1, 4-2, 4-3, 4-4, 4-5, 4-6, 4-7 and 4-8. Have.
In the present embodiment, the scan FFs 4-1 to 4-8 are arranged in a line, and include two scan FFs by connecting the output terminal Q and the scan-in terminal SIN every third. Four scan chains are formed. Note that serial data SDI, which is a test pattern input to the semiconductor integrated circuit 1 via the terminal P2, is input to the scan-in terminals SIN of the scan FFs 4-1 to 4-4 in the forefront stage of each scan chain. The output terminals Q of the scan FFs 4-1 to 4-7 are connected to the combination circuit 2, and the output terminals of the scan FFs 4-5 to FF 4-8 at the last stage of the four scan chains are connected to the selection circuit 6c. It is connected.

The four scan chains take in the serial data SDI at different timings using the above-described four types of divided scan clocks, and perform a shift operation by parallelizing the serial data SDI.
Data used in the normal operation mode is input from the terminal P1 to the data input terminal D of the scan FF4-1. The data input terminals D of the scan FFs 4-2 to 4-8 are connected to the combinational circuit 2, and data from the combinational circuit 2 is input thereto. A shift enable signal indicating whether or not to enable the shift operation is input from the terminal P3 to the shift enable terminals S of the scan flip-flops 4-1 to 4-8.

  The selection circuit 6c selects the outputs of the four scan chains one by one and outputs them as serial data via the terminal P5. In the example of the present embodiment, the selection circuit 6c uses the count value cnt of the divided-by-4 clock generation counter 20 as the selection signal. In the following description, it is assumed that when the count value cnt is “00”, the output of the scan FF 4-8 is selected, and when it is “01”, the output of the scan FF 4-5 is selected. When the count value cnt is “10”, the output of the scan FF 4-6 is selected. When the count value cnt is “11”, the output of the scan FF 4-7 is selected.

Hereinafter, an example of the operation of the semiconductor integrated circuit 1c according to the third embodiment will be described.
7 and 8 are timing charts showing an operation of an example of the semiconductor integrated circuit according to the third embodiment at the time of the scan test in the shift mode.

  7 and 8, the scan clock SCK, the serial data SDI, the input clocks of the scan FFs 4-1 to 4-8, the outputs of the scan FFs 4-1 to 4-8, the selection signal, and the four inputs (inputs) of the selection circuit 6c A to D), an example of the output of the selection circuit 6c is shown. Note that the input A of the selection circuit 6c is the output of the scan FF 4-5, and the input B of the selection circuit 6c is the output of the scan FF 4-6. An input C of the selection circuit 6c is an output of the scan FF 4-7, and an input D of the selection circuit 6c is an output of the scan FF 4-8.

The serial data SDI is input to the semiconductor integrated circuit 1c in the order of data d1, d2, d3, d4, d5, d6... In synchronization with the scan clock SCK.
First, in synchronization with the rising timing of the input clock of the scan FF4-1 at timing t20, the data d1 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF4-1 is taken into the scan FF4-1. Is output.

  Further, in synchronization with the rising timing of the input clock of the scan FF4-2 at the timing t21, the serial data SDI data d2 supplied to the scan-in terminal SIN of the scan FF4-2 is taken into the scan FF4-2. Is output.

  Further, in synchronization with the rising timing of the input clock of the scan FF 4-3 at timing t22, the data d3 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF 4-3 is taken into the scan FF 4-3. Is output.

  Further, in synchronization with the rising timing of the input clock of the scan FF 4-4 at timing t23, the data d4 of the serial data SDI supplied to the scan-in terminal SIN of the scan FF 4-4 is taken into the scan FF 4-4. Is output.

  At timing t24, the input clock of the scan FF 4-5 rises to the H level. In synchronization with this rising timing, the data d1 that is the output of the scan FF4-1 is taken into the scan FF4-5 and output.

  At timing t24, the input clock of the scan FF4-1 also rises to the H level. As a result, the data d5 supplied to the scan-in terminal SIN of the scan FF4-1 is taken into the scan FF4-1 and output.

  Further, as shown in FIG. 8, when the output of the scan FF 4-5 becomes the data d1, the input A of the selection circuit 6c becomes the data d1. When the selection signal (count value cnt) becomes “01” in synchronization with the rising timing of the scan clock SCK at the timing t25, the selection circuit 6c selects and outputs the input A. Thereby, data d1 is output.

  Thereafter, at timing t26, the input clock of the scan FF 4-6 rises to the H level. In synchronization with this rising timing, the data d2 that is the output of the scan FF4-2 is taken into the scan FF4-6 and output.

  At timing t26, as shown in FIG. 7, the input clock of the scan FF4-2 also rises to the H level. As a result, the data d6 supplied to the scan-in terminal SIN of the scan FF4-2 is taken into the scan FF4-2 and output.

  Further, as shown in FIG. 8, when the output of the scan FF 4-6 becomes data d2, the input B of the selection circuit 6c becomes data d2. When the selection signal (count value cnt) becomes “10” in synchronization with the rising timing of the scan clock SCK at the timing t26, the selection circuit 6c selects and outputs the input B. Thereby, data d2 is output.

  Thereafter, at timing t27, the input clock of the scan FF 4-7 rises to the H level. In synchronization with this rise timing, the data d3, which is the output of the scan FF 4-3, is taken into the scan FF 4-7 and output.

  At timing t27, as shown in FIG. 7, the input clock of the scan FF 4-3 also rises to the H level. Thereby, the data d7 supplied to the scan-in terminal SIN of the scan FF 4-3 is taken into the scan FF 4-3 and output.

  Further, as shown in FIG. 8, when the output of the scan FF 4-7 becomes the data d3, the input C of the selection circuit 6c becomes the data d3. When the selection signal (count value cnt) becomes “11” in synchronization with the rising timing of the scan clock SCK at the timing t28, the selection circuit 6c selects and outputs the input C. Thereby, data d3 is output.

  Thereafter, at timing t29, the input clock of the scan FF 4-8 rises to the H level. In synchronization with this rise timing, the data d4 that is the output of the scan FF 4-4 is taken into the scan FF 4-8 and output.

  At timing t29, as shown in FIG. 7, the input clock of the scan FF 4-4 also rises to the H level. As a result, the data d8 supplied to the scan-in terminal SIN of the scan FF 4-4 is taken into the scan FF 4-4 and output.

  Further, as shown in FIG. 8, when the output of the scan FF 4-8 becomes data d4, the input D of the selection circuit 6c becomes data d4. When the selection signal (count value cnt) becomes “00” in synchronization with the rising timing of the scan clock SCK at timing t29, the selection circuit 6c selects and outputs the input D. Thereby, data d4 is output.

The scan shift operation is similarly performed on the data d5 to d8, and the data is output from the selection circuit 6c serially.
As described above, the same effect as the semiconductor integrated circuit 1 described in the first embodiment can be obtained even in the semiconductor integrated circuit 1c in which serial data is scan-shifted in four parallel by the four scan chains. Note that power consumption can be further reduced by setting the frequency division to 4 and further reducing the frequency of the scan clock.

(Fourth embodiment)
In the above description, the semiconductor integrated circuit that inputs serial data from one terminal, performs a scan test, and outputs the resulting serial data from one terminal has been described, but the present invention is not limited to this. Serial data may be input from a plurality of terminals, a scan test may be performed, and the resulting serial data may be output from the plurality of terminals.

A semiconductor integrated circuit that inputs serial data from two terminals and outputs two scan results from the two terminals will be described below.
FIG. 9 is a diagram illustrating an example of a semiconductor integrated circuit according to the fourth embodiment.

Elements similar to those of the semiconductor integrated circuit 1a of the second embodiment shown in FIG. 2 are denoted by the same reference numerals.
The semiconductor integrated circuit 1d according to the fourth embodiment includes two scan chains 5a-1 and 5a-2 that perform a scan shift operation by parallelizing serial data input from the terminal P2a. Further, the semiconductor integrated circuit 1d has two scan chains 5b-1 and 5b-2 that perform a scan shift operation by parallelizing two serial data input from the terminal P2b.

  The scan chain 5a-1 has scan FFs 4a-1, 4a-3, 4a-5, and the scan chain 5a-2 has scan FFs 4a-2, 4a-4, 4a-6. The scan chain 5b-1 includes scan FFs 4b-1, 4b-3, and 4b-5, and the scan chain 5b-2 includes scan FFs 4b-2, 4b-4, and 4b-6.

  The scan FFs 4a-1 to 4a-6 are arranged in a line, and are connected every other line to form two scan chains 5a-1 and 5a-2. The scan FFs 4b-1 to 4b-6 are also arranged in a line and are connected every other line to form two scan chains 5b-1 and 5b-2.

  In FIG. 9, the data input terminal D and the shift enable terminal S of the scan FFs 4a-1 to 4a-6 and 4b-1 to 4b-6 are not shown. Also, the combinational circuit 2 shown in FIG. 2 is not shown in FIG.

  At the time of the scan test, the clock terminals CK and the selection circuits 6a and 6b of the scan FFs 4a-1, 4b-1, 4a-3, 4b-3, 4a-5, and 4b-5 are connected to the selector 14 of the divided clock generation unit 3a. The selected divided clock is supplied. Further, the divided clock selected by the selector 13 of the divided clock generator 3a is supplied to the clock terminals CK of the scan FFs 4a-2, 4b-2, 4a-4, 4b-4, 4a-6, and 4b-6. Is done.

  Thereby, the serial data input from the terminal P2a is parallelized by the scan chains 5a-1 and 5a-2, the scan shift operation is performed, and the scan shift result is returned to the serial data by the selection circuit 6a. Output from P5a. The serial data input from the terminal P2b is parallelized by the scan chains 5b-1 and 5b-2, a scan shift operation is performed, and the scan shift result is returned to the serial data by the selection circuit 6b. Is output from.

  Also in the semiconductor integrated circuit 1d of the fourth embodiment, the same effect as that of the semiconductor integrated circuit 1 described in the first embodiment can be obtained. As the number of scan FFs increases as shown in FIG. 9, the effect of reducing power consumption by operating with a divided scan clock increases.

  As described above, one aspect of the semiconductor integrated circuit of the present invention has been described based on the embodiment, but these are only examples, and the present invention is not limited to the above description.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Combination circuit 3 Divided clock generation part 4-1 to 4-6 Scan FF
5-1 and 5-2 scan chain 6 selection circuit CK clock terminal d1 to d5 data D data input terminal P1 to P5 terminal Q output terminal S shift enable terminal SCK scan clock SCK1 and SCK2 divided scan clock SDI and SDO serial data SIN Scan-in terminal

Claims (3)

A frequency-divided clock generating unit that receives the scan clock, divides and adjusts the phase of the scan clock, and generates frequency-divided scan clocks of N (≧ 2) types of frequency-divided numbers N or less;
Each containing the same number of scan flip-flops, the data that is serially inputted, the uptake at different timings in N types of the divided scan clock, a scan chain of the N to perform shift operation in N parallel,
A selection circuit for selecting the outputs of the N scan chains one by one and outputting them as serial data;
Have
The scan flip-flops are arranged in a row, and the N scan chains are formed by connecting every N-1 units.
Semiconductor integrated circuit, wherein a call. The frequency-divided clock generation unit includes the N types of the N types of N scan flip-flops that are phase-adjusted so that the N scan flip-flops in the forefront stage of the N scan chains can sequentially receive N pieces of data that are serially input. The semiconductor integrated circuit according to claim 1, wherein the divided scan clock is generated. The frequency-divided clock generation unit generates a selection signal that causes the selection circuit to sequentially select and output the outputs of the N scan flip-flops at the last stage of the N scan chains, and supplies the selection signal to the selection circuit. the semiconductor integrated circuit according to claim 1 or 2, characterized in that.

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