KR102028922B1 - Data processing method of semiconductor chip and semiconductor chip therefor - Google Patents

Abstract

A semiconductor chip includes a separator which separates input data into first type data and second type data; a memory which receives the second type data of K bytes from the separator, outputs data of (K-M) bytes among the received second type data of K bytes, and stores data of M bytes among the second type data of the K bytes; and a clock signal generator which generates a first clock signal. The memory receives the second type data of K bytes by using a second clock signal input to the semiconductor chip, and outputs data of (K-M) bytes among the second type data of K bytes by using the first clock signal. It is possible to prevent the jitter and noise of a clock from propagating to the next semiconductor chip.

Description

DATA PROCESSING METHOD OF SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP THEREFOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing method of a semiconductor chip and a semiconductor chip, and more particularly, to a data processing method and a semiconductor chip of a semiconductor chip having a different clock for data input and a clock for data output.

1 illustrates a configuration of semiconductor chips connected in a daisy chain structure. 2 is an explanatory diagram of a clock in which an error due to noise occurs.

In a semiconductor chip connected in a daisy chain structure as shown in FIG. 1, when jitter or noise occurs in a clock, the jitter or noise is accumulated and propagated to a semiconductor chip connected to a later stage. The duty cycle is distorted, and if the distortion is severe, the clock disappears.

The jitter and noise of the clock propagate to the semiconductor chip of the connected rear end and finally to the semiconductor chip of the final stage.

In a semiconductor chip connected in such a daisy chain structure, there is a need to prevent jitter and noise of a clock from propagating to a semiconductor chip of a later stage.

1. Korean Laid-Open Patent Publication No. 10-2015-0031543 (March 25, 2015): A clock reproducing apparatus and a regeneration method for a cascaded circuit.

Disclosure of Invention The present invention has an object to solve the above technical problem, and in a semiconductor chip connected in a daisy chain structure, jitter and noise of a clock are not propagated to a semiconductor chip of a later stage. And its semiconductor chip.

In addition, another object of the present invention is to provide a data processing method of a semiconductor chip capable of reducing power consumption and a semiconductor chip, which may occur in a semiconductor chip connected in a daisy chain structure using a shifter register.

The semiconductor chip of the present invention comprises: a separator for separating input data into first type data and second type data; Receiving the second type of K bytes of data from the separator, and outputs the (KM) byte of the data of the second type K of the received K bytes, and the data of M bytes of the second type of data of the K bytes Memory for storing; And a clock signal generator for generating a first clock signal.

Specifically, the memory may receive the second type of K bytes of data from the separator using the second clock signal input to the semiconductor chip, and the second byte of the K bytes using the first clock signal. And (KM) byte data of the slave data.

The separator may further output the first type data or the changed first type data using the first clock signal, and output the second type data using the second clock signal.

In addition, the semiconductor chip of the present invention receives the first type data or the changed first type data from the separator, receives the second type data from the memory, and serializes the data using the first clock signal. And a serializer for outputting. In addition, the serializer receives the first clock signal and outputs the first clock signal according to a control signal.

Preferably, the semiconductor chip of the present invention further includes a parallelizer for receiving and parallelizing the first type data, the second type data, and the second clock signal, and outputting the parallel type chip. And outputting the output parallelized first type data, the second type data and the second clock signal.

In addition, the memory is a FIFO (First In First Out) type memory, the storage capacity of the memory is preferably M bytes.

A data processing method of a semiconductor chip of the present invention includes the steps of: (a) separating input data into first type data and second type data; (b) receiving the second type of K bytes of data from the step (a), outputting (KM) bytes of the second type of data of the K bytes, and outputting the second type of K bytes of data; Storing M bytes of data; (c) generating a first clock signal; And (d) receiving the first type of data or the changed first type of data from step (a), receiving the second type of data from step (b), and serializing using the first clock signal. It includes; outputting.

Specifically, in the step (b), the second type of K byte data is input using the second clock signal input to the semiconductor chip of the present invention, and the K byte of the first byte signal is used using the first clock signal. It is characterized by outputting (KM) byte data of two kinds of data.

The step (a) may include outputting the first type data or the changed first type data using the first clock signal, and outputting the second type data using the second clock signal. desirable.

In the step (d), the first clock signal is input and output according to a control signal.

Preferably, the data processing method of the semiconductor chip of the present invention, the method, before the step (a), the first type of data, the second type of data and the second clock signal to receive and parallelize and output In addition, the step (a) is characterized in that for receiving the parallelized first type data, the second type data and the second clock signal outputted from the parallelized output.

In addition, the step (b) uses a memory of the first in first out (FIFO) method, the storage capacity for the second type of data of the memory, characterized in that M bytes.

According to the data processing method of the semiconductor chip and the semiconductor chip of the present invention, in the semiconductor chip connected in a daisy chain structure, jitter and noise of the clock can be prevented from propagating to the semiconductor chip of the subsequent stage. In addition, according to the present invention, power consumption that may occur in a semiconductor chip connected in a daisy chain structure using a shifter resistor may be reduced.

1 is a block diagram of a semiconductor chip connected in a daisy chain structure.
2 is an explanatory diagram of a clock in which an error due to noise occurs.
3 is a configuration diagram of a system using a semiconductor chip of the present invention.
4 is a block diagram of a semiconductor chip according to an embodiment of the present invention.
5 is an explanatory diagram of data flow in a system in which a semiconductor chip of the present invention is connected in a daisy chain structure.
6 is a flowchart of a data processing method of a semiconductor chip in accordance with one preferred embodiment of the present invention.

Hereinafter, a data processing method and a semiconductor chip of a semiconductor chip according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The following examples of the present invention are intended to embody the present invention, but not to limit or limit the scope of the present invention. From the detailed description and examples of the present invention, those skilled in the art to which the present invention pertains can easily be interpreted as belonging to the scope of the present invention.

3 shows a configuration diagram of a system using the semiconductor chip 100 of the present invention.

The use of the semiconductor chip 100 of the present invention may be a driving chip for driving an LED display, for example, a plurality of semiconductor chips 100 are connected in a daisy chain structure to drive a plurality of LEDs. Will be.

4 illustrates a configuration diagram of a semiconductor chip 100 according to an exemplary embodiment of the present invention.

As can be seen from Figure 4, the semiconductor chip 100 according to a preferred embodiment of the present invention, the parallelizer 10, the separator 20, the memory 30, the clock signal generator 40, the serializer 50 and a drive unit 60.

The parallelizer 10 receives the first type data, the second type data, and the second clock signal to parallelize and output the same. The parallelizer 10 is generally called a parallelizer.

Here, the first type data, also called prefix data, is data about a value held through an external pad, a register value, or a fuse, and is commonly used in a plurality of semiconductor chips 100 connected in a daisy chain structure. Data.

In addition, second type data, also called segment data, is data uniquely used by each semiconductor chip 100 of the plurality of semiconductor chips 100 connected in a daisy chain structure.

The separator 20 receives the parallelized first type data, the second type data, and the second clock signal output from the parallelizer 10, and divides the first type data and the second type data. In order to separate the first type data and the second type data, the separator 20 needs to receive or store data number information of the first type data in advance. Preferably, the number of second type data input to the separator 20 is K bytes. When the number of second type data for driving one semiconductor chip 100 is M bytes, the K byte is driven by the semiconductor chip 100 and the semiconductor chip 100 after the semiconductor chip 100. Is the number of type 2 data required. That is, if the current semiconductor chip 100 is the L-th chip, and (N-L) remaining semiconductor chips 100 remain, K = {(N- (L-1)) x M} bytes.

In addition, the separator 20 may output the first type data as it is, or change the first type data and output the same. For example, when ID and / or address allocation information of the L-th semiconductor chip 100 and the (L + 1) -th semiconductor chip 100 in the daisy chain structure is different, the L-th semiconductor chip 100 is changed. It is preferable to drive the corresponding elds using the first type of data that is not present, and change the current first type of data so as to match the (L + 1) th semiconductor chip 100 and output the same to the serializer 50. will be. In some cases, the LDLs are driven by using the first type data which is not changed in the L-th semiconductor chip 100, and the first type data which is not changed even by the (L + 1) -th semiconductor chip 100. May be output to the serializer 50. That is, whether to insert the first type data change function into the separator 20 may be set according to the design of the semiconductor chip 100.

Separator 20 may be implemented using at least a portion of a processor such as an MCU, DSP, MCU, or the like, using circuit elements, or a combination thereof.

The memory 30 receives K-byte second type data from the separator 20, outputs (KM) byte data of the K-type second type data, and outputs K-type second data. M bytes of data serve to store. The memory 30 is preferably the memory 30 of the FIFO (First In First Out) system. In addition, the storage capacity for the second type of data of the memory 30 is characterized in that M bytes.

In general, when a shift register is used as the memory 30, the number of shift registers that toggles every clock is the number of second type data required by the semiconductor chip 100 at worst. It becomes equal to M bytes, so that the maximum current and average power become large, and the power consumption becomes large. The use of the FIFO type memory 30 can solve this problem of power consumption.

The clock signal generator 40 serves to generate a first clock signal using an oscillator.

The serializer 50 is generally called a serializer, and serves to serialize and output input data.

The driver 60 receives first type data from the separator 20 and second type data from the memory 30 to generate a driving signal for driving the LED. The driver 60 may be implemented by using an element such as an amplifier.

That is, according to the present invention, a first clock signal, which is an internal clock signal, may be generated for each semiconductor chip 100, and the first and second binary data may be read or output from the separator 20, the memory 30, or the like. Data processing is possible by the clock signal and the second clock signal, so that the influence of the noise and / or jitter of the second clock signal as the input clock is not received by the first clock signal as the output clock.

Hereinafter, the separate use of the first clock signal and the second clock signal in each component will be described in detail.

The separator 20 outputs the first type data or the changed first type data using the first clock signal, and outputs the second type data using the second clock signal. The first type data or the modified first type data output by the separator 20 using the first clock signal is input to the serializer 50. In addition, the separator 20 may output the first type of data using the first clock signal or the second clock signal to be input to the driver 50. That is, the first type of data input to the driver 50 is not limited by the clock signal.

In addition, the memory 30 receives the second type of K-byte data by using the second clock signal, and outputs (KM) -byte data of the second type of K-byte data by using the first clock signal. .

Further, the serializer 50 receives the first type data or the changed first type data from the separator 20 using the first clock signal, and the second type from the memory 30 using the first clock signal. The data is input, serialized using the first clock signal, and output.

The serializer 50 receives the first clock signal and outputs the first clock signal according to the control signal. The first clock signal output by the serializer 50 is used when data is input from the semiconductor chip 100 at a later stage.

5 is an explanatory diagram of data flow in a system in which the semiconductor chip 100 of the present invention is connected in a daisy chain structure.

The first type of data and the second type of data of {(N- (L-1)) × M} bytes are input to the L-th semiconductor chip 100 among the N semiconductor chips 100 in total. Among the input second type data, M bytes are stored in the memory 30, and {(N-L) × M} bytes are output.

The first type of data is first input to the L-th semiconductor chip 100, and the second type of data of {(N− (L-1)) × M} bytes is input later, and the parallelizer 10 is inputted. By the separator 20 to be parallelized by the separator 20 and serialized by the serializer 50, so that time t 1 is required to output the first type data from the L-th semiconductor chip 100. do. In addition, in order for the second type of data to be output to the L-th semiconductor chip 100, the MFI memory 30 is output after a time t2 required for storing the M-byte memory 30. do. That is, when the storage capacity for the second type of data of M bytes of the memory 30 is filled, the second type of data is output from the memory 30. As a result, the number of bytes of the second type of data finally output from the memory 30 is {(N-L)) × M} bytes excluding M bytes stored in the memory 30.

6 is a flowchart illustrating a data processing method of the semiconductor chip 100 according to an exemplary embodiment of the present invention. Since the data processing method of the semiconductor chip 100 according to the exemplary embodiment of FIG. 6 uses the semiconductor chip 100 of the present invention described above, the semiconductor chip 100 of the present invention described above may be used without a separate description. Of course, it includes all the features of).

As can be seen from Figure 6, the data processing method of the semiconductor chip 100 according to an embodiment of the present invention, the step of parallelizing and outputting the first type data, the second type data and the second clock signal ( S10); Dividing the received data into first type data and second type data (S20); Receiving the second type of K-byte data from the step S20, and outputs the (KM) byte of the data of the second type of K-byte received, and stores the M-byte data of the second type of K-byte data (S30); Generating a first clock signal (S40); And receiving the first type data or the changed first type data from the step S20, receiving the second type data from the step S30, and serializing and outputting the first type using the first clock signal (S50).

In operation S20, the first type of data may be output as it is, or the first type of data may be changed and output. In operation S20, the first type data or the changed first type data may be output using the first clock signal, and the second type data may be output using the second clock signal.

In operation S20, the parallelized first type data, the second type data, and the second clock signal output from the step S10 may be input.

In addition, in step S30, the second type of K byte data is input using the second clock signal input to the semiconductor chip 100, and the second type of K byte type data of the K byte data is used (KM). It is characterized by outputting the data of byte. In addition, in the step S30, the memory 30 of the first in first out (FIFO) method is used, and the storage capacity for the second type of data of the memory 30 is preferably M bytes.

In operation S50, the first clock signal may be input and output according to a control signal.

As described above, according to the data processing method of the semiconductor chip 100 and the semiconductor chip 100 of the present invention, in the semiconductor chip 100 connected in a daisy chain structure, jitter and noise of a clock are the semiconductor chip of the latter stage. It can be seen that it can be prevented from propagating to (100). In addition, according to the present invention, power consumption that may occur in the semiconductor chip 100 connected in a daisy chain structure using a shifter resistor may be reduced.

100: semiconductor chip
10: parallelizer
20: separator
30: memory
40: clock signal generator
50: serializer
60 drive unit

Claims (16)

In a semiconductor chip,
A separator for separating the received data into first type data and second type data;
Receiving the second type of K bytes of data from the separator, and outputs the (KM) byte of the data of the second type K of the received K bytes, and the data of M bytes of the K Memory for storing; And
A clock signal generator for generating a first clock signal;
And K and M are integers greater than 0, and (KM) is an integer of 0 or more. The method of claim 1,
The memory,
The second type of K-byte data is input from the separator using the second clock signal input to the semiconductor chip, and the (KM) byte of the second type of K-byte data is used by the first clock signal. A semiconductor chip characterized by outputting data. The method of claim 2,
The semiconductor chip is connected in a daisy chain structure with a semiconductor chip at a rear end of the semiconductor chip,
The semiconductor chip and the semiconductor chip of the rear end each include an ID or address information,
The separator,
Outputting the first type of data using the first clock signal, or outputting the first type of data changed to match an ID or an address of the semiconductor chip of the subsequent stage using the first clock signal,
The separator,
And outputting the second type of data using the second clock signal. The method of claim 3, wherein
Receives the first type data outputted from the separator or the first type data modified and outputted from the separator, receives the second type data of (KM) bytes from the memory, and serializes the data using the first clock signal. And a serializer for outputting the semiconductor chip. The method of claim 4, wherein
The serializer,
And receiving the first clock signal and outputting the first clock signal according to a control signal. The method of claim 1,
The semiconductor chip,
And a parallelizer configured to receive the first type data, the second type data, and the second clock signal in parallel and output the same.
The separator,
And receiving parallelized first type data, second type data, and a second clock signal output from the parallelizer. The method of claim 1,
The memory,
A semiconductor chip comprising a first in first out (FIFO) type memory. The method of claim 7, wherein
Storage capacity for the second type of data of the memory,
A semiconductor chip characterized by being M bytes. In the data processing method of a semiconductor chip,
(a) dividing the received data into first type data and second type data;
(b) receiving the second type of K bytes of data from the step (a), outputting (KM) bytes of the second type of data of the K bytes, and outputting the second type of K bytes of data; Storing M bytes of data; And
(c) generating a first clock signal;
And K and M are integers greater than zero, and (KM) is an integer of zero or more. The method of claim 9,
In step (b),
The second type of K-byte data is input using the second clock signal input to the semiconductor chip, and the KM-byte data of the second type data of K bytes is output using the first clock signal. The data processing method characterized by the above-mentioned. The method of claim 10,
The semiconductor chip is connected in a daisy chain structure with a semiconductor chip at a rear end of the semiconductor chip,
The semiconductor chip and the semiconductor chip of the rear end each include an ID or address information,
In step (a),
Outputting the first type of data using the first clock signal, or outputting the first type of data changed to match an ID or an address of the semiconductor chip of the subsequent stage using the first clock signal,
In step (a),
And outputting the second type of data using the second clock signal. The method of claim 11,
The method,
(d) receiving the first type of data output from step (a) or the first type of data that has been modified and output, and receiving the second type of data of (KM) bytes from step (b), And serializing and outputting the same by using a clock signal. The method of claim 12,
In step (d),
And receiving the first clock signal and outputting the first clock signal according to a control signal. The method of claim 9,
The method, before step (a),
Receiving the first type data, the second type data, and the second clock signal in parallel and outputting the same;
In step (a),
And receiving the parallelized first type data, the second type data, and the second clock signal outputted from the parallelized output. The method of claim 9,
In step (b),
A data processing method comprising using a memory of a First In First Out (FIFO) method. The method of claim 15,
Storage capacity for the second type of data of the memory,
And M bytes.

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