JPH07248904A - Linear feedback shift register and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a linear feedback shift register for satisfying the conditions of pseudo random number generation or linear feedback while being provided with F/Fs operated by mutually different clocks and a semiconductor integrated circuit device provided with the linear feedback shift register. CONSTITUTION:The plural sets 101, 102 and 103 of the F/Fs operated in synchronism with the mutually different clocks CLK1, CLK2 and CLK3 are provided and the F/F 1 for satisfying the conditions of the pseudo random number generation or the linear feedback or mutually serially connected F/F 2 and a delay 3 are inserted mutually among the sets 101, 102 and 103 of the F/Fs. By this constitution, even when the sets 101, 102 and 103 of the F/Fs are operated in synchronism with the mutually different clocks CLK1, CLK2 and CLK3, output from the desired set of the F/Fs is delayed and signals propagated to the sets 101, 102 and 103 of the F/Fs satisfy the conditions of the pseudo random number generation or the linear feedback by the delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear feedback shift register and a semiconductor integrated circuit device having the linear feedback shift register,
Especially, LSI (Large Scale Integration), and VLSI (Very Large Scale Integration).
on), ULSI (Ultra Large Scale Integration) design for testability, and particularly a linear feedback shift register useful for built-in self test (Built-In Self Test), and a semiconductor integrated circuit including the same.

[0002]

2. Description of the Related Art Due to rapid progress in semiconductor technology, LSI
VLSI with even greater scale, complexity, and higher performance
Appears, and the appearance of ULSI is about to come. Along with this, the question of how to test these chips has become a very serious issue. In the conventional LSI chip, the LSI tester generally tests using only the functions defined for normal operation, but in VLSI and ULSI, it is necessary to create a huge amount of test vectors, and moreover,
LSI testers that can support the testing of these chips are also becoming more and more sophisticated and therefore more expensive. Furthermore, an objective determination of how well these test vectors are testing the chip must be made separately, which requires a great deal of CPU cost.

For these reasons, the VLS is used by the conventional method.
It is practically impossible to completely test the I and ULSI chips. As a solution to such a serious problem, design for testability, in which a test circuit for facilitating the test is built in the chip in advance and complete testing is performed at a low cost, is drawing attention and spreading.

Built-in self test (hereinafter abbreviated as BIST), which is a type of testability design
Is the device under test (DUT)
A test data generating circuit and a test result judging circuit for a circuit block inside the LSI chip are incorporated in the LSI chip, a test is started by an external signal, and a pass / fail judgment result signal or In the test that outputs the test result for judgment, LS
Almost no I tester is required, which is extremely effective in reducing test costs. What's more, the chip can be tested under the same conditions that it will be used, and can be tested after it is installed in the system. Because of these many outstanding advantages, BIST is expected to play a very important role in VLSI and ULSI testing.

The most basic technique in BIST as described above is called signature analysis (Signa-ture Analysis). This technology is based on the Linear Feedback Shift Register (LFS).
R is abbreviated).

First, the LFSR will be described. L
The FSR (bit width is n) can be used as a test data generation circuit and a test result determination circuit. LFSR (bit width n =
8) is n serially connected D-type flip-flops (hereinafter abbreviated as F / F) as shown in FIG.
And an exclusive OR of the output Q of a predetermined F / F (Exclusive-
OR: Feedback (Feedba) for generating and inputting to the D input of the first F / F of the serial connection
ck) circuit and a simple register circuit.

Initial values other than all-0 are set to the above F / F (this L
In the FSR, an initialization circuit is omitted). When the FSR is set and then operated, almost 2 ⁿ −1 (maximum number obtained by the LFSR) substantially random data (pseudo-random number) is output in a fixed order. This pseudo-random number can be taken out sequentially by using any of the outputs of the n F / Fs (Out _i , i = 0, ..., 7), or by using all of these outputs in parallel. You can also take it out.

The latter method is general and important for VLSIs and ULSIs in which data processing is performed with a recent multi-bit width. Now, the signature analysis is a technique that uses the LFSR as a test result determination circuit. Again, D
LFSR of the type that inputs output from UT serially
And MISR (Multiple Input Signature Register)
There is a parallel input type LFSR, also called
The latter is overwhelmingly more important in LSI and ULSI. Therefore, we will focus on this point from here on. An example of an n-bit parallel input type LFSR is shown in FIG. 10b (bit width n = 8). Bit i in LFSR (i =
0, ..., 6) Q output Q _i (= Out _i ) of F / F and external data In _{i + 1} of bit i + 1 are input to the D input of F / F of bit i + 1 via the XOR circuit. In addition, the output FB (= Q ₀ XO of the feedback circuit of the LFSR described above is input to the D input of the F / F of bit 0.
R Q ₅ XOR Q ₆ XOR Q ₇ ) and the external data of bit 0 are input via the XOR circuit.
The data newly generated inside the LFSR is Q ′ _i (i =
0, ..., 7), these are expressed by equations as follows: Q ′ _O = In _O XOR FB (Equation 1) Q ′ _{i + 1} = In _i XOR Q _i (i = 0, ..., 6) ... (Equation 2) (where XOR is a symbol representing an XOR operation). Due to the above configuration, an LFSR in which a certain fixed value is stored
When the response output from the DUT is sequentially applied to, internal random numbers are formed in the internal F / F according to those values, and finally, some specific test result data is stored in the LFSR. Has been formed. This LF
The data generated inside the SR is
: Signature, and the operation of applying a response output from the DUT to generate a signature is signature compression (Signat).
ure Compression) or signature analysis (Signature
Analysis) operation. In the signature analysis, the response output from the DUT for a series of test data is signature-compressed, and finally the test result (signature) remaining in the LFSR is compared with the expected value only once, so that the DUT is analyzed.
This is an analysis method for determining the quality of (the circuit block inside itself).

In general, after performing signature compression with sufficient test data, the final signature (test result) is the same as that in the normal state, even though the above signature has a correct probability that the output is different from that in the normal state. 1-2 subtracted from the probability of alias (Alias)
^-n . The alias probability generally has a large n (n>
24), it can be ignored, so that the reliability of signature analysis is extremely high in VLSI and VLSI in which multi-bit (n ≧ 32) width data processing is general.

Although the above LFSR may be provided exclusively for BIST, a register for normal operation is often diverted in order to save the test circuit.

In the conventional example described above, the LFSR is used.
As a result of being regarded as one circuit block, only those which operate by receiving a single clock from the outside have been considered. BIST using LFSR starts with RO
The application started with those having a regular structure such as M, RAM and PLA. These are, so to speak, registers, F
Circuit blocks that are "closed" by / F, and their outputs are usually stored in output registers on the edge of the system clock,
In the BIST that uses this output register as an LFSR and is used as a signature compression circuit, it is possible to simultaneously check the AC operation delay failure of the DUT.

More generally, a register that changes at the edge of the system clock, a DUT that is "closed" in the F / F, is used in a so-called random logic instead of in the circuit block having the regular structure as described above. If possible (a non-important signal may have a fixed value during the BIST period), a BIST that can be checked including its AC output delay can be effectively implemented, and thus such a BIST may be used in some cases. It has become to.

[0013]

However, in the I / O (Input / Output) section of a general LSI, for example, the signal delay at the output terminal of the LSI is less than one cycle based on the edge of the system clock. It is supposed to be delayed by a predetermined time. Therefore, the BI using the LFSR that operates at the edge of the conventional system clock is used.
If ST is applied to the output terminal of the LSI, LFSR
Although it is possible to check the logical value at the timing (the edge of the system clock) at which the data sampling is performed, there is a problem that the delay failure of the AC output from the DUT cannot be detected.

That is, the conventional BI to the input / output terminal of the LSI is
There is a big problem that the application of ST can basically be realized only in a form lacking the important item of checking the AC output delay.

Further, in the present and future, it is attempted to achieve high performance by mixing circuit blocks operating in synchronization with a plurality of clocks (including different edges of the same clock) inside the VLSI or ULSI. It is very likely that the design method will become important. On the other hand, the BIST using the conventional LFSR needs to be configured with a sufficient bit width in order to suppress the alias probability to a negligible level. Therefore, an extra register is required for each register and F / F group operating at each clock. LF by adding F / F
There is a high possibility that the SR has to be configured, and as a result, there is a problem that the area has to be increased.

Further, such overhead may be disliked and the application of BIST itself may be abandoned. The present invention has been made in view of the above problems, and an object thereof is to provide a linear feedback shift register that satisfies the conditions of pseudo-random number generation or linear feedback while including flip-flops that operate with different clocks. It is to provide a semiconductor integrated circuit device having the same.

[0017]

In order to achieve the above object, a linear feedback shift register according to the present invention includes a set of a plurality of flip-flops which operate in synchronization with mutually different clocks, and the flip-flops of these flip-flops are provided. It is characterized in that a means for establishing a condition of linear feedback that satisfies the condition of pseudo-random number generation or linear feedback is inserted between the sets.

[0018]

With the linear feedback shift register having the above structure,
Even if a plurality of flip-flop groups operate in synchronization with clocks different from each other, the plurality of flip-flop groups can operate in synchronization with each other by inserting a means for satisfying the condition of pseudo-random number generation or linear feedback. Of flip-flops can operate cooperatively as one LFSR. Therefore, this linear feedback shift register is allowed to operate in synchronization with different clocks for each flip-flop.

Such a linear feedback shift register has L
In SI, it can be effectively applied to embedded self-test (BIST). For example, it is considered that a flip-flop group provided in a boundary scan circuit provided in a recent LSI is a set of the flip-flops that operate in synchronization with a plurality of clocks. Since these operate with different clocks, not only the system clock edge of the LSI,
Signature compression can be performed at clock edges different from each other. Therefore, it is possible to detect an AC output delay failure from the circuit under test when applied to the input / output terminal portion of the LSI, which cannot be achieved by the circuit of the system synchronized with the system clock.

Further, the boundary scan circuit may be connected to each other while inserting the establishing means for establishing the condition of the linear feedback as in the above-mentioned configuration, and may be constructed in the linear feedback shift register. With this construction, a linear feedback shift register having a sufficient bit width such that the alias probability can be ignored can be obtained without adding a new flip-flop, and the area efficiency is improved.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a parallel input type LFSR according to a first embodiment of the present invention. LF shown in FIG.
SR is a plurality (here, three types) of clocks CLK1 and CLK
2, n-bit width parallel input type LF operating under CLK3
It is SR. This parallel input type LFSR is composed of flip-flops (F / Fs) 10 and 11, and is composed of a first set 101 and F / Fs 12 and 13 that operate in synchronization with a clock CLK2, and operates in synchronization with a clock CLK3. , 15 and includes a third set 103 which operates in synchronization with the clock CLK1. These groups 101, 102 and 103 are serially connected. At the connection point where the first set 101 and the second set 102 are connected to each other, the delay 3 and the F / F 2 serially connected to each other are inserted. Also, the third group 1
03 is connected to the first set 101 via the feedback circuit 200. An F / F1 is inserted at the connection point between the feedback circuit 200 and the first set 101. The feedback signal FB is input to the D terminal of the F / F1. Q terminal of F / F1 is XO
Connected to the first input of R (exclusive OR) gate 20,
The second input of the XOR gate 20 is connected to the data signal terminal d ₀ . The output of the XOR gate 20 is connected to the D terminal of the F / F 10. The Q terminal of F / F10 is XOR
It is connected to the first input of the gate 21 and to the first input of the XOR gate 30 in the feedback circuit 200. The second input of the XOR gate 21 is the data signal terminal d.
Connected to ₁ . The output of the XOR gate 21 is F / F
11 is connected to the D terminal, and the Q terminal of the F / F 11 is connected to one end of the delay 3. The other end of the delay 3 is connected to the D terminal of the F / F 2, the Q terminal of the F / F 2 is connected to the first input of the XOR gate 22, and the XOR gate 31 in the feedback circuit 200 is connected. Connected to the first input of the. The second input of the XOR gate 22 is connected to the data signal terminal d ₂ . The output of the XOR gate 22 is connected to the D terminal of the F / F 12, and the Q of the F / F 12 is connected.
The terminal is connected to the first input of the XOR gate 23.
The second input of the XOR gate 23 is connected to the data signal terminal d ₃ , and its output is connected to the D terminal of the F / F 13. The Q terminal of the F / F 13 is connected to the first input of the XOR gate 24. The second input of the XOR gate 24 is a data
Signal terminal d ₄ and its output is D of F / F 14.
It is connected to the terminal. The Q terminal of F / F14 is a feedback circuit
It is connected to the first input of the XOR gate 32 in 200 and is connected to the first input of the XOR gate (not shown) by the same connection as the other F / F groups 101 and 102. And
The output of the XOR gate (not shown) is connected to the D terminal of the F / F (not shown), and its Q terminal is connected to the first input of the XOR gate 25 (this is the data signal terminal d). 2 or more F / Fs may be present in the F / F set depending on the number of F). The second input of the XOR gate 25 is connected to the data signal terminal d _n-1 and its output is connected to the D terminal of the F / F 15. The Q terminal of the F / F15 is connected to the second input of the XOR gate 32, and its output is the XOR gate 3
1 is connected to the second input. The output of XOR gate 31 is connected to the second input of XOR gate 30. XOR
The output of the gate 30 is connected to the D terminal of F / F1. The output of this XOR gate 30 is the feedback signal FB. In this embodiment, the F / F output for generating the feedback signal FB is selected from an appropriate F / F for the purpose of explaining the operation described later.

F / F1, provided in the LFSR,
2, 10 to 15 are three types of clock signals CLK1, CLK2,
Rising edge of CLK3 (hereafter CLK1 ↑, CLK2 respectively
(Abbreviated as ↑ and CLK3 ↑) latches the input to the D terminal.
Here, F / F1, 14, ..., 15 are CLK1 ↑, and F / F
10, 11, and 2 are CLK2 ↑, and F / F12 and 13 are CLK3 ↑.
Then, the input to the D terminal is latched (herein, the F / F for latching the data at the rising edge of the clock signal is shown as an example, but the F / F of other structures may be used). The timing relationship between these clocks CLK1, CLK2 and CLK3 is shown in FIG.

When operating the LFSR with a plurality of clocks, it is easy to be ambiguous as to which data from the DUT (circuit under test) and which data inside the LFSR are signature-compressed. If you do not configure the LFSR after holding it down, even if you execute BIST with the intention of using it as a signature compression circuit, the operation condition of signature compression will not be satisfied, and the expected high quality BIST may not be realized. There is.

In consideration of the fact that, in general, any synchronous logic circuit is designed to give an output to a predetermined input defined according to each cycle of the basic system clock, the signature compression. You can clearly define the set of data you want. Based on this,
In the LFSR shown in FIG. 1, there are data d _O , ..., D _n-1 from a DUT (not shown) which is desired to be signature-compressed.
These data are compressed into corresponding F / Fs in the order of (1) to (3) below (XORed with other data and latched will be expressed as compressed). .

(1) The data d ₄ , ..., D _n-1 are compressed into F / F 14, ..., 15 by CLK1 ↑. (2) The data d ₀ and d ₁ are F / F 10, due to CLK2 ↑
Compressed to 11.

(3) The data d ₂ and d ₃ are compressed into F / Fs 12 and 13 by CLK3 ↑. A timing chart for these operations is shown in FIG. The data sets d _O , ..., D _n−1 correspond to the hatched portions and are compressed to the corresponding F / F at the time indicated by the downward arrow. The portion indicated by "X" indicates that the data is not valid.

As described in the conventional example, as a result of performing signature compression on the data d _O , ..., D _n-1 and the F / F data q ₀ , ..., Q _n-1 inside the LFSR,
Data of LFSR internal the F / F is _{q '0, ..., q'} n-1
If it changes to, the following must hold.

Q ′ _O = d _O XOR FB (Equation 3) (FB = q ₀ XOR q ₁ XOR q ₄ XOR q _n-1 q ′ _i = d _i XOR q _i-1 (i = 1, ... , N-1) (Equation 4) The operations (1) to (3) will be described in detail while paying attention to the above.

First, in (1), d ₄ , d _n-1 and q
_4, ..., a _{q n-1, q '4} , ..., q' n-1 is (Equation 4)
Corresponding to F / F14, ...,
It is stored in 15. However, the feedback signal FB is FB ′ = q ₀
It should be noted that varies the _{XOR q 1 XOR q '4 XOR} q' n-1.

Next, in (2), d ₁ , q ₀ , q '
(Equation 4) holds between ₁ and there is no problem (however, CLK3 ↑
Q ₁ related to latching the data at is that changing the q _'1 It has to be noted). However, regarding (Equation 3), since the feedback signal FB has already changed to FB ′, q ′ ₀ = d ₀ XOR FB ′ remains with the conventional LFSR configuration, and the signature compression is performed. The condition of will be broken. Therefore,
In this embodiment, as shown in FIG. 1, by inserting F / F1 which latches and holds the feedback signal FB at CLK1 ↑, the relationship of (Equation 3) is satisfied.

Further, in (3), d ₃ , q ₂ ,
Between q _'3 satisfied (Equation 4), no problem. However, as in the case of (2), with the conventional LFSR configuration, q ′ ₂ = d ₁ XOR q ′ ₁ , and the signature compression condition is broken. Therefore, in this embodiment, similarly to the case of (2), F / F2 for latching and holding data at CLK2 ↑ is inserted, and (Equation 3)
I want to be able to satisfy the relationship. Delay 3
Is provided in order to allow the data of the F / F 11 to be correctly propagated to the F / F 2. However, it is not necessary in some cases (the necessity is not related to the essence of the invention. It's not there, so I won't go into it here)

As described above, in this embodiment, a plurality of F / F groups operating in synchronization with mutually different clocks are set so that the linear feedback condition for signature compression is satisfied.
By inserting the F / Fs 1 and 2 that temporarily hold data at appropriate positions, it is possible to operate as one LFSR in a coordinated manner.

Next, a second embodiment of the present invention will be described with reference to FIGS. The device according to the second embodiment is provided with a circuit that can realize the role played by the F / Fs 1 and 2 in the first embodiment with a simpler circuit. FIG. 3A is a diagram showing the configuration of this simplified circuit.

As shown in FIG. 3A, the simplified circuit is basically a circuit that performs a latch operation. This circuit is designated by reference numeral 40 and will be referred to as a latch circuit. The latch circuit 40 includes a clocked inverter 41 as an input section connected to the terminal D.
And the output of the clocked inverter 41 is input, and the inverter 42 is connected as an output to the terminal DO.
And a latch portion 44 connected to a node 43 of the clocked inverter 41 and the inverter 42. The latch section 44 comprises an inverter 45 having an input connected to the node 43, and a clocked inverter 46 to which the output of the inverter 45 is input. The output of the clocked inverter 46 is connected to the node 43.
FIG. 3B shows the basic circuit configuration of the clocked inverters 41 and 46. There are three inputs, control input 1, control input 2, and input, and one output. In normal usage, the control input 2 is
Inversion of control input 1 is used. When control input 1 = Low (hereinafter written as 0), the output becomes hi-Z (high impedance) regardless of the input value, and the control input 1
= High (hereinafter, written as 1), the same logical operation as the inverter is performed. The clock signal is at terminal C
Is supplied to the control input 2 of the clocked inverter 41 and the control input 1 of the clocked inverter 46. Further, the latch circuit 40 is provided with an inverter 47 for generating an inverted signal of the clock signal applied to the terminal C, the output of which is the control input 1 of the clocked inverter 41. , And the control input 2 of the clocked inverter 46. In the figure, black circles near the clocked inverters 41 and 46 indicate that the adjacent input is the control input 2.

Next, the operation when the latch circuit 40 is incorporated in the LFSR shown in FIG. 1 will be described. First, as can be seen from FIG. 2, data d ₀ and d ₁ at CLK2 ↑
Is compressed during the period of CLK1 = 1. That is, the feedback signal FB can be held only during the period of CLK1 = 1.

The latch circuit 40 shown in FIG.
At the rising edge of the clock signal input to the C terminal, the input data to the DI terminal is latched and the clock signal = 1
During the period of 0, the input to the D terminal is propagated to the DO terminal during the period of the clock signal = 0. Therefore, in place of the F / F1 shown in FIG. 1, this latch circuit 40 is provided, and CLK1 is connected to its C terminal (nodes a and b in FIG.
By connecting (connecting the I terminal and the DO terminal), it is understood that the purpose can be sufficiently achieved by the latch circuit having the circuit amount of almost half of F / F1.

Further, as can be seen from FIG. 2, the data d
_2, CLK3 ↑ is that d ₃ is compressed, CLK2 ↓ (CLK2
Falling edge). Also here, F
When replacing / F2 with the latch circuit 40 shown in FIG. 3A, the C terminal is set to CLK2. At this time, if there is a skew between CLK2 and CLK3, CLK3 ↑ is to CLK2 ↓, via the DO terminal from DI terminal of the latch circuit 40, XOR gate of FIG. 1 - When was behind the propagation delay approximately to the output of the sheet 22, the data q _'1 which has already been changed But the data d ₁ from the DUT and XO
There is a risk that it will be red and latched by the F / F 12.
However, if the timing design between CLK2 ↓ and CLK3 ↑ is performed after paying sufficient attention to this point, the above-mentioned propagation delay time is considerably longer than the achievable clock skew, so that the latch circuit 40 can be used. it can. However, in reality, such timing design is often troublesome and involves some risk, so from the viewpoint of simplicity of design and certainty of operation,
This means that it is preferable to use F / F2.

As can be understood from the above description, the essence of the present invention is to combine a plurality of F / F groups operating in synchronization with different clocks with each other to form one LFSR.
When configuring the F / F (F / F
When the clock that operates the feedback signal generated by using the Q output of F as an input) precedes the clock that operates the F / F on the data receiving side, the condition of signature compression is not broken, That is, an F / F or a latch for temporarily holding the data stored in the former F / F is inserted. From this point, in the above,
Although an example in which the clocks have the same period but different phases has been described, the present invention can be applied to the case where clocks having different periods are mixed.

In the above embodiment, if the relative position between the outputs from the DUT can be freely changed, L
The number of F / Fs or latches to be inserted inside the FSR can be suppressed to one at the minimum. For example, the F / F groups 1, 2, ... In which data changes according to the edges of a plurality of clocks CLK1, CLK2 ,.
In the case where the FSR is arranged in the direction opposite to the flow of data (excluding feedback data) inside the FSR, only the F / F or the latch for holding the feedback signal may be inserted. By making good use of such information, the amount of additional circuits can be effectively reduced in actual implementation.

Next, as a third embodiment, an example in which the LFSR according to the present invention is used as a pseudo random number generating circuit will be described. As shown in FIG. 4, when the pseudo random number generation circuit is configured, the XOR circuits 20 to 2 for signature compression of the output from the DUT from the circuit shown in FIG.
5 may be deleted, and the delay 3 may be added to an appropriate position in order to guarantee correct operation (these delays 3 may not be necessary).

In FIG. 4, those assigned the same reference numerals as in FIG. 1 are used in the same meaning. clock
CLK1, CLK2, CLK3 also change at the same timing as shown in FIG.

The conditions for generating the pseudo-random number having the maximum length (2 ⁿ -1 cycle) mentioned in the conventional example are shown below (feedback signal FB
Is said to be configured to give the maximum length). q ′ _O = FB = q ₀ XOR q ₁ XOR q ₄ XOR q _n-1 q ′ _i = q _i-1 (i = 1, ..., n−1) In pseudo-random number generation, unlike signature compression, Although it is difficult to define which clock is the first, considering the essence of the present invention described above, regardless of this definition, if a conventional LFSR configuration is adopted, in general, q ′ _i = q It is easy to see that ′ _i−1 = q _i−2 and the above conditions are not satisfied. Therefore, as shown in Fig. 4, the F / F
It would be most desirable to have 1, 2 (or a latch).

Next, as a fourth embodiment, a semiconductor integrated circuit device in which the LFSR according to the present invention is applied to an I / O (Input / Output) section of an LSI will be described. Originally
Registers and F / Fs are rarely provided in the input / output terminals of the I / O section of the LSI. Therefore, when the present invention is applied to this section, it is necessary to add an F / F to each input / output terminal. There seems to be no realization in terms of area increase. Therefore, first, the technical background and feasibility of this embodiment will be briefly described.

In recent years, with the increase in size and complexity of LSI,
From the fear that the test of a board equipped with a plurality of LSIs will become extremely difficult, an F / F capable of scan operation is arranged for the input / output terminals forming the I / O section of each LSI, and the output from that LSI is output. Several years ago, a Boundary Scan Method was proposed, which makes it possible to directly observe data outside the board or to supply arbitrary data to the LSI from outside the board to facilitate board-level testing. Has become the IEEE standard 1149.1, and has reached the present. The term “boundary scan” refers to the scannable F / F (boundary scan) as described above.
The scan F / F is the peripheral edge (Boundar) of the LSI.
y) comes from where it is located. In any case, from the viewpoint of easy test at the board level, it is becoming more likely that registers and F / Fs will be placed in the I / O section of the LSI in the future. The example would be extremely feasible.

Now, as shown in FIG. 5, inside the LSI 50, the logic circuit block (DU) which is the target of BIST.
T) 51, input test data generation circuit block 52,
Three types of boundary scan circuits (hereinafter referred to as BSC).
Blocks 53, 54, 55 and a clock generation circuit 56 are provided respectively. Here, the test data generating circuit block 52 is, for example, as shown in FIG. 4 or FIG.
It is an LFSR based on the configuration shown in FIG. In addition, B.
S. C. Blocks 53, 54, 55 are connected to each other,
For example, one LFSR is configured based on the configuration shown in FIG. 1 and functions as the test result determination circuit 57. The logic circuit block 51 has an input terminal portion 71, and this input terminal portion 71 is connected to the output terminal portion 72 of the test data generating circuit. Further, the logic circuit block 51 has output terminal portions 73, 74, and 75, and the output terminal portion 73 is a B.I.
S. C. The input terminal portion 76 of the block 53 is connected to the output terminal portion 74 of the B. S. C. In the input terminal section 77 of the block 54,
The output terminal portion 75 is a B.I. S. C. The input terminals 78 of the block 55 are respectively connected.

During BIST execution, the logic circuit block 51 receives the output of the input test data generation circuit block 52 as test input data, and outputs the response output based on this input data as B. S. C. A response output is given to the blocks 53 to 55.

B. S. C. Blocks 53 to 55 are BI
Boundary scan F inside each when executing ST
/ F operates in synchronization with different clock signals CLK1, CLK2, and CLK3 supplied from a clock generation circuit block 56 (described later), and as a whole, the LFS according to the present invention.
Configure R. Therefore, these B. S. C. One of the blocks contains a circuit element (not shown) for satisfying the signature compression condition according to the present invention, as shown in FIG. 1, for example. In addition, these B. S. C. The block has an FBI (feedback signal input) terminal or an FBO (feedback signal output) terminal for forming a linear feedback circuit. Also, B for boundary scan transfer
SI (Boundary Scan Input) pin and BSO
It has a (boundary scan output) terminal. B.
S. C. The BSI terminal of the block 53 is connected with a boundary scan output from another boundary scan circuit block (not shown), but the output is disconnected because a feedback signal is selected during the BIST operation. It has become. B. S. C. BS of block 55
The O terminal is a further B. S. C. It is connected to the BSI terminal of a block (not shown).

B. S. C. The internal configuration (for one bit) of the blocks 53 to 55 (for output terminals) is shown in FIG. Figure 6
F / F 60 is a boundary scan F / F used for a boundary scan operation, as shown in FIG.
In the parallel signature compression operation of the output from the UT, L
It is also used as an F / F that constitutes an FSR. The clock signal from the clock generation circuit block 56 is
It is supplied to the terminal C of F. The output terminal of the DUT (circuit under test, that is, the logic circuit block 51) is connected to the DI terminal, and in the normal operation given by S2 = 0, the LS via the multiplexer 63 and the DO terminal.
It is output to the output terminal (output pad: not shown) of I50.

When S0 = 0 and S1 = 1, the boundary scan operation is performed, and the B. S. C. Block 53 ~
The contents of the F / F corresponding to the F / F 60 of each bit in 55 are serially transferred. The output from the DUT (circuit under test, that is, the logic circuit block 51) is guided to the input of the LFSR, and when CLK = CLK1 ↑, CLK2 ↑, CLK3 ↑, B.B. S.
C. At blocks 53, 54 and 55, signature compression operations are performed. When S0 = 1 and S1 = 0,
By CLK1 ↑, CLK2 ↑, CLK3 ↑, B. S. C.
In the blocks 53, 54, 55, the output from the DUT can be latched. The F / F 61 is for preventing the data outside the LSI from being accidentally supplied to the outside of the LSI during the transfer of the boundary scan data using the boundary scan F / F 60. . The contents of the F / F 61 are as follows depending on the boundary scan operation mode.
After the necessary data is transferred to the scan F / F 60, it can be changed by raising the updating clock CLK-UD.

Further, the clock generation circuit 56 has an LS
The frequency of the basic clock input signal CLK0 from the outside of I50 is multiplied by a constant, and the cycle corresponding to the frequency multiplied by the constant is
A plurality of clocks (CLK1, CLK2, CLK3) to the inside of the LSI 50 having the smallest step size are generated. Circuit block 5
An example of the configuration of No. 6 is shown in FIG. 7 (when the frequency of CLK0 is quadrupled).

As shown in FIG. 7, this circuit block is
It is composed of a PLL (Phase Locked Loop) circuit 64, a 2-bit counter 65, and a 2-bit decoder 66.
The PLL circuit is a circuit that multiplies the frequency of the basic clock input signal CLK0 from the outside by an integer. Here, from the clock input signal CLK0, a clock signal CLK having a frequency four times that of
Is being generated. This signal CLK causes counter 6
5 is counted up. The decoder 66 sets only the clock outputs CLK1, CLK2, CLK3, and CLK4 to 1 for the output values 00, 01, 10, and 11 of the counter 65 (note that CLK4 is used in the LSI 50). Absent). The counter 65 has a reset signal RST = 1.
Initialization is performed so that 11 is output. FIG. 8 shows a timing chart of the clock signal obtained by the circuit shown in FIG.

Strictly speaking, however, signature compression at three types of clock edges as in this example is considerably improved as compared with the conventional example, but an extremely accurate check for the AC output delay of the DUT is slightly. difficult. When a stricter time resolution is required, for example, the PLL circuit in the circuit block 56 is used to generate a clock signal CLK having a higher frequency than that in the above embodiment, and the time step width between clock edges is made finer. LFSR
Need to apply to.

Incidentally, it is of course possible to implement a plurality of clocks supplied by the circuit block 56 above from outside the LSI through a plurality of pins. Further, although not particularly shown, it is also possible to implement a linear shift register (LFSR) capable of generating pseudo random numbers as shown in FIG. 4 as a test data generating circuit. At this time, the output of the test data generating circuit is led to the input terminal of the DUT.

The present invention can be applied to various circuits other than the embodiments described above. For example, in FIG.
BILBO (Built-In Logic Block Observer) shown in
Can be implemented for BIST uses the automatic test data generation circuit to DUT a large number of test data.
(The circuit under test), a large number of response outputs of the DUT for these are signature-compressed by LFSR, and finally L
This has the great advantage that it is possible to detect a fault simply by checking the result (signature) in the FSR, but on the flip side, it is impossible to know the cycle in which the DUT outputs an abnormal signal or its abnormal data. , It has a weak point that it involves considerable difficulty in diagnosing the failure location. BILBO is intended to overcome this weakness by adding a simple circuit to the LFSR so that the scan operation can be performed together with the signature compression. The operation of BILBO is defined by two types of control signals B ₁ and B ₂ , as can be seen from FIG.
When B ₁ = 1 and B ₂ = 1, normal operation is performed (each output Z _{1 to} Z ₈ from the DUT is latched in a separate D-type F / F),
When B ₁ = 1 and B ₂ = 0, it operates as a parallel input LFSR, and parallel signature compression is possible. Also, B ₁ =
When 0 and B ₂ = 0, the scan operation is performed. This BILBO
It can be easily understood that the present invention can be applied to the case where the internal F / F is applied to the case where the internal F / F operates in synchronization with different clocks. All such applications of the invention to circuits based on LFSR are to be included in the scope of the invention. Further, those obtained from the embodiment of the present invention by changing the level of circuit elements such as logic gates and transistors and changing the polarities of various signals are naturally within the scope of the present invention.

In the LFSR described in the above embodiment, since it is possible to generate pseudo-random numbers and execute signature compression by allowing the F / Fs to operate in synchronization with different clocks, for example, a plurality of F / Fs can be executed. It is possible to construct a high-performance BIST that has high area efficiency and can detect an AC output delay failure of the DUT inside the LSI that operates in synchronization with the clock and in the I / O part of the LSI where the signal changes at various timings. Like

[0056]

As described above, according to the present invention, a linear feedback shift register and a linear feedback shift register satisfying the conditions of pseudo-random number generation or linear feedback while including F / Fs that operate with different clocks are provided. A semiconductor integrated circuit device provided can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a linear feedback shift register according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the linear feedback shift register according to the first embodiment of the present invention.

3A and 3B are views for explaining a latch circuit included in a linear feedback shift register according to a second embodiment of the present invention, FIG. 3A is a configuration diagram thereof, and FIG. ) A circuit diagram of the clocked inverter shown in the figure.

FIG. 4 is a configuration diagram of a linear feedback shift register according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram of one bit of a basic circuit constituting a boundary scan circuit included in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a clock generation circuit included in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart of the clock generation circuit shown in FIG.

FIG. 9 is a configuration diagram showing a configuration of BILBO.

10 is a configuration diagram of a conventional linear feedback shift register, FIG. 10A is a configuration diagram of a linear feedback shift register as a test data generating circuit, and FIG. 10B is a linear diagram as a test result determination circuit. The block diagram of a feedback shift register.

[Explanation of symbols]

1, 2 ... Flip-flop, 3 ... Delay, 10-16
… Flip-flops 20-25… Exclusive OR gate
30-32 ... Exclusive OR gate, 40 ... Latch circuit, 50 ... LSI, 51 ... Logic circuit block, 52 ... Input test data generating circuit, 53-55 Boundary scan circuit, 56 ... Clock Generator circuit, 101, 102, 103 ...
A set of flip-flops, 200 ... Feedback circuit.

Claims (7)

[Claims] 1. A combination of a plurality of flip-flops that operate in synchronization with mutually different clocks, and establishment means for establishing a condition of pseudo-random number generation or linear feedback is inserted between these pairs of flip-flops. Is a linear feedback shift register. 2. The delay circuit for delaying an output signal output from a set of flip-flops so as to meet a condition of pseudo-random number generation or linear feedback, and inputting the signal to another set of flip-flops. The linear feedback shift register according to claim 1, wherein 3. The linear feedback shift register according to claim 2, wherein the delay circuit includes at least one of a flip-flop and a latch circuit. 4. A semiconductor integrated circuit chip including a set of a plurality of flip-flops which operate in synchronization with a plurality of clocks generated from inside or outside, and pseudo-random number generation between the sets of these flip-flops. , Or a linear feedback shift register in which establishment means for establishing a linear feedback condition is inserted, and an output of the linear feedback shift register is electrically connected to at least a terminal functioning as an input terminal of a semiconductor integrated circuit unit provided inside the chip. Integrated circuit device, wherein the linear feedback shift register functions as a test data generating circuit. 5. A semiconductor integrated circuit chip including a set of a plurality of flip-flops that operate in synchronization with a plurality of clocks generated either internally or externally, and generating pseudo-random numbers between the sets of flip-flops. , Or a linear feedback shift register in which establishment means for establishing a linear feedback condition is inserted, and an input of the linear feedback shift register is electrically connected to at least a terminal functioning as an output terminal of a semiconductor integrated circuit unit provided inside the chip. Integrated circuit device, wherein the linear feedback shift register functions as a test result determination circuit. 6. A clock generating means for receiving a basic clock from the outside of the semiconductor integrated circuit chip and generating a plurality of different clocks from the basic clock is further provided inside the chip, and the clock generating means comprises: 7. The frequency of the basic clock is multiplied by a constant, and the plurality of clocks are generated with a period corresponding to the frequency multiplied by the constant as a minimum step size. The semiconductor integrated circuit device described. 7. The semiconductor integrated circuit device according to claim 6, wherein the clock generating means includes a PLL circuit.