WO2024040892A1 - Apparatus for converting binary code into thermometer code, and electronic device - Google Patents

Abstract

The present application provides an apparatus for converting a binary code into a thermometer code, and an electronic device, having good performance. The apparatus for converting a binary code into a thermometer code comprises: a decoding module, used for converting a high-bit binary code of high n/2 bits in an n-bit binary code into a high-bit code of 2^n/2 bits, and converting a low-bit binary code of low n/2 bits in the n-bit binary code into a low-bit code of 2^n/2 bits, wherein the number of target code elements in the high-bit code is related to the value of the high-bit binary code, the number of target code elements in the low-bit code is related to the value of the low-bit binary code, the target code elements are 0 or 1, and n is a positive even number; and a combinatorial logic module, comprising multiple logic sub-modules, the multiple logic sub-modules having the same delay, and the multiple logic sub-modules being used for combining the code elements in the high-bit code and the code elements in the low-bit code to obtain a thermometer code corresponding to the n-bit binary code.

Description

Devices and electronic equipment for converting binary codes into thermometer codes

This application claims the priority of the Chinese invention application submitted to the China Patent Office on August 26, 2022, with the application number 202211032712.2 and the invention name "Device and Electronic Equipment for Converting Binary Codes to Thermometer Codes", the entire content of which is incorporated into this document by application. Applying.

Technical field

The present application relates to the field of electronic technology, and more specifically, to a device and electronic equipment for converting a binary code into a thermometer code.

Background technique

Binary code is the most commonly used digital code in digital circuits. It uses 2 as the base for counting and is commonly represented by symbols 0 and 1. Each symbol occupies 1 bit. In digital circuits, the implementation of logic gates directly uses binary, so modern computers and computer-dependent devices all use binary. Thermometer Code is a digital code with consistent weights for each bit. It is also composed of symbols 0 and 1, but the number of symbols 1 in the thermometer code corresponds to a decimal value, so it has good linearity and monotonicity. sex.

Since the thermometer code is long in length, consumes a lot of power and requires a large amount of memory, the thermometer code is inconvenient to calculate. Therefore, in some implementations, binary codes are used for calculation and then converted into Thermometer code is used. In this process, the conversion of binary code to thermometer code is very important.

In view of this, how to provide a device for converting binary codes to thermometer codes with better performance is an urgent technical problem to be solved.

Contents of the invention

This application provides a device and electronic equipment for converting a binary code into a thermometer code, which has better performance.

In a first aspect, a device for converting a binary code into a thermometer code is provided, including: a decoding module for converting the upper n/2-bit high-order binary code of the n-bit binary code into a 2 ^n/2 -bit high-order binary code, and converting The low n/2 bits of the low binary code in the n-bit binary code are converted into 2 ^n/2 bits of low bit code. Among them, the number of target symbols in the high bit code is related to the value of the high bit binary code. The number of target symbols in the low bit code is Quantity and The value of the low-order binary code is related, the target symbol is 0 or 1, and n is a positive even number; the combinational logic module includes multiple logical sub-modules, the delays of the multiple logical sub-modules are the same, and the multiple logical sub-modules are used to The code elements in the high-bit code are combined with the code elements in the low-bit code to obtain the thermometer code corresponding to the n-bit binary code.

Through the technical solution of the embodiment of the present application, a device for converting a binary code to a thermometer code including a decoding module and a combinational logic module is provided. Through the decoding module, not only can the n-bit binary code be split into two parts, respectively Processing is carried out in order to improve the processing efficiency of the high-bit code and low-bit code corresponding to the binary code by the subsequent combinational logic module. The value of the high-bit code and the low-bit code can also be reflected in the high-bit code and the low-bit code respectively through the number of target code elements. code value, thus facilitating the logical design of subsequent combinational logic modules. Furthermore, through the combinational logic module, which is formed by multiple logic sub-modules with the same delay, the overall complexity of the combinational logic module can be reduced, and it has good adaptability and accuracy for the conversion of high-digit binary codes to thermometer codes. It is scalable and can ensure the synchronous output of each code element in the thermometer code, which will not cause logical errors in subsequent circuits, and comprehensively guarantees the performance of the device for converting binary codes to thermometer codes.

In some possible implementations, the number of target code elements in the above-mentioned high-bit code is related to the value of the high-bit binary code, including: the 0th to u-th bits in the high-bit code are the target code elements, and the high-bit code except the 0th bit Bits other than the u-th bit are non-target code elements, where u is the value of the high-order binary code, 0≤u≤2 ^n/2 -1; the number of target code elements in the above-mentioned low-order code and the value of the low-order binary code Related include: the 0th to vth bits in the low-order code are target code elements, and the other bits in the low-order code except the 0th to v-th bits are non-target code elements, where v is the value of the low-order binary code , 0≤v≤2 ^n/2 -1; when the target symbol is 1, the non-target symbol is 0, or, when the target symbol is 0, the non-target symbol is 1.

In some possible implementations, the decoding module includes multiple identical decoding sub-modules, and the multiple identical decoding sub-modules are used to convert high-bit binary codes and low-bit binary codes to obtain high-bit codes and low-bit codes.

In some possible implementations, the decoding module includes two identical decoding sub-modules. The first decoding sub-module of the two identical decoding sub-modules is used to convert the high-order binary code to obtain the high-order code. The second decoding sub-module among the same decoding sub-modules is used to convert the low-order binary code to obtain the low-order code.

In some possible implementations, the multiple logical sub-modules include: 2 ⁿ -1 first logical sub-modules and a second logical sub-module, and a second logical sub-module is used to convert the 0th bit in the thermometer code The code element output is the preset code element, the 2 ⁿ -1 first logic sub-modules are the same, and are used to combine the code elements in the high-order code and the code elements in the low-order code to output the first code element in the thermometer code to The 2 ⁿ -1 bit code element.

In some possible implementations, the 2 ⁿ -1 first logical sub-modules include 2 ^n/2 groups of first logical sub-modules, wherein each first logical sub-module in the i-th group of first logical sub-modules is Multiple intermediate results are obtained based on the i-th code element in the high-bit code and multi-bit code elements in the low-bit code, and multiple intermediate results in the thermometer code are obtained based on the multiple intermediate results and the i+1-th code element in the high-bit code. Bit symbol, where 0≤i≤2 ^n/2 -1, i is an integer.

In some possible implementations, when 0<i≤2 ^n/2 -1, the i-th group of first logical sub-modules includes 2 ^n/2 first logical sub-modules, and when i=0 , the i-th group of first logical sub-modules includes 2 ^n/2 -1 first logical sub-modules, wherein the j-th first logical sub-module in the i-th group of first logical sub-modules is used to generate data according to the high-order code The j-th intermediate result among multiple intermediate results is obtained from the i-th symbol in and the j-th symbol in the low-order code, and based on the j-th intermediate result and the i+1-th symbol in the high-order code, we obtain The (i*2 ^n/2 +j)th code element in the thermometer code, where, when 0＜i≤2 ^n/2 -1, 0≤j≤2 ^n/2 -1, when i＝ In the case of 0, 0<j≤2 ^n/2 -1, and j is an integer.

In some possible implementations, the target symbol is 1, the non-target symbol is 0, and the j-th first logical sub-module is used to combine the i-th symbol in the high-order code with the j-th code in the low-order code. The element executes AND logic to obtain the jth intermediate result, and performs OR logic between the jth intermediate result and the i+1th bit symbol in the high-order code to obtain the (i*2 ^n/2 +j)th bit in the thermometer code. code element.

In some possible implementations, the target symbol is 0, the non-target symbol is 1, and the j-th first logical sub-module is used to combine the i-th symbol in the high-order code with the j-th code in the low-order code. The element performs OR logic to obtain the jth intermediate result, and performs NAND logic on the jth intermediate result and the i+1th bit symbol in the high-order code to obtain the (i*2 ^{n/2 +j)th (i*2 n/2} +j) in the thermometer code. bit code element.

In some possible implementations, the decoding module and/or the combinational logic module is a logic circuit including logic gates.

In some possible implementations, the decoding module includes a decoder circuit, and the number of logic gates between any input terminal in the decoder circuit and any output terminal connected to the input terminal is the same.

In some possible implementations, the decoding module includes two decoder circuits with the same structure. When n=4, the decoder circuit includes two circuit input terminals and four circuit output terminals. The two circuits The input terminal is used to input a 2-bit high-order binary code or a low-order binary code, and the four circuit output terminals are used to output a 4-digit high-order binary code or low-order code; among the four circuit output terminals, the first circuit output terminal is connected to the buffer gate, with The zeroth preset symbol in the output high-order code or low-order code; the input terminal of the two circuits The first circuit input terminal and the second circuit input terminal are connected to the input terminal of the NOR gate, the output terminal of the NOR gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the four circuit output terminals. The second circuit output terminal is used to output the first symbol of the high-order code or the low-order code; the second circuit input terminal of the two circuit input terminals is connected to the input terminal of the second NOT gate, and the second circuit input terminal of the second NOT gate The output terminal is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate is connected to the third circuit output terminal among the four circuit output terminals for outputting the second code element of the high-order code or the low-order code; two The first circuit input terminal and the second circuit input terminal among the circuit input terminals are connected to the input terminal of the NAND gate, the output terminal of the NAND gate is connected to the input terminal of the fourth NOT gate, and the output terminal of the fourth NOT gate is connected to The fourth circuit output terminal among the four circuit output terminals is used to output the third code element of the high-order code or the low-order code.

In some possible implementations, the combinational logic module includes: a combinational logic circuit, the combinational logic circuit includes 2 ⁿ -1 first logic subcircuits and a second logic subcircuit, and a second logic subcircuit is used to combine the thermometer The 0th code element in the code is output as a preset code element. The circuits of the 2 ⁿ -1 first logic sub-circuits are the same and are used to combine the code elements in the high-bit code and the code elements in the low-bit code to output the thermometer. The 1st code element to the ²ⁿ -1th code element in the code.

In some possible implementations, the delay of any one of the 2 ⁿ -1 first logic sub-circuits is the same as the delay of a second logic sub-circuit.

In some possible implementations, the first logic sub-circuit includes three circuit input terminals and one circuit output terminal, and the first circuit input terminal and the second circuit input terminal among the three circuit input terminals are used to input high-order binary codes. 2 symbols, the third circuit input terminal among the three circuit input terminals is used to input 1 symbol in the low-order binary code, and the circuit output terminal is used to output 1 symbol in the thermometer code; in the target symbol When it is 1, the first circuit input terminal and the third circuit input terminal are connected to the input terminal of the AND gate, the output terminal of the AND gate and the second circuit input terminal are connected to the input terminal of the OR gate, and the output terminal of the OR gate is connected to at the output end of the circuit, or, when the target symbol is 0, the first circuit input end and the third circuit input end are connected to the input end of the OR gate, and the output end of the OR gate and the second circuit input end are connected to the AND The input terminal of the NOT gate and the output terminal of the NAND gate are connected to the output terminal of the circuit.

In some possible implementations, the decoding module and/or the combinational logic module are functional modules in a digital chip.

In some possible implementations, the thermometer code is used to input the control module, so that the control module implements the control function according to the thermometer code.

In a second aspect, an electronic device is provided, including: a control module, and the device in the first aspect or any possible implementation manner in the first aspect, the device is used to convert a 2 ^n- bit binary code into a According to the thermometer code, the control module is used to receive the thermometer code and implement the control function according to the thermometer code.

In some possible implementations, the electronic device includes an LC oscillation circuit, the LC oscillation circuit includes 2 ⁿ capacitors with the same capacitance value, the control module includes a switch array composed of 2 ⁿ switches, and each switch in the switch array is connected Based on a capacitor, the switch array is used to receive the thermometer code and control the number of working capacitors in the LC oscillation circuit according to the thermometer code.

Description of drawings

Figure 1 is a schematic diagram of a binary code to thermometer code conversion circuit provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of another binary code to thermometer code conversion circuit provided by an embodiment of the present application.

Figure 3 is a schematic structural block diagram of a device for converting a binary code into a thermometer code provided by an embodiment of the present application.

Figure 4 is a schematic structural block diagram of a decoding module provided by an embodiment of the present application.

FIG. 5 is a schematic logic circuit diagram of a 2-line to 4-line decoder circuit provided by an embodiment of the present application.

Figure 6 is a schematic structural block diagram of a combinational logic module provided by an embodiment of the present application.

FIG. 7 is a schematic structural block diagram of another combinational logic module provided by an embodiment of the present application.

Figure 8 is a schematic structural block diagram of the i-th group of first logical sub-modules provided by the embodiment of the present application.

Figure 9 is a schematic structural block diagram of another combinational logic module provided by an embodiment of the present application.

Figure 10 is a schematic logic circuit diagram of a first logic sub-module provided by an embodiment of the present application.

Figure 11 is a schematic logic circuit diagram of another first logic sub-module provided by an embodiment of the present application.

Figure 12 is a schematic structural block diagram of another device for converting a binary code into a thermometer code provided by an embodiment of the present application.

Detailed ways

The technical solutions in this application will be described below with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a binary code to thermometer code conversion circuit 100 provided by an embodiment of the present application.

As shown in Figure 1, the binary code to thermometer code conversion circuit includes three input terminals and seven output terminals. The three input terminals are used to receive the three code elements B ₀ to B ₂ of the binary code respectively. The seven output terminals The terminal is used to output the seven code elements T ₁ to T ₇ of the thermometer code respectively. The circuit shown in Figure 1 can also be called a 3-line to 7-line binary code to thermometer code circuit.

Through this 3-wire to 7-wire binary code to thermometer code conversion circuit, Table 1 below shows the truth table of decimal, binary code and thermometer code.

Table 1

In the embodiment shown in Figure 1, the outputs from B ₀ to B ₂ to T ₃ and T ₅ need to pass through four-level logic gates, while the outputs from B ₀ to B ₂ only need to go through two-level logic gates. Therefore, the The output of _T3 and _T5 has a large delay, which not only limits the conversion rate of the thermometer code, but the difference in delay between _T3 and _T5 and other signals will also cause logic errors in subsequent circuits.

In addition, in the embodiment shown in FIG. 1 , the logic gate circuit is relatively complex and there are many wire crossings, which results in higher power consumption, more complex layout design and higher process cost of the circuit. As the number of binary code bits increases, the above problems such as delay, power consumption, and cost will become more serious.

In addition to the above-mentioned embodiment shown in Figure 1, in some other binary code to thermometer code circuits, such as the 2-line to 3-line binary code to thermometer code circuit 200 shown in Figure 2, although the transistors Mn ₁ , Mp ₁ , The number of Tg ₁ , Tg ₂ , Tg ₃ and INV is small, but there will still be problems such as inconsistent delays from the input end (B ₀ to B ₁ ) to the output end (T ₁ to T ₃ ) and more complex circuits, causing this The binary code to thermometer code circuit shown in Figures 1 and 2 does not perform well.

In view of this, the present application provides a new binary code to thermometer code conversion device, which has better performance than the above-mentioned binary code to thermometer code conversion circuits 100 and 200 .

FIG. 3 shows a schematic structural block diagram of a device 300 for converting a binary code into a thermometer code provided by an embodiment of the present application.

As shown in FIG. 3 , the device 300 for converting binary codes to thermometer codes includes: a decoding module 310 and a combinational logic module 320 . Specifically, the decoding module 310 is used to convert the upper n/2-bit high-order binary code of the n-bit binary code into a 2 ^n/2- bit high-order binary code, and convert the low-order n/2 bits of the n-bit binary code into the low-order binary code. The code is converted into a low-bit code of 2 ^n/2 bits. Among them, the number of target code elements in the high-bit code is related to the value of the high-bit binary code. The number of target code elements in the low-bit code is related to the value of the low-bit binary code. n is a positive even number. .

The combinational logic module 320 includes multiple logical sub-modules, and the multiple logical sub-modules have the same delay. And the plurality of logic sub-modules are used to combine the code elements in the above-mentioned high-order code and the code elements in the low-order code to obtain the thermometer code corresponding to the n-bit binary code.

Through the technical solution of the embodiment of the present application, a device 300 for converting a binary code into a thermometer code including a decoding module 310 and a combinational logic module 320 is provided. Through the decoding module 310, not only the n-bit binary code can be split It is divided into two parts and processed separately, so as to improve the processing efficiency of the high-bit code and low-bit code corresponding to the binary code by the subsequent combination logic module 320. The high-bit code can also be reflected in the high-bit code and the low-bit code by the number of target symbols. and the value of the low-order binary code, thus facilitating the subsequent logic design of the combinational logic module 320. Furthermore, through the combinational logic module 320, which is formed by multiple logic sub-modules with the same delay, the overall complexity of the combinational logic module can be reduced, and it has good adaptability for the conversion of high-digit binary codes to thermometer codes. and scalability, and can ensure the synchronous output of each symbol in the thermometer code, without causing logical errors in subsequent circuits, and comprehensively guarantee the performance of the device 300 for converting binary codes to thermometer codes.

Optionally, in some implementations, the decoding module 310 and/or the combinational logic module 320 may be a logic circuit including logic gates. Specifically, the decoding module 310 may be a decoder logic circuit including at least one logic gate, and the combinational logic module 320 may be a combinational logic circuit including at least one logic gate. The logic gates include but are not limited to: AND gate, OR gate, NOT gate, NAND gate, NOR gate, XOR gate or XOR gate, etc.

Or, in other embodiments, the decoding module 310 and/or the combinational logic module 320 can also be a functional module in a digital chip. The functional module can include a software module and a hardware module in the digital chip, and the two cooperate with each other to achieve Implement the logical functions of the decoding module 310 and/or the combinational logic module 320. The hardware module can be an integrated circuit in a digital chip, and the software module can be a program code, which can be stored in the digital chip, or can be stored outside the digital chip. The digital chip includes Field Programmable Gate Array (FPGA) chip, Complex Programmable Logic Device (CPLD) chip, etc. The logic program code in the digital chip can be written through the verilog hardware description language (Hardware Description Language, HDL) to write.

As an example, this application mainly uses the decoding module 310 and the combinational logic module 320 as logic circuits for detailed description. When the decoding module 310 and the combinational logic module 320 are functional modules in a digital chip, the logic program code can be used to cooperate with the integrated circuit. To realize the function of the logic circuit, this application does not limit the specific implementation method of the logic program code.

For the decoding module 310, it can be used to receive n-bit binary codes, where n is a positive even number, The highest bit of the even-digit binary code may be "0". Optionally, in some implementations, a processing module (eg, a digital chip) may provide an n-bit binary code to the decoding module 310. When the actual binary code is an odd number of digits, the processing module may generate an n-bit binary code at the end of the actual binary code. The highest bit is filled with "0" to form an even-numbered binary code. For example, if the actual binary code is 111, the processing module can add "0" before "111" to form an even-numbered binary code "0111". The process of filling the highest bit with "0" will not affect the actual value of the binary code, and is also beneficial to the processing of the binary code in the decoding module 310.

Specifically, the decoding module 310 is used to decode the high-order n/2 bits of the n-bit binary code into a 2 ^n/2- bit high-order binary code, and convert the n-bit binary code to the low n/2 bits. The 2-bit low-order binary code is decoded to form a 2 ^n/2- bit low-order code. Among them, the number of target code elements in the high-bit code can reflect the value of the high-bit binary code, and the number of target code elements in the low-bit code can reflect the value of the low-bit binary code. The target code element can be 1 or 0.

Through this decoding process, not only can the n-bit binary code be split into two parts for processing respectively, so as to improve the conversion efficiency of the binary code by subsequent modules, but also the target symbol can be passed through the high-bit code and low-bit code. The quantities respectively reflect the value of the high-order binary code and the value of the low-order binary code, which is beneficial to the logic design of the subsequent module and facilitates the subsequent module to convert the binary code into a thermometer code based on the code elements of the high-order code and low-order code.

Further, the combinational logic module 320 includes multiple logic sub-modules with the same delay. The thermometer code corresponding to the n-bit binary code can be obtained by combining the symbols in the high-order code and the symbols in the low-order code decoded by the above-mentioned decoding module 310 through the multiple logical sub-modules. Specifically, for each logic sub-module, the delay may be the time required for a signal to be transmitted from the input end of the logic sub-module to the output end.

The combinational logic module 320 may include multiple logic sub-modules. The structure of each logic sub-module is easy to implement simply and clearly, and has good adaptability and scalability for converting high-digit binary codes to thermometer codes. Moreover, the multiple logic sub-modules have the same delay, thereby ensuring the synchronous output of each symbol in the thermometer code, without causing logical errors in subsequent circuits, and ensuring the performance of the device 300 for converting binary codes to thermometer codes.

Figure 4 shows a schematic structural block diagram of a decoding module 310 provided by an embodiment of the present application.

As shown in Figure 4, the decoding module 310 includes two identical first decoding sub-modules 311 and second decoding sub-modules 312, where the first decoding sub-module 311 is used to convert the n-bit binary code into high n The /2-bit high-order binary code is converted into a 2 ^n/2- bit high-order code. The second decoding submodule 312 is used to convert the low-order n/2-bit low-order binary code of the n-bit binary code into a 2 ^n/2 -bit high-order binary code. Low code.

As an illustration, in Figure 4, the lower n/2 bits in the n-bit binary code are represented as B ₀ to B _n/2-1 respectively, and the B ₀ to B _n/2-1 form an n/2-bit Low binary code. The n/2-bit low-order binary code is converted by the second decoding sub-module 312 to form a low-order code Low<2 ^n/2 -1:0>. The low-order code Low<2 ^n/2 -1:0> includes 2 ^n/2 bits, the lowest bit can be expressed as Low ₀ and the highest bit can be expressed as Low ₂ ^n/2 _-1 .

Optionally, in some implementations, in the low code Low<2 ^n/2 -1:0>, from the 0th bit Low ₀ to the vth bit Low _v are the target code elements, and the low code Low<2 ^n/2 -1:0> The other bits except the 0th bit Low ₀ to the vth bit Low _v are non-target code elements, where v can be the value of the low-order binary code, 0≤v≤2 ^n/2 -1 .

For example, when the target symbol is "1" and the non-target symbol is "0", if the low-order binary code is 01, the value of the low-order binary code is 1, and the second decoding sub-module 312 The low-order code Low<3:0> obtained after converting the low-order binary code 01 can be 0011. Among them, the 0th to 1st bits of the low-order code 0011 are the target code element "1", and the 2nd and 3rd bits are the non-target code element "0". The target code element "1" in the low-order code 0011 is It can reflect the value of low-order binary code 01.

Or, when the target symbol is "0" and the non-target symbol is "1", if the low-order binary code is 11, the value of the low-order binary code is 3, and the second decoding sub-module 312 will The low code Low<3:0> obtained after code 11 is converted can be 0000. Among them, the 0th to 3rd bits of the low-order code 0000 are all target code elements "0", and the target code element "0" in the low-order code 0000 can reflect the value of the low-order binary code 11.

Similarly, in Figure 4, the upper n/2 bits in the n-bit binary code are represented as B _n/2 to B _n-1 respectively, and the B _n/2 to B _n-1 form the upper binary code. The n/2-bit high-order binary code is converted by the first decoding sub-module 311 to form a high-order code High<2 ^n/2 -1:0>. The high-order code High<2 ^n/2 -1:0> includes 2 ^n/2 bits, the lowest bit can be expressed as High ₀ , and the highest bit can be expressed as High ₂ ^n/2 _-1 .

Optionally, in some implementations, in the high-bit code High<2 ^n/2 -1:0>, from the 0th bit High ₀ to the u-th bit High _u are the target code elements, and the high-bit code High<2 ^n/2 The other bits in -1:0> except the 0th bit High ₀ to the u-th bit High _u are non-target code elements, where u can be the value of the high-order binary code, 0≤u≤2 ^n/2 -1.

For example, when the target symbol is "1" and the non-target symbol is "0", if the high-order binary code is 10, the value of the high-order binary code is 2, and the first decoding sub-module 311 The high-bit code High<3:0> obtained after converting the high-bit binary code 10 can be 0111. Among them, the high-digit code 0111 is Bits 0 to 2 are all target code elements "1", while bit 3 is the non-target code element "0". The target code element "1" in the high-order code 0111 can reflect the value of the high-order binary code 10.

Or, when the target symbol is "0" and the non-target symbol is "1", if the high-order binary code is 10, the value of the high-order binary code is 2, and the first decoding sub-module 311 The high bit code High<3:0> obtained after code 10 is converted can be 1000. Among them, the 0th to 2nd bits of the high-bit code 1000 are all target code elements "0", and the 3rd bit is the non-target code element "1". The target code element "0" in the high-bit code 1000 can reflect the high-bit code The value of binary code 10.

Through the technical solution of the embodiment of the present application, the decoding module 310 uses two identical decoding sub-modules (the first decoding sub-module 311 and the second decoding sub-module 312) to respectively decode the upper n/2 bits of the n-bit binary code. The high-bit binary code and the low n/2-bit low-bit binary code are converted into 2 ^n/2- bit high-bit code and low-bit code. The logical structure of each decoding sub-module can be relatively simple, which can reduce the overall cost of the decoding module 310. The design complexity is high, and the same decoding sub-module has the same delay, so as to ensure that the high-order code and the low-order code can be output synchronously to ensure the normal operation of subsequent modules.

Furthermore, in the high-order code and low-order code converted by the two decoding sub-modules, the target symbols are continuously arranged in the low-order bits. The number of the low-order target symbols can respectively represent the values of the high-order binary code and the low-order binary code, so that This further facilitates the subsequent logical design of the combinational logic module 320 and ensures the generation of thermometer codes.

Optionally, in the example of the above embodiment, the high-order binary code or the low-order binary code input by the decoding sub-module (the first decoding sub-module 311 or the second decoding sub-module 312) may be 2 bits, and The high-order code or low-order code output by the decoding sub-module is 4 bits. In this case, the decoding sub-module may be a 2-line to 4-line decoder circuit.

As an example, FIG. 5 shows a schematic logic circuit diagram of a 2-line to 4-line decoder circuit 400 provided by an embodiment of the present application. The 2-line to 4-line decoder circuit 400 may be suitable for the above-mentioned first decoding sub-module 311 and/or the second decoding sub-module 312.

As shown in Figure 5, the 2-wire to 4-wire decoder circuit 400 includes: two circuit input terminals in0 and in1, and four circuit output terminals out0 to out3. The two circuit input terminals in0 and in1 can be used to input a 2-bit binary code, and the four circuit output terminals out0 to out3 can be used to output a 4-bit high-order code or a low-order code. Specifically, the two circuit input terminals in0 and in1 are used to respectively input the low and high bits of the 2-bit binary code, and the four circuit output terminals out0 to out3 are used to respectively output the 4-bit high-bit code from the low to the high bits. or low code.

Optionally, the logic between the two input terminals in0 and in1 and the four output terminals out0 to out3 The gate circuit can include four types of logic gates: NOT gate inv, NOR gate nor, AND gate nand, and buffer gate buffer.

Specifically, as shown in Figure 5, the first circuit output terminal out0 among the four circuit output terminals can be connected to the buffer gate buffer and is used to output the zeroth preset symbol in the high-order code or the low-order code. The zeroth preset symbol may be a target symbol. As an example, the decoder circuit 400 can generate a signal "0" internally, and the signal "0" passes through the fifth inverter gate inv5 and the buffer gate buffer and outputs the zeroth preset symbol as "1".

Among the two circuit input terminals, the first circuit input terminal in0 and the second circuit input terminal in1 are connected to the input terminal of the NOR gate nor, and the output terminal of the NOR gate nor is connected to the input terminal of the first NOT gate inv1. The output terminal of a NOT gate inv1 is connected to the second circuit output terminal out1 among the four circuit output terminals, and is used to output the first symbol of the high-order code or the low-order code.

The second circuit input terminal in1 of the two circuit input terminals is connected to the input terminal of the second invertor inv2, and the output terminal of the second invertor inv2 is connected to the input terminal of the third invertor inv3. The output terminal is connected to the third output terminal out2 among the four output terminals, and is used to output the second code element of the high-order code or the low-order code.

Among the two circuit input terminals, the first circuit input terminal in0 and the second circuit input terminal in1 are connected to the input terminal of the NAND gate nand, and the output terminal of the NAND gate nand is connected to the input terminal of the fourth invert gate inv4. The output terminal of the four-NOT gate inv4 is connected to the fourth output terminal out3 among the four output terminals, and is used to output the third code element of the high-order code or the low-order code.

Through the decoder circuit 400 shown in the embodiment shown in FIG. 5, the 2-bit binary code can be converted into a 4-bit high-order code or a low-order code. The high-order code or low-order code starts from the 0th bit to The k-th bits are all target symbols "1", where k can represent the value of a 2-bit binary code, 0<k<2 ^n/2 .

Optionally, the above-described decoder circuit 400 can be understood as a shift decoder circuit. When the target symbol is "1", the default output of the shift decoder circuit is 1, that is, regardless of the input What is the value of the binary code? The lowest bit of the output of the shift decoder circuit is 1 by default. When the value of the input binary code is x, the lowest bit "1" is copied and moved to the left by output. For example, for the 2-line to 4-line decoder circuit 400, when the value of the input binary code is 0, the lowest bit "1" is copied and moved to the left by 0 bits and the high bit is filled with "0", that is, to the left Carry 0 "1"s and fill the high bits with "0", and output 0001. When the value of the input binary code is 1, the lowest bit "1" is copied and moved 1 bit to the left and the high bits are filled with "0", that is, carry to the left 1 "1" and the high bit is filled with "0", output 0011, when the value of the input binary code is 2, the lowest bit "1" is copied and moved 2 bits to the left and the high bit is filled with "0", that is, 2 "1"s are carried to the left and the high bit is filled with "0", and 0111 is output.

Or, when the target symbol is "0", the default output of the shift decoder circuit is 0, that is, no matter what the value of the input binary code is, the lowest bit of the output of the shift decoder circuit defaults to is 0. When the value of the input binary code is x, the lowest bit "0" is copied and moved to the left by x bits and the high bit is supplemented with "1", thus forming the final output of the shift decoder circuit. For example, for the 2-line to 4-line decoder circuit 400, when the value of the input binary code is 0, the lowest bit "0" is copied and moved to the left by 0 bits and the high bit is supplemented with "1", and 1110 is output. When the value of the input binary code is 1, the lowest bit "0" is copied and moved 1 bit to the left and the high bit is filled with "1", that is, one "0" is carried to the left and the high bit is filled with "1", and 1100 is output. When input When the value of the binary code is 2, the lowest bit "0" is copied and moved 2 bits to the left and the high bit is filled with "1", that is, 2 "0"s are carried to the left and the high bit is filled with "1", and 1000 is output.

Through the decoder circuit 400 in the embodiment shown in Figure 5 above, the circuit implementation is relatively simple, and the delay of each output end is the same, thereby ensuring that the high-order code and the low-order code can be output synchronously to ensure the normal operation of subsequent modules.

It should be noted that the above Figure 5 is only an example and not a limitation, introducing the circuit structure of a 2-line to 4-line decoder circuit 400. The 2-line to 4-line decoder circuit 400 can also be configured through other circuits. The structure (for example: other types of logic gates) implements the decoding function so that the number of target symbols in the 4-bit decoding output by the decoder circuit 400 can represent the value of the 2-bit binary code. This application The embodiment does not limit the specific circuit structure of the 2-line to 4-line decoder circuit 400.

In addition, when the input and output of the decoder circuit are respectively 3 lines to 8 lines, 4 lines to 16 lines, or other more input lines and output lines, the decoder circuit can also be based on the above 2 lines to 4 lines. The design principles of the decoder circuit 400 are used to carry out corresponding circuit design. In the embodiment of the present application, the circuit structure of the decoder circuit with 3 lines to 8 lines, 4 lines to 16 lines or other more input lines to output lines is no longer required. Be specific.

Optionally, in the embodiment shown in FIG. 5 , the number of logic gates between any input terminal and any output terminal connected to the input terminal is the same. Therefore, any input terminal of the decoder circuit 400 and Any output connected to this input has the same delay. Through this technical solution, the decoder circuit 400 can ensure the synchronous output of each symbol without causing logical errors in the subsequent module, that is, the combinational logic module 320, and comprehensively ensure the performance of the device 300 for converting binary codes to thermometer codes.

Optionally, in the above embodiment, the decoding module 310 may include two identical decoding sub-modules 311 and 312. The first decoding sub-module 311 of the two decoding sub-modules is used to decode high-order binary data. The code is converted to obtain a high-bit code, and the second decoding sub-module 312 is used to convert the low-bit binary code to obtain a low-bit code. Through the technical solution of this embodiment, the logical structures of the first decoding sub-module 311 and the second decoding sub-module 312 can be relatively simple, reducing the overall design complexity of the decoding module 310, and decoding sub-modules with the same structure have The same delay ensures that the high-bit code and the low-bit code can be output synchronously to ensure the normal operation of subsequent modules.

In some alternative implementations, the decoding module 310 may also include other numbers of multiple identical decoding sub-modules, which are used to convert the high-order binary code and the low-order binary code to obtain the high-order binary code. code and low-order code, the embodiment of the present application does not limit the specific number of sub-modules of the decoding module 310.

The decoding module 310 provided by the embodiment of the present application has been described above with reference to Figures 4 and 5. The combinational logic module 320 provided by the embodiment of the present application will be described below with reference to Figures 6 to 10.

Figure 6 shows a schematic structural block diagram of a combinational logic module 320 provided by the embodiment of the present application.

As shown in Figure 6, in the combinational logic module 320 of this embodiment, the multiple logical sub-modules include: ²ⁿ -1 first logical sub-modules 321 and one second logical sub-module 322. Specifically, the multiple The logical sub-module is composed of 2 ⁿ -1 first logical sub-modules 321 and one second logical sub-module 322 . The second logical sub-module 322 is used to output the 0th symbol en<0> in the thermometer code as a preset symbol. The 2 ⁿ -1 first logical sub-modules 321 are the same and are used to convert the above-mentioned translation The code elements in the converted high-order code and the code elements in the low-order code are combined by the code module 310 to output the 1st to ²ⁿ -1th code elements en< ²ⁿ -1:1> in the thermometer code. Through the combinational logic module 320, a 2 ^n- bit thermometer code corresponding to the n-bit binary code can be obtained.

Optionally, in this embodiment of the present application, the preset symbol output by the second logic sub-module 322 may be “0”. The combinational logic module 320 combining the 2 ⁿ -1 first logic sub-modules 321 and one second logic sub-module 322 can ensure the conversion accuracy of the combinational logic module 320 in converting high-order codes and low-order codes into thermometer codes.

In addition, 2 ⁿ -1 first logic sub-modules 321 combine the symbols in the high-order code and the symbols in the low-order code to output other symbols of the thermometer code except the 0th bit symbol. The 2 ⁿ -1 The first logic sub-module 321 is used to analyze the target symbols in the high-order code and the low-order code, so as to convert the accurate thermometer code.

To sum up, in the embodiment of the present application, by combining 2 ⁿ -1 first logic sub-modules 321 and one second logic sub-module 322 in the logic module 320, a complete and accurate thermometer code can be converted, The performance of the device 300 for converting binary codes to thermometer codes is comprehensively guaranteed.

Combining the embodiment shown in Figure 6 with the embodiment shown in Figure 4 above, the input of each first logic sub-module 321 in the 2 ⁿ -1 first logic sub-modules 321 in the embodiment shown in Figure 6 The terminals are connected to the output terminal of the first decoding sub-module 311 and the output terminal of the second decoding sub-module 312, so that each first logical sub-module 321 can receive the high-order code output by the first decoding sub-module 311. and the low-order code output by the second decoding sub-module 312.

Based on the embodiment shown in FIG. 6 above, FIG. 7 shows a schematic structural block diagram of another combinational logic module 320 provided by an embodiment of the present application.

As shown in Figure 7, in this embodiment, the above-mentioned 2 ⁿ -1 first logical sub-modules 321 include 2 ^n/2 groups of first logical sub-modules. Specifically, the 2 ⁿ -1 first logical sub-modules 321 consists of 2 ^n/2 groups of first logical sub-modules. Wherein, each first logical sub-module 321 in the i-th group of first logical sub-modules is used to obtain multiple intermediate results based on the i-th symbol in the above-mentioned high-bit code and the multi-bit symbols in the above-mentioned low-bit code, and The multi-bit code elements in the thermometer code are obtained based on the multiple intermediate results and the i+1th code element in the high-order code, where 0≤i≤2 ^n/2 -1 and i is an integer.

Each group of first logic sub-modules among the 2 ^n/2 groups of first logic sub-modules can be used to output a group of code elements of the thermometer code. As an example, as shown in Figure 7, the i-th group of first logical sub-modules can be used to output the i-th group of symbols en _i of the thermometer code. Each code element in the i-th group of code elements en _i can be determined according to the i-th code element ^High i, the i+1-th code element High i+ ₁ and the high-order code High<2 n/ _{2 -1:0} >. One symbol in the low code Low<2 ^n/2 -1:0> is obtained.

It should be noted that in the embodiment of the present application, for the 2 ^n/2 -1 group of first logical sub-modules, it needs to receive High ₂ ^n/2 _-1 and High ₂ ^n/2 , where High ₂ ^{n/ 2} _-1 is the highest code element in the high-bit code, and High ₂ ^n/2 is not a code element in the high-bit code, but can be a preset code element, for example, it can be 0.

The code elements en ₀ to en ₂ n/ ² _-1 output by the 2 ^n/2 groups of first logic submodules in the embodiment shown in Figure 7 are connected in sequence from low bits to high bits to form the final output thermometer code.

Optionally, in the 2 ^n/2 groups of first logical sub-modules shown in Figure 7 above, in the case of 0<i≤2 ^n/ 2-1, the i-th group of first logical sub-modules includes 2 ^{n/ 2} first logical sub-modules 321. When i=0, the i-th group of first logical sub-modules (ie, the 0th group of first logical sub-modules) includes 2 ^n/2 -1 first logical sub-modules 321. .

Specifically, the j-th first logical sub-module 321 in the i-th group of first logical sub-modules is used to obtain the intermediate result based on the i-th symbol in the high-order code and the j-th symbol in the low-order code, and according to Should The intermediate result is combined with the i+1th code element in the high-order code to obtain the (i*2 ^n/2 +j)th code element in the thermometer code, where, in the case of 0<i≤2 ^n/2 -1 , 0≤j≤2 ^n/2 -1, when i=0, 0<j≤2 ^n/2 -1, j is an integer.

In other words, in the embodiment of the present application, when i=0, j is not equal to 0 and 0<j≤2 ^n/2 -1. The 0th group of first logical submodules does not include the 0th first logical submodule 321, and the 0th group of first logical submodules includes the 1st to 2n ^/2-1th first logical submodules 321. When 0＜i≤2 ^n/2 -1, 0≤j≤2 ^n/2 -1, that is, each of the first logical submodule in the first group to the first logical submodule in the 2nd ^n/2 -1 group The group of first logical sub-modules includes the 0th to 2 ^n/2 -1th first logical sub-modules 321 . In the i-th group of first logical sub-modules, each first logical sub-module 321 can be used to output one symbol of the thermometer code. As an example, as shown in FIG. 8 , the j-th first logic sub-module 321 may be used to output the j-th symbol en _i <j> in the i-th group of symbols en _i of the thermometer code. The j-th code element en _i <j> can be based on the i-th code element High _i , the i+1-th code element High i+1 and the low-bit code in the high code High<2 ^n/2 _-1 :0> The j-th symbol Low _j in Low<2 ^n/2 -1:0> is obtained. The j-th symbol en _i <j> in the i-th group of symbols en _i may be the (i*2 ^n/2 +j)-th symbol in the thermometer code.

Optionally, in some implementations, according to the above related technical solutions of high-bit code and low-bit code, for example, the 2 ^n/2- bit high-bit code High<2 ^n/2 -1:0> is selected from the 0th-bit code The element High ₀ to the u-th code element High _u is the target code element, and the u+1th code element High _u to the 2 ^n/2 -1 bit code in the high code High<2 ^n/2 -1:0> The element High ₂ ^n/2 _-1 is a non-target code element, u can be the value of the high-bit binary code, and the low-bit code Low<2 ^n/2 -1:0> is from the 0th code element Low ₀ to the v-th bit The code element Low _v is the target code element, and in the low code Low<2 ^n/2 -1:0>, the v+1th code element Low _v to the 2 ^n/2 -1th code element Low ₂ ^n/2 _{- 1} is a non-target code element, and v can be the value of the low-order binary code.

In this case, if the target symbol is 1 and the non-target symbol is 0, then the j-th first logical sub-module 321 in the i-th group of first logical sub-modules is used to set the high-order code High<2 ^n/ The i-th code element High _i in ² -1:0> and the j-th code element Low _j in low code Low<2 ^n/2 -1:0> perform AND logic to obtain an intermediate result, and the intermediate result is Perform OR logic with the i+1th bit symbol High i ₊₁ in the high bit code High<2 ^n/2 -1:0> to obtain the (i*2 ^n/2 +j)th bit symbol en in the thermometer code. _i <j>.

Specifically, the symbol en _i <j> can be calculated by the following formula (1):

en _i <j>=High _i+1 +Low _j *High _i (1).

The i-th group of code elements en _i where the code element en _i <j> is located can be calculated by the following formula (2):

en _i <2 ^n/2 -1:0>=High _i+1 +Low <2 ^n/2 -1:0>*High _i (2).

Among them, the "+" operation represents "OR logic", and the "*" operation represents "AND logic".

Or, if the target symbol is 0 and the non-target symbol is 1, then the j-th first logical sub-module 321 in the i-th group of first logical sub-modules is used to set the high-order code High<2 ^n/2 -1 The i-th symbol High _{i in :0>} and the j-th symbol Low _j in the low code Low<2 ^n/2 -1:0> perform OR logic to obtain an intermediate result, and combine the intermediate result with the high code The i+1th code element High _i+1 in High<2 ^n/2 -1:0> performs NAND logic to obtain the (i*2 ^n/2 +j)th code element en _i < in the thermometer code. j>.

Specifically, the symbol en _i <j> can be calculated by the following formula (3):

en _i <j>=(High _i+1 *(Low _j +High _i ))'(3).

The i-th group of code elements en _i where the code element en _i <j> is located can be calculated by the following formula (4):

en _i <2 ^n/2 -1:0>=(High _i+1 *(Low <2 ^n/2 -1:0>+High _i ))'(4).

Among them, the "+" operation represents "OR logic", the "*" operation represents "AND logic", and the "'" operation represents non-logic.

It can be understood that in some alternative implementations, when the target symbol is "1" and the non-target symbol is "0", the high-order code and the low-order code can be negated through non-logical negation, and the above formula ( 3) and formula (4) are converted to obtain the thermometer code, or, when the target code element is "0" and the non-target code element is "1", the high-order code and the low-order code can be negated through non-logic, and through the above Formula (1) and formula (2) are converted to obtain the thermometer code.

It can be seen from the above solution that in the combination logic module 320, the 2 ⁿ -1 first logic sub-modules 321 can not only have the same structure, but also the logic implementation of the first logic sub-module 321 is relatively simple, and can effectively deal with high-level codes. The thermometer code can be obtained through combined conversion with the code elements in the low-order code, and at the same time, the conversion efficiency can be improved, so that the thermometer code can be output quickly.

When n=4, that is, the number of bits of the high-order code and the low-order code is also 4, FIG. 9 shows a schematic structural block diagram of a combinational logic module 320 provided by the embodiment of the present application.

As shown in FIG. 9 , the combinational logic module 320 is used to receive the 4-bit high-order code High<3:0> and the 4-bit low-order code Low<3:0>, and output the 16-bit thermometer code en<15:0>.

The combinational logic module 320 includes 4×4, that is, 16 logic sub-modules, and the 16 logic sub-modules are composed of 15 first logic sub-modules 321 and 1 second logic sub-module 322.

Optionally, the first logic sub-module 321 and the second logic sub-module 322 may be logic sub-circuits, the circuit structures of the 15 first logic sub-circuits may be the same, and each first logic sub-circuit may include three inputs. Terminals High _a , High _b , Low _a and an output terminal en. A second logic sub-circuit can be a buffer gate (buffer), used to output the preset symbol "0" as the 0th bit symbol en 0 _<0> of the thermometer code en<15:0>.

Among the 15 first logical sub-modules 321, the bottom three first logical sub-modules 321 may be the 0th group of first logical sub-modules in the above embodiment, which are used to receive High ₀ and High ₁ , And receive Low ₁ to Low ₃ respectively to output the first code element en _{0 <1> to the third code element en 0 <3>} of the thermometer code en<15:0>. Similarly, the four first logical sub-modules 321 in the penultimate row may be the first group of first logical sub-modules in the above embodiment, which are used to receive High ₁ and High ₂ and receive Low ₀ to Low respectively. ₃ , to output the 4th code element en ₁ <0> to the 7th code element en ₁ <3> of the thermometer code en<15:0>. The four first logic sub-modules 321 in the second row can be the second group of first logic sub-modules in the above embodiment, which are used to receive High ₂ and High ₃ and receive Low ₀ to Low ₃ respectively to output The 8th code element en ₂ <0> of the thermometer code en<15:0> to the 11th code element en ₂ <3>. The four first logical sub-modules 321 in the first row may be the third group of first logical sub-modules in the above embodiment, which are used to receive High ₃ and High ₄ and receive Low ₀ to Low ₃ respectively to output The 12th code element en ₃ <0> of the thermometer code en<15:0> to the 15th code element en ₃ <3>, where High ₄ =0.

As an example, when the target symbol in the high-order code and the low-order code is "1", Figure 10 shows a schematic logic circuit diagram of the first logic sub-module 321. In this embodiment, the first logic sub-module 321 The sub-module 321 can also be called the first logic sub-circuit.

As shown in Figure 10, the first logic sub-circuit includes three circuit input terminals and one circuit output terminal, in which the first circuit input terminal High _a and the second circuit input terminal High _b are used to input high-bit binary codes 2 symbols in , the third circuit input terminal Low _a is used to input 1 symbol in the low binary code, and the circuit output terminal en is used to output 1 symbol in the thermometer code.

The first circuit input terminal High _a and the third circuit input terminal Low _a are connected to the AND gate and. The output terminal of the AND gate and and the second circuit input terminal High _b are connected to the input terminal of the OR gate or. The output of the OR gate or The terminal is connected to the circuit output terminal en.

As another example, when the target symbol in the high-order code and the low-order code is "0", Figure 11 shows a schematic logic circuit diagram of another first logic sub-module 321. In this embodiment, the first logic sub-module 321 The sub-module 321 can also be called the first logic sub-circuit.

As shown in Figure 11, in the first logic sub-circuit, the first circuit input terminal High _a and the third circuit input terminal Low _a are connected to the OR gate or, and the output terminal of the OR gate or and the second circuit input terminal High _b is connected to the input terminal of the NAND gate nand, and the output terminal of the NOT gate nand is connected to the circuit output terminal en.

Optionally, as shown in Figures 10 and 11, the first logic sub-circuit may also include: a buffer gate buffer. In the embodiment shown in Figure 10, the output terminal of the OR gate or can be connected to the circuit output terminal en through the buffer gate buffer. That is, the output terminal of the OR gate or is connected to the input terminal of the buffer gate buffer. The output terminal of the door punch buffer is connected to the circuit output terminal en. In the embodiment shown in FIG. 11, the output terminal of the NAND gate nand can be connected to the circuit output terminal en through the buffer gate buffer. That is, the output terminal of the NAND gate nand is connected to the input terminal of the buffer gate buffer, and the output terminal of the buffer gate buffer is connected to the circuit output terminal en.

In the above embodiments shown in Figures 10 and 11, if the first logic subcircuit is the jth first logic subcircuit in the ith group of first logic subcircuits among the ²ⁿ -1 first logic subcircuits , the first circuit input terminal High _a is used to input the i-th symbol in the high-order binary code, the second circuit input terminal High _b is used to input the i+1-th symbol in the high-order binary code, and the third circuit input The terminal Low _a is used to input the i-th code element in the low-order binary code, and the circuit output terminal en is used to output the (i*2 ^n/2 +j)-th code element in the thermometer code.

It should be noted that FIG. 10 and FIG. 11 are only schematic diagrams of the logic circuits of the two first logic sub-circuits provided by the embodiments of the present application. In addition to the technical solution shown in FIG. 10, the first The logic subcircuit can also be implemented through other circuit structures (such as other types of logic gates), and is intended to convert the high-order code and low-order code corresponding to the binary code into a thermometer code. In addition, in addition to directly using the AND gate, OR gate and NAND gate shown in the above-mentioned Figure 10 and Figure 11, the AND logic, OR logic and NAND logic of the code element can also be implemented by other types of logic gates. This application The embodiment does not limit the specific circuit structure of the first logic sub-circuit.

Optionally, the delay of the second logic sub-circuit shown in FIG. 9 may be consistent with the delay of the first logic sub-circuit. Specifically, the time delay of the second logic sub-circuit may be the time required for the signal to be transmitted from the input end of the second logic sub-module to the output end. Similarly, the time delay of the first logic sub-circuit may be the time required for the signal to be transmitted from the input end of the second logic sub-module to the output end. The time required to transmit from the input terminal of a logic submodule to the output terminal.

Optionally, the second logic sub-circuit may include a buffer gate buffer, so that the delay of the 0th-bit thermometer code output by the second logic sub-circuit is consistent with that of other bit thermometer codes output by the first logic sub-circuit, thereby ensuring The conversion performance of the device for converting binary code to thermometer code.

Optionally, in the case where both the first logic subcircuit and the second logic subcircuit include buffer gate buffers, and the buffering time of the buffer gate buffers is the same, the number of buffer gate buffers in the second logic subcircuit may be greater than the number of buffer gate buffers in the second logic subcircuit. The number of buffer gate buffers in a logical subcircuit, or, in the case where both the first logical subcircuit and the second logical subcircuit have a buffer gate, the delay time caused by the buffer gate of the second logical subcircuit is longer than that of the second logical subcircuit. The buffer gate of a logic subcircuit introduces a longer delay time.

Based on the above embodiments, Figure 12 shows another binary system provided by the embodiment of the present application. A schematic structural block diagram of a device 300 for converting thermometer codes.

As shown in Figure 12, in the device 300, the relevant technical solution of the decoding module 310 can be the same as the technical solution of the embodiment shown in Figure 4 above, and will not be described again here.

The combinational logic module 320 includes 2 ^n/2 groups of first logic sub-modules and one second logic sub-module 322 . In the 2 ^n/2 groups of first logical sub-modules, except for the 0th group of first logical sub-modules, each other group of first logical sub-modules includes 2 ^n/2 first logical sub-modules 321, and the 0th group of first logical sub-modules A logical sub-module includes 2 ^n/2 -1 first logical sub-modules 321 .

The second logic sub-module 322 is used to output the 0th thermometer code en ₀ <0>. The first logical submodule of group 0 is used to output the thermometer code of group 0 en ₀ <2 ^n/2 -1:1>, and the first logical submodule of group 1 is used to output the thermometer code of group 1 en ₁ <2 ^{n /2} -1:0>, and so on, the 2 ^n/2 -1 group of first logical submodules are used to output the 2 ^{n/2 -1 group of thermometer codes en 2 n/} ₂ ^-1 _< 2 ^n/2 - 1:0>. Arrange the multiple groups of thermometer codes from the 0th group to the 2n ^/2 -1 group in sequence, and combine them with the 0th thermometer code en ₀ <0> to obtain a 2 ⁿ -digit thermometer code en<2 ⁿ -1 :0>.

In the case of n=4, the decoding module 310 is used to input a 4-bit binary code. After conversion by the decoding module 310, a 4-bit high-order code and a 4-bit low-order code are obtained respectively. The high-order code and the low-order code are obtained respectively. After the code is converted by the combinational logic module 320, a 16-bit thermometer code is obtained.

In the case where the target symbol is “1” and the non-target symbol is “0” in the high-bit code and low-bit code converted by the decoding module 310, Table 2 below shows a device 300 according to the embodiment of the present application. The implemented truth table from 4-bit binary code (B<3:0>) to 16-bit thermometer code (en<15:0>), where Dec represents the decimal code.

Table 2

In the case where the target symbol is "0" and the non-target symbol is "1" in the high-bit code and low-bit code converted by the decoding module 310, in the truth table shown in the above Table 2, except for High<3 Except for the inversion of :0> and Low<3:0>, other values remain unchanged.

Through the technical solution of the above embodiment, a device 300 for converting a binary code into a thermometer code is provided. The circuit structure of the device 300 is simple and clear, and the power consumption is low. Moreover, the device 300 can achieve a consistent and short delay time for each symbol, thereby ensuring synchronous and correct reception of data transmission during high-speed data transmission. When the transmission speed of the binary code is fast, the device 300 can quickly and accurately convert the binary code into a thermometer code for use, and the conversion speed can track the speed of the input binary code. Furthermore, due to the simple circuit structure of the device 300 in the embodiment of the present application, it only includes two layers of logic circuits, the decoding module and the combinational logic module. When drawing the layout, complex layout wiring (such as avoiding cross wiring) can be avoided. At the same time, It also reduces parasitism and area.

In addition, the thermometer code converted by the device 300 can be used to input the control module, so that the control module implements the control function according to the thermometer code.

As an example, the control module may include a switch array, and each symbol in the thermometer code may be used to control a switch in the switch array. The weight of the unit controlled by each switch is consistent. For example, the symbol "1" can indicate that the switch is on, and the symbol "0" can indicate that the switch is off. The number of open switches in the switch array can be controlled only by controlling the number of code elements "1" in the thermometer code.

Through the thermometer code control module, it not only ensures the convenient and accurate implementation of the control method, but also achieves control and adjustment functions with excellent linearity and monotonicity.

This application also provides an electronic device. The electronic device may include the above control module and the device 300 for converting a binary code to a thermometer code as in any of the above embodiments. The device 300 is used to convert an n-bit binary code into a corresponding thermometer code. code, the control module is used to receive the thermometer code and implement control functions based on the thermometer code.

In some embodiments, the electronic device may include an LC oscillation circuit. The control module includes a switch array composed of 2 ⁿ switches. Each switch in the switch array is connected to a capacitor in the LC oscillation circuit. The switch array is used to receive a thermometer. The code controls the number of working capacitors in the LC oscillation circuit according to the thermometer code.

Specifically, the LC oscillation circuit may include 2 ⁿ capacitors, the 2 ⁿ capacitors have the same capacitance value, and the 2 ⁿ capacitors correspond to the 2 ⁿ capacitors in the switch array in a one-to-one manner. Each code element in the thermometer code is used to control a switch in the switch array. When the switch is closed, the capacitor connected to the switch is connected to the LC oscillation circuit, which acts as a working capacitor to generate oscillation. On the contrary, when the switch is open, the capacitor connected to the switch is connected to the LC oscillation circuit. When it is on, the capacitor connected to the switch is disconnected from the LC oscillation circuit and does not serve as the working capacitor of the LC oscillation circuit.

Through the technical solution of this embodiment, the cooperation between the control module and the device 300 for converting binary codes to thermometer codes can realize linear and monotonic control of the capacitance in the LC oscillation circuit, thereby ensuring the linearity of the gain of the LC oscillation circuit to improve Overall performance of LC oscillator circuit.

In addition to the above-mentioned LC oscillator circuit, the control module and the device 300 for converting binary codes to thermometer codes provided by the embodiments of the present application can also be applied to other control scenarios applicable to thermometer codes, which are not specifically limited in the embodiments of the present application.

It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art better understand the embodiments of the present application, but are not intended to limit the scope of the embodiments of the present application.

For example, each specific technical feature described in the above-mentioned specific embodiments can be combined in any suitable way without conflict. In order to avoid unnecessary repetition, this application will no longer describe various possible combinations. Specify otherwise.

For another example, any combination of various embodiments of the present application can be carried out. As long as they do not violate the idea of the present application, they should also be regarded as the contents disclosed in the present application.

It should be understood that the terminology used in the embodiments of the present application and the appended claims is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the present application. For example, as used in the embodiments and the appended claims, the singular forms "a," "above," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

Those of ordinary skill in the art will appreciate that the units of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. In order to clearly illustrate the interchangeability of hardware and software In the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians are available for each specific application Different methods may be used to implement the described functionality, but such implementations should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. In addition, the coupling or direct coupling or communication connection between each other shown or discussed may be indirect coupling or communication connection through some interfaces, devices or modules, or may be electrical, mechanical or other forms of connection.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of various equivalent methods within the technical scope disclosed in the present application. Modification or replacement, these modifications or replacements shall be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (19)

1. A device for converting binary codes into thermometer codes, which is characterized by including:

   Decoding module, used to convert the high n/2 bits of the n-bit binary code into a 2 ^n/2 bit high-bit code, and convert the n/2 bits of the n-bit binary code into the low-bit binary code. is a low-order code of 2 ^n/2 bits, wherein the number of target symbols in the high-order code is related to the value of the high-order binary code, and the number of target symbols in the low-order code is related to the value of the low-order binary code Relevant, the target symbol is 0 or 1, n is a positive even number;

   A combinational logic module includes a plurality of logic sub-modules, the plurality of logic sub-modules have the same delay, and the plurality of logic sub-modules are used to combine the symbols in the high-order code and the codes in the low-order code. Elements are combined to obtain the thermometer code corresponding to the n-bit binary code.
2. The device according to claim 1, wherein the correlation between the number of target symbols in the high-order code and the value of the high-order binary code includes: the 0th to uth bits in the high-order code are the target Code element, the other bits in the high-order code except the 0th to u-th bits are non-target code elements, where u is the value of the high-order binary code, 0≤u≤2 ^n/2 -1 ;

   The number of target code elements in the low-order code is related to the value of the low-order binary code: the 0th to v-th bits in the low-order code are the target code elements, and the low-order code except the 0th Bits other than the v-th bit are non-target code elements, where v is the value of the low-order binary code, 0≤v≤2 ^n/2 -1;

   When the target symbol is 1, the non-target symbol is 0, or when the target symbol is 0, the non-target symbol is 1.
3. The device according to claim 2, characterized in that the decoding module includes a plurality of identical decoding sub-modules, and the plurality of identical decoding sub-modules are used to compare the high-order binary code and the low-order binary code. The binary code is converted to obtain the high-order code and the low-order code.
4. The device according to claim 3, characterized in that the decoding module includes two identical decoding sub-modules, and the first decoding sub-module of the two identical decoding sub-modules is used to The high-order binary code is converted to obtain the high-order code, and the second decoding sub-module of the two identical decoding sub-modules is used to convert the low-order binary code to obtain the low-order code.
5. The device according to any one of claims 1 to 4, characterized in that the plurality of logical sub-modules include: 2 ⁿ -1 first logical sub-modules and a second logical sub-module, and the first logical sub-module The two logical sub-modules are used to output the 0th bit symbol in the thermometer code as a preset symbol. The 2 ⁿ -1 first logical sub-modules are the same and are used to output the code element in the high-order code. Yuan and the low bit code The code elements are combined to output the 1st code element to the ²ⁿ -1th code element in the thermometer code.
6. The device according to claim 5, characterized in that the 2 ⁿ -1 first logical sub-modules include 2 ^n/2 groups of first logical sub-modules, wherein each of the i-th group of first logical sub-modules A first logical sub-module is used to obtain a plurality of intermediate results according to the i-th symbol in the high-order code and the multi-bit symbols in the low-order code, and according to the multiple intermediate results and the high-order code The i+1th bit symbol in obtains the multi-bit symbol in the thermometer code, where 0≤i≤2 ^n/2 -1, i is an integer.
7. The device according to claim 6, wherein when 0<i≤2 ^n/2 -1, the i-th group of first logical sub-modules includes 2 ^n/2 first logical sub-modules, In the case of i=0, the i-th group of first logical sub-modules includes 2 ^n/2 -1 first logical sub-modules;

   Wherein, the j-th first logical sub-module in the i-th group of first logical sub-modules is used to obtain the j-th bit symbol in the high-order code and the j-th bit symbol in the low-order code. The j-th intermediate result among the plurality of intermediate results is obtained, and the (i*2 ^{n/ 2} +j) bit symbol, where, when 0<i≤2 ^n/2 -1, 0≤j≤2 ^n/2 -1, when i=0, 0<j≤2 ^{n /2} -1, j is an integer.
8. The device according to claim 7, characterized in that the target symbol is 1 and the non-target symbol is 0;

   The jth first logic sub-module is used to perform AND logic on the i-th symbol in the high-order code and the j-th symbol in the low-order code to obtain the jth intermediate result, and The jth intermediate result and the i+1th bit symbol in the high-order code are ORed to obtain the (i*2 ^n/2 +j)th bit symbol in the thermometer code.
9. The device according to claim 7, wherein the target symbol is 0 and the non-target symbol is 1;

   The jth first logic sub-module is used to perform OR logic on the i-th symbol in the high-order code and the j-th symbol in the low-order code to obtain the jth intermediate result, and The jth intermediate result and the i+1th bit symbol in the high-order code perform NAND logic to obtain the (i*2 ^n/2 +j)th bit symbol in the thermometer code.
10. The device according to any one of claims 1 to 9, characterized in that the decoding module and/or the combinational logic module is a logic circuit including logic gates.
11. The device according to claim 10, characterized in that the decoding module includes a decoder circuit, and the distance between any input terminal in the decoder circuit and any output terminal connected to the input terminal is The number of logic gates is the same.
12. The device according to claim 10 or 11, characterized in that the decoding module includes two decoder circuits with the same structure. When n=4, the decoder circuit includes two circuit inputs. terminals and four circuit output terminals, the two circuit input terminals are used to input a 2-bit high-order binary code or a low-order binary code, and the four circuit output terminals are used to output a 4-bit high-order binary code or low-order code;

    The first circuit output terminal among the four circuit output terminals is connected to the buffer gate and is used to output the zeroth preset symbol in the high-order code or the low-order code;

    The first circuit input terminal and the second circuit input terminal among the two circuit input terminals are connected to the input terminal of the NOR gate, the output terminal of the NOR gate is connected to the input terminal of the first NOT gate, and the third circuit input terminal is connected to the input terminal of the NOR gate. The output terminal of a NOT gate is connected to the second circuit output terminal among the four circuit output terminals, and is used to output the first symbol of the high-order code or the low-order code;

    The second circuit input terminal among the two circuit input terminals is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the input terminal of the third NOT gate, and the third NOT gate The output terminal is connected to the third circuit output terminal among the four circuit output terminals, and is used for outputting the second code element of the high-order code or the low-order code;

    The first circuit input terminal and the second circuit input terminal among the two circuit input terminals are connected to the input terminal of the NAND gate, the output terminal of the NAND gate is connected to the input terminal of the fourth NOT gate, and the third circuit input terminal is connected to the input terminal of the NAND gate. The output terminal of the four NOT gate is connected to the fourth circuit output terminal among the four circuit output terminals, and is used for outputting the third code element of the high-order code or the low-order code.
13. The device according to any one of claims 10 to 12, characterized in that the combinational logic module includes: a combinational logic circuit, the combinational logic circuit includes 2 ⁿ -1 first logic sub-circuits and a second Logic sub-circuit, the one second logic sub-circuit is used to output the 0th bit symbol in the thermometer code as a preset symbol, the circuits of the 2 ⁿ -1 first logic sub-circuits are the same, and Used to combine the symbol elements in the high-order code and the symbol elements in the low-order code to output the 1st to ²ⁿ -1th symbol elements in the thermometer code.
14. The device according to claim 13, wherein the delay of any one of the 2 ⁿ -1 first logic sub-circuits is the same as the delay of the one second logic sub-circuit.
15. The device according to claim 13 or 14, characterized in that the first logic sub-circuit includes three circuit input terminals and one circuit output terminal, and the first circuit input terminal and the third circuit input terminal among the three circuit input terminals The input terminal of the second circuit is used to input the 2 symbols in the high-order binary code, so The third circuit input terminal among the three circuit input terminals is used to input 1 symbol in the low-order binary code, and the circuit output terminal is used to output 1 symbol in the thermometer code;

    When the target symbol is 1, the first circuit input terminal and the third circuit input terminal are connected to the input terminal of the AND gate, and the output terminal of the AND gate and the second circuit input terminal Connected to the input end of the OR gate, the output end of the OR gate is connected to the output end of the circuit, or,

    When the target symbol is 0, the first circuit input terminal and the third circuit input terminal are connected to the input terminal of the OR gate, and the output terminal of the OR gate and the second circuit input terminal Connected to the input terminal of the NAND gate, the output terminal of the NAND gate is connected to the output terminal of the circuit.
16. The device according to any one of claims 1 to 15, characterized in that the decoding module and/or the combinational logic module are functional modules in a digital chip.
17. The device according to any one of claims 1 to 16, wherein the thermometer code is used to input into a control module, so that the control module implements a control function according to the thermometer code.
18. An electronic device, characterized by including: a control module, and

    The device according to any one of claims 1 to 17, the device is used to convert an n-bit binary code into a corresponding thermometer code, and the control module is used to receive the thermometer code and implement the thermometer code according to the thermometer code. control function.
19. The electronic device according to claim 18, characterized in that the electronic device includes an LC oscillation circuit, the LC oscillation circuit includes 2 ⁿ capacitors with the same capacitance value, and the control module includes a switch composed of 2 ⁿ switches. A switch array, each switch in the switch array is connected to a capacitor in the LC oscillation circuit, the switch array is used to receive the thermometer code and control the operation of the LC oscillation circuit according to the thermometer code. The number of capacitors in the state.