CN105099458B - Thermometer decoder - Google Patents
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Abstract
A kind of thermometer decoder, including the first sub- decoding unit, the second sub- decoding unit and 2N‑MA control module.The first sub- decoding unit is suitable for least significant bit data to the M-bit data of the binary data to be decoded being decoded as 2MBit binary data；It is 2 that the second sub- decoding unit, which is suitable for (M+1) position data of the binary data to be decoded to most significant bit data decoding,N‑MBit binary data；Each control module includes 2MA control unit.The thermometer decoder circuit structure of technical solution of the present invention offer is simple, circuit area is small, decoding speed is fast.
Description
Technical field
The present invention relates to digital circuit technique field, more particularly to a kind of thermometer decoder.
Background technology
In digital display circuit, it is often necessary to by a kind of code conversion be another code, to meet specific needs, complete
The circuit of this function is known as code conversion circuit.Code conversion circuit include encoder and decoder, wherein, decoder be by with
The binary code of specific meanings is converted into the code conversion circuit of corresponding output signal.Thermometer decoder as decoder one
Kind, it is widely used in memory repair design and digital analog converter.
Table one is a kind of truth table of existing 3 lines -8-channel temperature monitor decoder, and 3 lines -8-channel temperature monitor decoder is fitted
In the triad data A that will be inputted2A1A0It is decoded as 8 bit binary data Y7Y6Y5Y4Y3Y2Y1Y0Output.
Table one
| Input | Output |
| A2A1A0 | Y7Y6Y5Y4Y3Y2Y1Y0 |
| 000 | 00000001 |
| 001 | 00000011 |
| 010 | 00000111 |
| 011 | 00001111 |
| 100 | 00011111 |
| 101 | 00111111 |
| 110 | 01111111 |
| 111 | 11111111 |
As shown in Table 1, the 8 bit binary data Y7Y6Y5Y4 Y3Y2Y1Y0In, least significant bit (LSB, Least
Significant Bit) data Y0For the 1st data, most significant bit (MSB, Most Significant Bit) data Y7For
8th data, least significant bit data to (N+1) position data are binary data 1, and (N+2) position data are effective to highest
Position data are binary data 0, and N is the triad data A2A1A0Corresponding decimal data.Because described 8 two into
Data Y processed7Y6Y5Y4Y3Y2Y1Y0In, stepped variation is presented in binary data 1 or the scale variation of thermometer is similar, thus quilt
Referred to as thermometer decoder.
Certainly, according to the concrete application environment of thermometer decoder, truth table has a variety of versions.Table is second is that existing
The truth table of some another kind 3 lines -8-channel temperature monitor decoders：
Table two
| Input | Output |
| A2A1A0 | Y7Y6Y5Y4 Y3Y2Y1Y0 |
| 000 | 11111111 |
| 001 | 11111110 |
| 010 | 11111100 |
| 011 | 11111000 |
| 100 | 11110000 |
| 101 | 11100000 |
| 110 | 11000000 |
| 111 | 10000000 |
In the prior art, every output data can be obtained generally according to the truth table of 3 lines -8-channel temperature monitor decoder
Logical expression, then obtain by the logical expression of every output data the circuit knot of the 3 lines -8-channel temperature monitor decoder
Structure schematic diagram, every output data correspond to one group of logic gates.Fig. 1 is one corresponding 3 lines of table -8-channel temperature monitor decoder 10
A kind of electrical block diagram, 3 lines -8-channel temperature monitor decoder 10 include the first NAND gate circuit 100, the first NOT gate
Circuit 101, the second NAND gate circuit 102, the second not circuit 103, OR circuit 104, third NAND gate circuit 105, third
Not circuit 106, the 4th not circuit 107, the 5th not circuit 108, AND gate circuit 109, the first OR-NOT circuit 110,
Six not circuits 111, the second OR-NOT circuit 112, the 7th not circuit 113, third OR-NOT circuit 114, the 8th NOT gate electricity
Road 115, the 9th not circuit 116, PMOS transistor P10 and NMOS transistor N10, wherein, the PMOS transistor P10's
Source electrode connects power end Vdd, and the connection relation of each logic gates is with reference to 1 institute of figure in 3 lines -8-channel temperature monitor decoder 10
Show.The electrical block diagram or Fig. 1 of two corresponding 3 lines of table -8-channel temperature monitor decoding are similar, and details are not described herein.
The circuit of the thermometer decoder of any digit input can be obtained according to the logical expression of every output data
Structure diagram, however, when the input data digit of thermometer decoder increases, the circuit structure of the thermometer decoder
Become sufficiently complex, the area occupied is very big.
Invention content
What the present invention solved is the problem of existing thermometer decoder is complicated, circuit area is big.
To solve the above problems, the present invention provides a kind of thermometer decoder, translated including the first sub- decoding unit, the second son
Code unit and 2N-MA control module, N are the digit of binary data to be decoded, and 2≤M≤(N-2), M are positive integer；
The first sub- decoding unit is suitable for the least significant bit data of the binary data to be decoded to M digits
According to being decoded as 2MBit binary data, described 2MThe least significant bit data of bit binary data to J data are binary number
According to 1, described 2M(J+1) position data of bit binary data to most significant bit data are binary data 0, J for it is described most
Low order data are to the corresponding decimal data of M-bit data；
The second sub- decoding unit is suitable for (M+1) position data of the binary data to be decoded are effective to highest
Position data are decoded as 2N-MBit binary data, described 2N-MThe least significant bit data of bit binary data to K data are
Binary data 1, described 2N-M(K+1) position data of bit binary data to most significant bit data are binary data 0, K
For (M+1) position data to the corresponding decimal data of most significant bit data；
Each control module includes 2MA control unit；
Described control unit includes first input end, the first output terminal, reset terminal and set end, wherein, described first
Output terminal is suitable for the output and described the when the reset terminal receives binary data 0, the set end receives binary data 1
The opposite binary data of binary data that one input terminal receives, binary system is received in the reset terminal and the set end
Binary data output 0 during data 1 exports binary system when the reset terminal and the set end receive binary data 0
Data 1；
The first input end of the P control unit is suitable for receiving described 2 in each control moduleMThe of bit binary data
P data, 1≤P≤2M, P is positive integer；
The reset terminal of each control unit is suitable for receiving described 2 in the Q control moduleN-MQ of bit binary data
Data, 1≤Q≤2N-M, Q is positive integer；
The set end of each control unit receives binary data 1 in 1st control module, every in l-th control module
The set end of a control unit is suitable for receiving described 2N-M(L-1) position data of bit binary data, 2≤L≤2N-M, L is just
Integer.
Optionally, described control unit further includes the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube
And phase inverter, the phase inverter include the second input terminal, second output terminal, the first power end and second source end；
The grid of first PMOS tube connects the reset terminal, the source electrode connection described second of first PMOS tube
The source electrode of PMOS tube is simultaneously suitable for the first supply voltage of input, and the drain electrode of first PMOS tube connects first power end；
The grid of second PMOS tube connects the set end, and the drain electrode connection described first of second PMOS tube is defeated
The drain electrode of outlet, the second output terminal and second NMOS tube；
The grid of second NMOS tube connects the reset terminal, the source electrode connection described first of second NMOS tube
The source electrode of NMOS tube is simultaneously suitable for input second source voltage, and the second source voltage is less than first supply voltage；
The grid of first NMOS tube connects the set end, drain electrode connection second electricity of first NMOS tube
Source；
Second input terminal connects the first input end.
The prior art is compared, and technical scheme of the present invention has the following advantages：
Thermometer decoder provided by the invention, according to the truth table characteristic of thermometer decoder, using setting for stratification
Meter.The low M-bit data of binary data to be decoded and high (N-M) position data are translated respectively by two sub- decoding units
Code, 2 low M-bit data will obtained into row decodingMBit binary data is as 2N-MThe input of a control module, and by height (N-
M) the 2 of position data decoding acquisitionN-MBit binary data control described 2N-MA control module controls each control module output institute
State 2MBit binary data, 2MBit binary data 1 or 2MBit binary data 0.By the design of stratification, temperature is simplified
The circuit structure of degree meter decoder saves circuit area, it is easy to accomplish the decoding to multidigit binary data.
Further, thermometer decoder circuit structure provided by the invention is simple, and signaling rate is fast, improves decoding
Speed.
Description of the drawings
Fig. 1 is a kind of electrical block diagram of one corresponding 3 lines of table -8-channel temperature monitor decoder；
Fig. 2 is the electrical block diagram of the control module of embodiment of the present invention；
Fig. 3 is the circuit diagram of the control unit of the embodiment of the present invention；
Fig. 4 is the electrical block diagram of the first sub- decoding unit of the embodiment of the present invention.
Specific embodiment
Just as described in the background art, it is designed according to the logical expression of every output data of thermometer decoder more
The thermometer decoder of bit binary data, the circuit structure complexity of acquisition, the area occupied are big.The present invention provides a kind of temperature
Decoder is counted, using the design of stratification, the circuit structure of the thermometer decoder can be simplified, save circuit area.
Thermometer decoder provided by the invention includes the first sub- decoding unit, the second sub- decoding unit and 2N-MA control
Molding block, N are the digit of binary data to be decoded, and 2≤M≤(N-2), M are positive integer.The binary data to be decoded
Least significant bit data are the 1st data of the binary data to be decoded, and the highest of the binary data to be decoded has
Imitate the N data that position data are the binary data to be decoded.
The first sub- decoding unit is suitable for the least significant bit data of the binary data to be decoded to M digits
According to being decoded as 2MBit binary data, described 2MThe least significant bit data of bit binary data to J data are binary number
According to 1, described 2M(J+1) position data of bit binary data to most significant bit data are binary data 0, J for it is described most
Low order data are to the corresponding decimal data of M-bit data.
The second sub- decoding unit is suitable for (M+1) position data of the binary data to be decoded are effective to highest
Position data are decoded as 2N-MBit binary data, described 2N-MThe least significant bit data of bit binary data to K data are
Binary data 1, described 2N-M(K+1) position data of bit binary data to most significant bit data are binary data 0, K
For (M+1) position data to the corresponding decimal data of most significant bit data.
Each control module includes 2MA control unit, described control unit include first input end, the first output terminal, answer
Position end and set end, wherein, first output terminal is suitable for receiving binary data 0, the set end in the reset terminal
The binary data opposite with the binary data that the first input end receives is exported when receiving binary data 1, described
Binary data output 0 when reset terminal and the set end receive binary data 1, in the reset terminal and the set end
Binary data output 1 when receiving binary data 0.
The first input end of the P control unit is suitable for receiving described 2 in each control moduleMThe of bit binary data
P data, 1≤P≤2M, P is positive integer；The reset terminal of each control unit is suitable for receiving described 2 in the Q control moduleN-M
Q data of bit binary data, 1≤Q≤2N-M, Q is positive integer；The set of each control unit in 1st control module
It holds and receives binary data 1, the set end of each control unit is suitable for receiving described 2 in l-th control moduleN-MPosition binary system
(L-1) position data of data, 2≤L≤2N-M, L is positive integer.
Described 2N-MA control module includes 2NA control unit, described 2NA control unit output 2NBit binary data is
Decoding result for the binary data to be decoded.
Thermometer decoder provided by the invention uses the design of stratification, by the described first sub- decoding unit to described
The low M-bit data of binary data to be decoded is into row decoding, the second sub- decoding unit to the binary data to be decoded
Height (N-M) position data into row decoding, 2 low M-bit data will obtained into row decodingMBit binary data is as 2N-MA control
The input of molding block, and 2 obtained by high (N-M) position data decodingN-MBit binary data control described 2N-MA control module,
Control each control module output described 2MBit binary data, 2MBit binary data 1 or 2MBit binary data 0.Pass through
The design of stratification simplifies the circuit structure of thermometer decoder, saves circuit area, it is easy to accomplish to multidigit binary system
The decoding of data.Further, thermometer decoder circuit structure provided by the invention is simple, and signaling rate is fast, improves
Decoding speed.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
To be illustrated for the thermometer decoder to -64 line of 6 line, the thermometer decoder is suitable for 6 are waited to translate
Code binary data A5A4A3A2A1A0Into row decoding, i.e. N=6.Therefore, M can be equal to 2,3 or 4.In the present embodiment, with M
It is illustrated for equal to 3.The binary data A to be decoded5A4A3A2A1A0Least significant bit data (be also the 1st digit
According to) it is A0, most significant bit data are A5.Fig. 2 is the electrical block diagram of the thermometer decoder of the embodiment of the present invention, institute
It states thermometer decoder and includes the first sub- decoding unit 200, the second sub- decoding unit 201 and 8 control modules.
Specifically, the described first sub- decoding unit 200 is suitable for the binary data A to be decoded5A4A3A2A1A0Most
Low order data are to the 3rd data A2A1A0Into row decoding, by the least significant bit data to the 3rd data A2A1A0Decoding
For 8 bit binary data X7X6X5X4X3X2X1X0.The 8 bit binary data X7X6X5X4X3X2X1X0Least significant bit data
It is binary data 1 to J data, the 8 bit binary data X7X6X5X4X3X2X1X0(J+1) position data to highest
Number of significant digit evidence is binary data 0, wherein, J is the least significant bit data to the 3rd data A2A1A0Corresponding ten into
Data processed.
Table three
| Input | Output |
| A2A1A0 | X7X6X5X4X3X2X1X0 |
| 000 | 00000000 |
| 001 | 00000001 |
| 010 | 00000011 |
| 011 | 00000111 |
| 100 | 00001111 |
| 101 | 00011111 |
| 110 | 00111111 |
| 111 | 01111111 |
The truth table of the first sub- decoding unit 200 is as shown in Table 3.
The second sub- decoding unit 201 is suitable for the binary data A to be decoded5A4A3A2A1A0The 4th data
To most significant bit data A5A4A3It is 8 binary systems by the 4th data to most significant bit data decoding into row decoding
Data Z7Z6Z5Z4Z3Z2Z1Z0.The 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0Least significant bit data to K data
For binary data 1, the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0(K+1) position data to most significant bit data be
Binary data 0, wherein, K is the 4th data to most significant bit data A5A4A3Corresponding decimal data.Described
The truth table of two sub- decoding units 201 is as shown in Table 4：
Table four
| Input | Output |
| A5A4A3 | Z7Z6Z5Z4Z3Z2Z1Z0 |
| 000 | 00000000 |
| 001 | 00000001 |
| 010 | 00000011 |
| 011 | 00000111 |
| 100 | 00001111 |
| 101 | 00011111 |
| 110 | 00111111 |
| 111 | 01111111 |
With continued reference to Fig. 2,8 control modules are specially the 1st control module 21, the 2nd control module
22nd, the 8th control module 28.Each control module includes 8 control units：1st control module 21 includes control
Unit 211, control unit 212, control unit 218；2nd control module 22 includes control unit 221, control list
First 222, control unit 228；···；8th control module 28 includes control unit 281, control unit
282nd, control unit 288.
Described control unit includes first input end IN, the first output terminal OUT, reset terminal RST and set end SETX.Its
In, the first output terminal OUT be suitable for the reset terminal RST receive binary data 0, the set end SETX receive two into
The binary data opposite with the binary data that the first input end IN is received is exported during data 1 processed, i.e., described first
Binary data output 0 when input terminal IN receives binary data 1, when the first input end IN receives binary data 0
Binary data output 1；The first output terminal OUT is suitable for receiving two in the reset terminal RST and the set end SETX
Binary data output 0 during binary data 1；The first output terminal OUT is suitable in the reset terminal RST and the set end
Binary data output 1 when SETX receives binary data 0.
In 1st control module 21 the 1st in the first input end of the 1st control unit 211, the 2nd control module 22
The first input end of control unit 221, in the 8th control module 28 the 1st control unit 281 first input end
Suitable for receiving the 8 bit binary data X7X6X5X4X3X2X1X0The 1st data X0；2nd control in 1st control module 21
The first input end of 2nd control unit 222 in the first input end of unit 212 processed, the 2nd control module 22,
The first input end of the 2nd control unit 282 is suitable for receiving 8 bit binary data in 8 control modules 28
X7X6X5X4X3X2X1X0The 2nd data X1；···；First input of the 8th control unit 218 in 1st control module 21
End, the first input end of the 8th control unit 228 in the 2nd control module 22, the 8th in the 8th control module 28
The first input end of a control unit 288 is suitable for receiving the 8 bit binary data X7X6X5X4X3X2X1X0The 8th data X7。
The reset terminal of each control unit is suitable for receiving 8 bit binary data in 1st control module 21
Z7Z6Z5Z4Z3Z2Z1Z0The 1st data Z0, the set end of each control unit receives binary number in the 1st control module 21
According to 1；The reset terminal of each control unit is suitable for receiving 8 bit binary data in 2nd control module 22
Z7Z6Z5Z4Z3Z2Z1Z0The 2nd data Z1, the set end of each control unit is suitable for receiving described 8 in the 2nd control module 22
Bit binary data Z7Z6Z5Z4Z3Z2Z1Z0The 1st data Z0；···；Each control unit in 8th control module 28
Reset terminal is suitable for receiving the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0The 8th data Z7, it is every in the 8th control module 28
The set end of a control unit is suitable for receiving the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0The 7th data Z6。
As the binary data A to be decoded5A4A3A2A1A0When being 000000,8 bit binary data
X7X6X5X4X3X2X1X0With the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0It is 00000000.1st control module
The binary data phase that the first output terminal output of each control unit and the first input end of each control unit receive in 21
Anti- binary data, i.e. Y7···Y1Y0It is 11111111；2nd control module 21, it is described 8th control
First output terminal binary data output 1 of each control unit, i.e. Y in molding block 2863···Y57Y56、···、
Y15···Y9Y8It is 11111111.Therefore, as the binary data A to be decoded5A4A3A2A1A0When being 000000, decoding
The binary data of acquisition is 11,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111 111
11111。
As the binary data A to be decoded5A4A3A2A1A0When being 000001,8 bit binary data
X7X6X5X4X3X2X1X0It is 00000001, the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0It is 00000000.1st control
The binary system that the first output terminal output of each control unit and the first input end of each control unit receive in molding block 21
The opposite binary data of data, i.e. Y7···Y1Y0It is 11111110；2nd control module 21, it is described
First output terminal binary data output 1 of each control unit, i.e. Y in 8th control module 2863···
Y57Y56、···、Y15···Y9Y8It is 11111111.Therefore, as the binary data A to be decoded5A4A3A2A1A0For
When 000000, the binary data for decoding acquisition is 1111111111111111111111111111111111111111111111
111111111111111110。
As the binary data A to be decoded5A4A3A2A1A0When being 000010,8 bit binary data
X7X6X5X4X3X2X1X0It is 00000011, the 8 bit binary data Z7Z6Z5Z4Z3Z2Z1Z0It is 00000000.1st control
The binary system that the first output terminal output of each control unit and the first input end of each control unit receive in molding block 21
The opposite binary data of data, i.e. Y7···Y1Y0It is 11111100；2nd control module 21, it is described
First output terminal binary data output 1 of each control unit, i.e. Y in 8th control module 2863···
Y57Y56、···、Y15···Y9Y8It is 11111111.Therefore, as the binary data A to be decoded5A4A3A2A1A0For
When 000000, the binary data for decoding acquisition is
1111111111111111111111111111111111111111111111111111111111111100。
The operation principle of the thermometer decoder of the embodiment of the present invention will not enumerate, the thermometer decoder it is true
It is similar with table 2 to be worth table.It should be noted that simply converted by the thermometer decoder to the embodiment of the present invention,
It can obtain and truth table as table one kind.Those skilled in the art know how simply to be converted, and details are not described herein.
The embodiment of the present invention also provides a kind of particular circuit configurations of described control unit, as shown in Figure 3.The control is single
Member include first input end IN, the first output terminal OUT, reset terminal RST and set end SETX, further include the first PMOS tube P31,
Second PMOS tube P32, the first NMOS tube N31, the second NMOS tube N32 and phase inverter 30, the phase inverter include the second input
Hold a3, second output terminal a4, the first power end a1 and second source end a2.
Specifically, the grid of the first PMOS tube P31 connects the reset terminal RST, the source of the first PMOS tube P31
Pole connects the source electrode of the second PMOS tube P32 and suitable for the first supply voltage Vdd of input, the leakage of the first PMOS tube P31
Pole connects the first power end a1.The grid of the second PMOS tube P32 connects the set end SETX, the 2nd PMOS
The drain electrode of pipe P32 connects the leakage of the first output terminal OUT, the second output terminal a4 and the second NMOS tube NP32
Pole.The grid of the second NMOS tube N32 connects the reset terminal RST, the source electrode connection of the second NMOS tube N32 described the
The source electrode of one NMOS tube N31 is simultaneously suitable for input second source voltage, and the second source voltage is less than first supply voltage
Vdd.Described in the drain electrode connection of grid connection the set end SETX, the first NMOS tube N31 of the first NMOS tube N31
Second source end a2.The second input terminal a3 connections first input end IN.In general, the second source voltage is ground electricity
Pressure, i.e., the drain electrode of described second NMOS tube N32 and the source electrode of the first NMOS tube N31 are grounded.
Illustrate the operation principle of the control unit of the embodiment of the present invention below.
When the reset terminal RST receives binary data 0, the set end SETX receives binary data 1, described the
One PMOS tube P31 and the first NMOS tube N31 conductings, the second PMOS tube P32 and the second NMOS tube N32 cut-offs.
The first supply voltage Vdd is transmitted to the first power end a1, the second source electricity by the first PMOS tube P31
Pressure is transmitted to the second source end a2 by the first NMOS tube N31, and the phase inverter 30 works：When the described first input
When holding IN reception binary data 1, the first output terminal binary data output 0；When the first input end IN receives two
During binary data 0, the first output terminal binary data output 1.
When the reset terminal RST and the set end SETX receive binary data 1, the first PMOS tube P31
End with the second PMOS tube P32, the second NMOS tube N32 conductings.The second source voltage passes through described second
NMOS tube N32 is transmitted to the first output terminal OUT, the first output terminal OUT binary data outputs 0.
When the reset terminal RST and the set end SETX receive binary data 0, the first NMOS tube N31
End with the second NMOS tube N32, the second PMOS tube P32 conductings.First supply voltage passes through described second
PMOS tube P32 is transmitted to the first output terminal OUT, the first output terminal OUT binary data outputs 1.
Further, in embodiments of the present invention, the phase inverter 30 is CMOS inverter.The phase inverter 30 further includes
Three PMOS tube P33 and third NMOS tube N33.The grid of the third PMOS tube P33 connects the grid of the third NMOS tube N33
With the second input terminal a3, the source electrode of the third PMOS tube P33 connects the first power end a1, the third PMOS tube
The drain electrode of P33 connects the drain electrode of the third NMOS tube N33 and the second output terminal a4；The source of the third NMOS tube N33
Pole connects the second source end a2.
The embodiment of the present invention also provides a kind of particular circuit configurations of the first sub- decoding unit 200, as shown in Figure 4.
The first sub- decoding unit 200 includes the first not circuit 400, the second not circuit 401, third not circuit the 402, the 4th
Not circuit 407, the first NAND gate circuit 403, the second NAND gate circuit 404, third NAND gate circuit 406, OR circuit
405th, AND gate circuit 408, the first OR-NOT circuit 409, the second OR-NOT circuit 410, third OR-NOT circuit the 411, the 4th
PMOS tube P41 and the 4th NMOS tube N41.
Specifically, the input terminal of first not circuit 400 is suitable for inputting the binary data to be decoded
A5A4A3A2A1A0A data A0, the input terminal of second not circuit 401 is suitable for the input binary system to be decoded
Data A5A4A3A2A1A0Second data A1, the input terminal of the third not circuit 402 is suitable for input described to be decoded two
Binary data A5A4A3A2A1A0Third position data A2。
The first input end of first NAND gate circuit 403 connects the output terminal of first not circuit 400, described
Second input terminal of the first NAND gate circuit 403 connects the output terminal of second not circuit 401, the first NAND gate electricity
The third input terminal on road 403 connects the output terminal of the third not circuit 402, the output of first NAND gate circuit 403
End is suitable for exporting the 8 bit binary data X7X6X5X4X3X2X1X0A data X0。
The first input end of second NAND gate circuit 404 connects the output terminal of second not circuit 401, described
Second input terminal of the second NAND gate circuit 404 connects the output terminal of the third not circuit 402, the second NAND gate electricity
The output terminal on road 404 is suitable for exporting the 8 bit binary data X7X6X5X4X3X2X1X0Second data X1。
The first input end of the OR circuit 405 connects the output terminal of first not circuit 400, and described or door is electric
The output terminal of second input terminal connection, second not circuit 401 on road 405, the first of the third NAND gate circuit 406
Input terminal connects the output terminal of the OR circuit 405, the second input terminal connection of the third NAND gate circuit 406 described the
The output terminal of three not circuits 402, the output terminal of the third NAND gate circuit 406 are suitable for exporting 8 bit binary data
X7X6X5X4X3X2X1X0Third position data X2。
The input terminal of 4th not circuit 407 connects the output terminal of the third not circuit 402, and the described 4th is non-
The output terminal of gate circuit 407 is suitable for exporting the 8 bit binary data X7X6X5X4X3X2X1X0Four figures according to X3。
The first input end of the AND gate circuit 408 connects the output terminal of first not circuit 400, described electric with door
The output terminal of second input terminal connection, second not circuit 401 on road 408, the first of first OR-NOT circuit 409
Input terminal connects the output terminal of the AND gate circuit 408, the second input terminal connection of first OR-NOT circuit 409 described the
The output terminal of three not circuits 402, the output terminal of first OR-NOT circuit 409 are suitable for exporting 8 bit binary data
X7X6X5X4X3X2X1X0Five-digit number according to X4。
The first input end of second OR-NOT circuit 410 connects the output terminal of second not circuit 401, described
Second input terminal of the second OR-NOT circuit 410 connects the output terminal of the third not circuit 402, the second nor gate electricity
The output terminal on road 410 is suitable for exporting the 8 bit binary data X7X6X5X4X3X2X1X0The 6th data X5。
The first input end of the third OR-NOT circuit 411 connects the output terminal of first not circuit 400, described
Second input terminal of third OR-NOT circuit 411 connects the output terminal of second not circuit 401, the third nor gate electricity
The third input terminal on road 411 connects the output terminal of the third not circuit 402, the output of the third OR-NOT circuit 411
End is suitable for exporting the 8 bit binary data X7X6X5X4X3X2X1X0The 7th data X6。
The source electrode of the 4th PMOS tube P41 is suitable for the first supply voltage Vdd of input, the grid of the 4th PMOS tube P41
Pole connects the drain electrode of the 4th PMOS tube P41 and the grid of the 4th NMOS tube N41, the leakage of the 4th NMOS tube N41
It is extremely suitable to export the 8 bit binary data X7X6X5X4X3X2X1X0Eight bit data X7, the source of the 4th NMOS tube N41
It is extremely suitable to input second source voltage, the second source voltage is less than the first supply voltage Vdd.In general, described second
Supply voltage is ground voltage, i.e., the source electrode ground connection of described 4th NMOS tube N41.
The particular circuit configurations of the second sub- decoding unit 201 and the physical circuit of the described first sub- decoding unit 200
Structure is similar, and details are not described herein.It should be noted that described control unit and the first sub- decoding unit 200 is specific
Circuit structure is not limited to the circuit structure cited by the embodiment of the present invention.In other embodiments, described control unit and institute
The first sub- decoding unit 200 or the circuit of other forms are stated, as long as work(in the technical solution of the present invention can be realized
Energy, this is not limited by the present invention.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
In the spirit and scope of invention, it can make various changes or modification, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (6)
1. a kind of thermometer decoder, which is characterized in that including the first sub- decoding unit, the second sub- decoding unit and 2N-MIt is a
Control module, N are the digit of binary data to be decoded, and 2≤M≤(N-2), M are positive integer；
The first sub- decoding unit is suitable for translating least significant bit data to the M-bit data of the binary data to be decoded
Code is 2MBit binary data, described 2MThe least significant bit data of bit binary data to J data are binary data 1,
Described 2M(J+1) position data of bit binary data to most significant bit data are binary data 0, and J minimum has to be described
Position data are imitated to the corresponding decimal data of M-bit data；
The second sub- decoding unit is suitable for (M+1) position data of the binary data to be decoded to most significant bit number
According to being decoded as 2N-MBit binary data, described 2N-MThe least significant bit data of bit binary data to K data for two into
Data 1 processed, described 2N-M(K+1) position data of bit binary data to most significant bit data are binary data 0, and K is institute
(M+1) position data are stated to the corresponding decimal data of most significant bit data；
Each control module includes 2MA control unit；
Described control unit includes first input end, the first output terminal, reset terminal and set end, wherein, first output
End is suitable for exporting when the reset terminal receives binary data 0, the set end receives binary data 1 and described first is defeated
Enter the opposite binary data of the binary data of end reception, binary data is received in the reset terminal and the set end
Binary data output 0 when 1, the binary data output when the reset terminal and the set end receive binary data 0
1；
The first input end of the P control unit is suitable for receiving described 2 in each control moduleMThe P digits of bit binary data
According to 1≤P≤2M, P is positive integer；
The reset terminal of each control unit is suitable for receiving described 2 in the Q control moduleN-MThe Q digits of bit binary data
According to 1≤Q≤2N-M, Q is positive integer；
The set end of each control unit receives binary data 1 in 1st control module, is each controlled in l-th control module
The set end of unit processed is suitable for receiving described 2N-M(L-1) position data of bit binary data, 2≤L≤2N-M, L is positive integer.
2. thermometer decoder as described in claim 1, which is characterized in that described control unit further include the first PMOS tube,
Second PMOS tube, the first NMOS tube, the second NMOS tube and phase inverter, the phase inverter include the second input terminal, the second output
End, the first power end and second source end；
The grid of first PMOS tube connects the reset terminal, and the source electrode of first PMOS tube connects second PMOS tube
Source electrode and suitable for the first supply voltage of input, the drain electrode of first PMOS tube connects first power end；
The grid of second PMOS tube connects the set end, drain electrode connection first output of second PMOS tube
The drain electrode at end, the second output terminal and second NMOS tube；
The grid of second NMOS tube connects the reset terminal, and the source electrode of second NMOS tube connects first NMOS tube
Source electrode and suitable for input second source voltage, the second source voltage be less than first supply voltage；
The grid of first NMOS tube connects the set end, and the drain electrode of first NMOS tube connects the second source
End；
Second input terminal connects the first input end.
3. thermometer decoder as claimed in claim 2, which is characterized in that the phase inverter further includes third PMOS tube and
Three NMOS tubes；
The grid of the third PMOS tube connects the grid of the third NMOS tube and second input terminal, the 3rd PMOS
The source electrode of pipe connects first power end, and the drain electrode of the third PMOS tube connects the drain electrode of the third NMOS tube and described
Second output terminal；
The source electrode of the third NMOS tube connects the second source end.
4. thermometer decoder as claimed in claim 2, which is characterized in that the second source voltage is ground voltage.
5. such as Claims 1-4 any one of them thermometer decoder, which is characterized in that N 6, M 3, first son
Decoding unit includes the first not circuit, the second not circuit, third not circuit, the 4th not circuit, the first NAND gate electricity
Road, the second NAND gate circuit, third NAND gate circuit, OR circuit, AND gate circuit, the first OR-NOT circuit, the second nor gate
Circuit, third OR-NOT circuit, the 4th PMOS tube and the 4th NMOS tube；
The input terminal of first not circuit is suitable for inputting a data of the binary data to be decoded, and described second
The input terminal of not circuit is suitable for inputting the second data of the binary data to be decoded, the third not circuit it is defeated
Enter the third position data that end is suitable for inputting the binary data to be decoded；
The first input end of first NAND gate circuit connects the output terminal of first not circuit, first NAND gate
Second input terminal of circuit connects the output terminal of second not circuit, and the third input terminal of first NAND gate circuit connects
The output terminal of the third not circuit is connect, the output terminal of first NAND gate circuit is suitable for output described 2MBit
According to a data；
The first input end of second NAND gate circuit connects the output terminal of second not circuit, second NAND gate
Second input terminal of circuit connects the output terminal of the third not circuit, and the output terminal of second NAND gate circuit is suitable for defeated
Go out described 2MThe second data of bit binary data；
The first input end of the OR circuit connects the output terminal of first not circuit, and the second of the OR circuit is defeated
Enter the output terminal that end connects second not circuit, the first input end connection of the third NAND gate circuit is described or door is electric
The output terminal on road, the second input terminal of the third NAND gate circuit connect the output terminal of the third not circuit, and described the
The output terminal of three NAND gate circuits is suitable for output described 2MThe third position data of bit binary data；
The input terminal of 4th not circuit connects the output terminal of the third not circuit, the 4th not circuit it is defeated
Outlet is suitable for output described 2MThe four figures evidence of bit binary data；
The first input end of the AND gate circuit connects the output terminal of first not circuit, and the second of the AND gate circuit is defeated
Enter the output terminal that end connects second not circuit, the first input end of first OR-NOT circuit connects described and door electricity
The output terminal on road, the second input terminal of first OR-NOT circuit connect the output terminal of the third not circuit, and described the
The output terminal of one OR-NOT circuit is suitable for output described 2MThe five-digit number evidence of bit binary data；
The first input end of second OR-NOT circuit connects the output terminal of second not circuit, second nor gate
Second input terminal of circuit connects the output terminal of the third not circuit, and the output terminal of second OR-NOT circuit is suitable for defeated
Go out described 2M6th data of bit binary data；
The first input end of the third OR-NOT circuit connects the output terminal of first not circuit, the third nor gate
Second input terminal of circuit connects the output terminal of second not circuit, and the third input terminal of the third OR-NOT circuit connects
The output terminal of the third not circuit is connect, the output terminal of the third OR-NOT circuit is suitable for output described 2MBit
According to the 7th data；
The source electrode of 4th PMOS tube is suitable for the first supply voltage of input, the grid connection the described 4th of the 4th PMOS tube
The drain electrode of PMOS tube and the grid of the 4th NMOS tube, the drain electrode of the 4th NMOS tube are suitable for output described 2MPosition binary system
The eight bit data of data, the source electrode of the 4th NMOS tube are suitable for input second source voltage, and the second source voltage is low
In first supply voltage.
6. thermometer decoder as claimed in claim 5, which is characterized in that the second source voltage is ground voltage.
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| CN110703582B (en) * | 2019-09-25 | 2021-02-26 | 天津大学 | Thermometer code to binary code circuit for time-to-digital converter |
| CN113114264B (en) * | 2020-01-10 | 2023-08-08 | 炬芯科技股份有限公司 | Thermometer decoding method and circuit |
| CN115102553B (en) * | 2022-08-26 | 2022-12-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
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