CN101908886A - Ten-bit superspeed CMOS digital to analog converter based on MOS current mode logic - Google Patents
Ten-bit superspeed CMOS digital to analog converter based on MOS current mode logic Download PDFInfo
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- CN101908886A CN101908886A CN2009102544165A CN200910254416A CN101908886A CN 101908886 A CN101908886 A CN 101908886A CN 2009102544165 A CN2009102544165 A CN 2009102544165A CN 200910254416 A CN200910254416 A CN 200910254416A CN 101908886 A CN101908886 A CN 101908886A
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Abstract
The invention discloses a CMOS digital to analog converter, mainly aiming to solve the problems of large switch noise, poor circuit precision and low speed of the traditional CMOS digital to analog converter under the condition of low power consumption. The CMOS digital to analog converter is composed of an input synchronization latch, a thermometer decoder, a delay equalizer, a latch, a current switch driver, an NMOS current source array and a band-gap reference voltage source, wherein the thermometer decoder adopts a parallel thermometer decoder structure and consists of an AND gate/NAND gate logical unit and an OR gate/NOR gate logical unit of an MOS current mode logical structure; the delay equalizer comprises a reverse directional device of the MOS current mode logic structure; both the latch and the current switch driver adopt the MOS current mode logic structure; and the input end of the NMOS current source array is connected with the complementary output ends of the latch and the current switch driver so as to generate complementary output current. The CMOS digital to analog converter in the invention has the advantages of small output pendulum deflection and switch noise, high circuit precision and rapid working speed, and can be applicable to communication, signal processing and video processing systems.
Description
Technical field
The invention belongs to microelectronic, particularly a kind of CMOS digital to analog converter is used for communication, signal processing and processing system for video.
Background technology
Modern Communication System, the continuous development of information processing system and processing system for video impels the Digital Analog Hybrid Circuits designer to be devoted to the research of high speed data converter IP kernel.Wherein, the Embedded Application of digital to analog converter in fields such as HDTV, mobile communication makes high-speed low-power-consumption be designed to the important directions of modern D/A side exhibition.
Traditional CMOS digital to analog converter is by input synchrolock storage, thermometer decoded device and delay equalizer, latch and current switch driver, NMOS current source array, and bandgap voltage reference composition, these unit are made of the traditional cmos logical construction.For traditional CMOS logical construction, as reverser, with door, or door, latch, current switch drivers etc. all are the working methods that is in full swing.The full swing working method of CMOS logic has been aggravated switching noise, and these noises can be coupled to the simulation part by substrate and power line, thereby has influence on the precision of circuit.Under the traditional cmos logical construction, be to finish the most direct effective method of low power dissipation design though reduce supply voltage, the reduction of supply voltage is a cost to sacrifice speed ability.
Summary of the invention
The objective of the invention is to overcome above-described shortcoming, a kind of 10 CMOS digital to analog converters based on the MOS current mode logic are provided, with the restriction output voltage swing, the switching noise when reducing circuit working improves circuit precision and operating rate.
For achieving the above object, digital to analog converter of the present invention comprises input synchrolock storage, 6～63 thermometer decoders, delay equalizer, latch, current switch driver, NMOS current source array and bandgap voltage references, the input data are connected to 6～63 thermometer decoders and delay equalizer through input synchrolock storage, be connected to latch, current switch driver and NMOS current source array more successively, wherein:
6～63 thermometer decoders adopt the thermometer decoded device of parallel construction, comprise N MOS current mode logic structure with door/NAND gate logical block with or door/NOR gate logical block, 1＜N＜100;
Delay equalizer is made up of the reverse direction controller of MOS current mode logic structure;
Latch and current switch driver all adopt MOS current mode logic structure;
The NMOS current source array, input is connected with the complementary output end of latch and current switch driver, produces complementary output current.
Described and door/NAND gate logical block, adopts two PMOS manage (P1, P2), five NMOS manage (N1, N2, N3, N4 N5) connects to form.
Described or door/NOR gate logical block, adopt two PMOS pipes (P3, P4), five NMOS pipes (N6, N7, N8, N9 N10) connects to form.
Described inverter, (P5, P6), (N11, N12 N13) connect to form three NMOS pipes to adopt two PMOS pipes.
Described latch, adopt two PMOS pipe (P7, P8), seven NMOS pipes (N14, N15, N16, N17, N18, N19 N20) connects to form.
Described current switch driver, adopt four PMOS pipe (P9, P10, P11, P12), (N21, N22 N23) connect to form three NMOS pipes.
Described NMOS current source array, (N26 N27) connects to form for N24, N25 to adopt the four NMOS pipe.
The present invention has following advantage:
1) the present invention makes that the amplitude of oscillation of incoming level and output level is smaller owing to use the MOS current mode logic, and can effectively reduce the logical effect of bursting, and improves the reaction speed of circuit;
2) the present invention can make output signal keep having avoided the misoperation of switch synchronously owing to adopt MOS current mode logic delay equalizer and latch, has improved the speed of change-over circuit;
3) the present invention is owing to by regulating current switch drive signal crosspoint, prevent that current switch from turn-offing simultaneously, and burr and the trap eliminating output signal effectively and produced improve the linearity of output;
4) the present invention adopts the thermometer decoded device of parallel construction, has simplified the thermometer decoded circuit, helps the layout design of thermometer decoded device.
Description of drawings
Fig. 1 is the structured flowchart among the present invention;
Fig. 2 among the present invention with door/NAND gate logical block
Fig. 3 is among the present invention or the circuit diagram of door/NOR gate logical block;
Fig. 4 is the circuit diagram of the reverser among the present invention;
Fig. 5 is the circuit diagram of the latch cicuit among the present invention;
Fig. 6 is the circuit diagram of the current switch driver among the present invention;
Fig. 7 is the circuit diagram in the cascode current source of nmos switch among the present invention;
Fig. 8 is current switch drive signal waveform figure among the present invention.
Embodiment
One. design principle of the present invention
The MOS current mode logic that the present invention uses has less long-pending, the adjustable output voltage swing of power consumption time-delay, and can keep higher speed under low supply voltage work.
The output voltage swing of MCML circuit can be expressed as:
ΔV＝I×R
P (1)
Wherein, I is the bias current value that flows through this branch road, and R
PResistance value for adjustable resistance.By formula (1) as can be known, regulate output voltage swing by the mode of regulating current value or resistance value.In order to guarantee the operate as normal of circuit, can be to resistance value R
PRegulate, make current value I constant.
In order to obtain less Δ V, MOS current mode logic circuit usually utilizes the metal-oxide-semiconductor that is operated in dark linear zone as load, to obtain the adjustable less resistive of resistance.The PMOS pipe trench road resistance that is operated in dark linear zone can be expressed as:
μ
Eff, pBe the transistorized effective channel mobility of PMOS, C
OxBe the electric capacity of unit are, V
ODBe overdrive voltage, W is that PMOS is transistorized wide, and L is the transistorized length of PMOS.Increase the breadth length ratio W/L of metal-oxide-semiconductor, can reduce channel resistance, but can increase area and introduce parasitic capacitance, circuit performance is descended.In order to obtain the influence that less values of channel resistance reduces parasitic factor again, adopt maximum overdrive voltage V among the present invention
OD, therefore with the load PMOS transistor gate earth level of MOS current mode logic circuit under less breadth length ratio W/L condition, to obtain higher circuit performance.
The thermometer decoded device of the digital to analog converter of structure of current rudder normally ranks decoder architecture is realized, its shortcoming is must open the current line unit before switching to the next line unit, thereby reduced the flexibility of decoder, and influenced the arbitrary placement of current switch.Be to realize the high speed design of digital to analog converter under the low supply voltage, and avoid the shortcoming of ranks decoder, 6～63 parallel thermometer decoded devices that the present invention is based on MOS current mode logic structural design.
For the thermometer decoded device of N position, do not need to list fully all 2
NThe boolean logical expression of-1 output if consider to translate the output equation of thermometer decoded device even bit earlier, then can be simplified the design of logical circuit.6 the parallel thermometer decoded even bit of MSB output equations can be expressed as
Wherein B1～B6 corresponds respectively to binary system input code D4～D9, and has
The output of odd bits can be obtained by the output of even bit.According to the characteristic of thermometer decoded as can be known, if high-order even bit F
2n+2Be 1, then as odd bits F
2n+1Be 1; If F
2n+2Be 0, then see F
2nAnd B
1Whether be 1 simultaneously.If translated lowest order binary system input code B
1Be 1, then explanation is interpreted as odd number.If at this moment hang down one even bit F
2nBe 1, then current odd bits F
2n+1Must be 1.Therefore the output of odd bits can be expressed as
F
2n+1＝F
2n·B
1+F
2n+2，n＝0，1，2，…，30 (5)
By equation (3), (4), (5) as can be known, utilize with door and or gate logic just can realize 6 MSB decoding circuits, thereby simplified the design of thermometer decoded circuit, and help the layout design of thermometer decoded device.The synchronous signal transmission path of all inputs of thermometer decoded device helps the maximization of digital to analog converter sampling rate.
Two, realization example of the present invention
With reference to Fig. 1, digital to analog converter of the present invention comprises input synchrolock storage, 6～63 thermometer decoders, delay equalizer, latch, current switch driver, NMOS current source array and bandgap voltage references.Wherein, import the synchrolock storage, be used to receive the digital signal of input, latch and make described digital signal synchronous described digital signal; 6～63 thermometer decoders, adopt the thermometer decoded device of parallel construction, by MOS current mode logic structure with door/NAND gate logical block and or door/NOR gate logical block constitute, be used to receive high 6 position digital signals of handling through described input synchrolock storage, and produce 63 complementary thermometer-codes; Delay equalizer is made of MOS current mode logic reverser, is used to receive the ends 4 position digital signal of handling through described input synchrolock storage, produces 4 complementary binary codes, makes output signal and 6～63 signal Synchronization that the thermometer decoder produces; Latch and current switch driver, all adopt MOS current mode logic structure, be used to accept through 63 thermometer-codes of described 6～63 thermometer decoders generation and 4 binary codes of described delay equalizer generation, make the signal Synchronization of input, produce the complementary current drive signal of amplitude limit, reduced to burst and led to effect,, eliminated burr and trap that output signal produced by having adjusted the crosspoint of current switch drive signal; The NMOS current source array is used to accept the signal handled through described latch and current switch driver, produces the output current signal of low distortion; Bandgap voltage reference is used for to described 6～63 thermometer decoded devices, delay equalizer, and latch and current switch driver, the NMOS current source array provides bias voltage.
Digital signal is passed to 6～63 thermometer decoders with high 6 truth of a matter word signals after input synchrolock storage is synchronous, produce 63 complementary thermometer-codes, and 4 the digital signal in the end is passed to delay equalizer, produces 4 complementary binary codes; The signal that 6～63 thermometer decoders and delay equalizer produce is passed to latch and current switch driver successively, produces the complementary current switching drive signal of the end of swing width of cloth; Signal through described latch and current switch driver processing is passed to the NMOS current source array, produces the output current signal of low distortion; Bandgap voltage reference is given described 6 ~ 63 thermometer decoded devices, delay equalizer, and latch, current switch driver and NMOS current source array provide bias voltage.
With reference to Fig. 2, that uses during this is bright comprises with door/NAND gate logical unit structure: two PMOS pipe P1, P2, five NMOS pipe N1, N2, N3, N4, N5; Its annexation is:
The one PMOS manages P1, and the 2nd PMOS manages P2, source electrode connect power supply, grounded-grid makes PMOS pipe P1 and the 2nd PMOS pipe P2, is operated in dark linear zone, as active load; The drain electrode of the one PMOS pipe P1 links to each other with the drain electrode of NMOS pipe N1, as the output of NAND Logic; The drain electrode of the 2nd PMOS pipe P2 links to each other with the drain electrode of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3, as with the output of logic; The source electrode of the one NMOS pipe N1 and the 2nd NMOS pipe N2 links to each other with the drain electrode of the 4th NMOS pipe N4, and the source electrode of the 3rd NMOS pipe N3 and the 4th NMOS pipe N4 links to each other with the drain electrode of the 5th NMOS pipe N5, and the source electrode of the 5th NMOS pipe N5 links to each other with ground; The one NMOS manages N1, and the grid of the 2nd NMOS pipe N2 links to each other with inverted signal with the positive signal of one of them input signal respectively; The 3rd NMOS manages N3, and the grid of the 4th NMOS pipe N4 links to each other with inverted signal with the positive signal of another input signal respectively; The grid of the 5th NMOS pipe N5 links to each other with the bias voltage that bandgap voltage reference provides, and forms bias current sources; PMOS manages P1, and the substrate of P2 is connected with power supply, provides biasing to the substrate of PMOS pipe, and NMOS manages N1, N2, and N3, N4, the substrate of N5 is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 3, use during this is bright or door/NOR gate logical unit structure comprise: two PMOS pipe P3, P4, five NMOS manage N6, N7, N8, N9, N10; Its annexation is:
The source electrode of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 connects power supply, and grounded-grid makes the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 be operated in dark linear zone, as active load; The drain electrode of the 3rd PMOS pipe P3 links to each other with the drain electrode of the 8th NMOS pipe N8 with the 6th NMOS pipe N6, as the output of NOR-logic; The drain electrode of the 4th PMOS pipe P4 links to each other with the drain electrode of the 7th NMOS pipe N7, as or the output of logic; The source electrode of the 6th NMOS pipe N6 and the 7th NMOS pipe N7 links to each other with the drain electrode of the 9th NMOS pipe N9, and the source electrode of the 8th NMOS pipe N8 and the 9th NMOS pipe N9 links to each other with the drain electrode of the tenth NMOS pipe N10, and the source electrode of the tenth NMOS pipe N10 links to each other with ground; The 6th NMOS manages N6, and the grid of the 7th NMOS pipe N7 links to each other with inverted signal with the positive signal of an input signal respectively; The 8th NMOS manages N8, and the grid of the 9th NMOS pipe N9 links to each other with inverted signal with the positive signal of another input signal respectively; The grid of the tenth NMOS pipe N10 links to each other with the bias voltage that bandgap voltage reference provides, and forms bias current sources; PMOS manages P3, and the substrate of P4 is connected with power supply, provides biasing to the substrate of PMOS pipe, described NMOS pipe N6, and N7, N8, N9, the substrate of N10 is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 4, the reverser structure of using during this is bright comprises: two PMOS pipe P5, P6, three NMOS pipe N11, N12, N13; Its annexation is:
The source electrode of the 5th PMOS pipe P5 and the 6th PMOS pipe P6 connects power supply, and grounded-grid makes the 5th PMOS pipe P5 and the 6th PMOS pipe P6 be operated in dark linear zone, as active load; The drain electrode of the 5th PMOS pipe P5 links to each other with the drain electrode of the 11 NMOS pipe N11, as alogical output; The drain electrode of the 6th PMOS pipe P6 links to each other with the drain electrode of the 12 NMOS pipe N12, as the output identical with input; The source electrode of the 11 NMOS pipe N11 and the 12 NMOS pipe N12 links to each other with the drain electrode of the 13 NMOS pipe N13; The 11 NMOS manages N11, and the grid of the 12 NMOS pipe N12 links to each other with inverted signal with the positive signal of input signal respectively; The grid of the 13 NMOS pipe N13 link to each other with the bias voltage that bandgap voltage reference provides, and form bias current sources; PMOS manages P5, and the substrate of P6 is connected with power supply, provides biasing to the substrate of PMOS pipe, described NMOS pipe N11, and N12, N13, N9, the substrate of N10 is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 5, the latch structure that uses during this is bright comprises: two PMOS pipe P7, P8, three NMOS pipe N14, N15, N16, N17, N18, N19, N20; Its annexation is:
The source electrode of the 7th PMOS pipe P7 and the 8th PMOS pipe P8 connects power supply, and grounded-grid makes the 7th PMOS pipe P7 and the 8th PMOS pipe P8 be operated in dark linear zone, as active load; The drain electrode of the 7th PMOS pipe P7 and the 14 NMOS pipe N14, the drain electrode of the 15 NMOS pipe N15 links to each other with the grid of the 16 NMOS pipe N16, as the reverse output of latch; The drain electrode of the 8th PMOS pipe P8 and the 16 NMOS pipe N16, the drain electrode of the 17 NMOS pipe N17 links to each other with the grid of the 15 NMOS pipe N15, as the forward output of latch; The source electrode of the 14 NMOS pipe N14 and the 17 NMOS pipe N17 links to each other with the drain electrode of the 18 NMOS pipe N18, the source electrode of the 15 NMOS pipe N15 and the 16 NMOS pipe N16 links to each other with the drain electrode of the 19 NMOS pipe N19, the source electrode of the 18 NMOS pipe N18 and the 19 NMOS pipe N19 links to each other with the drain electrode of the 20 NMOS pipe N20, the source electrode of the 20 NMOS pipe N20 links to each other with ground, the 14 NMOS manages N14, the grid of the 17 NMOS pipe N17 links to each other with inverted signal with the positive signal of input signal respectively, the 18 NMOS manages N18, and opposite with the phase place respectively clock of grid of the 19 NMOS pipe N19 links to each other; When the grid of the 18 NMOS pipe N18 are high potential, the function that the latch realization is read in, when the grid of the 18 NMOS pipe N18 are electronegative potential, the function that the latch realization is latched; The grid of the 20 NMOS pipe N20 link to each other with the bias voltage that bandgap voltage reference provides, and form bias current sources; PMOS manages P7, and the substrate of P8 is connected with power supply, provides biasing to the substrate of PMOS pipe, and NMOS manages N14, N15, and N16, N17, N18, N19, the substrate of N20 is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 6, the current switch driver structure of using during this is bright comprises: two PMOS pipe P9, P10, P11, P12, three NMOS pipe N21, N22, N23; Its annexation is:
The 9th PMOS manages P9, and the source electrode of the tenth PMOS pipe P10 connects power supply, and grounded-grid makes the 9th PMOS pipe P9, and the tenth PMOS pipe P10 is operated in dark linear zone, as active load; The source electrode of the 9th PMOS pipe P9 links to each other with power supply, drain electrode and the 22 NMOS pipe N22, and the drain electrode of the 11 PMOS pipe P11 links to each other with the grid of the 21 NMOS pipe N21, exports as the current switch driver forward; The source electrode of the 12 PMOS pipe P12 links to each other with power supply, drain electrode and the 21 NMOS pipe N21, and the drain electrode of the tenth PMOS pipe P10 links to each other with the grid of the 22 NMOS pipe N22, and oppositely exports as current switch driver; The 9th PMOS manages P9, and the grid of the tenth PMOS pipe P10 links to each other with inverted signal with the positive signal of input signal respectively; The 21 NMOS manages N21, and the source electrode of the 22 NMOS pipe N22 links to each other with the drain electrode of the 23 NMOS pipe N23; The grid of the 23 NMOS pipe N23 links to each other with the bias voltage that bandgap voltage reference provides, form bias current sources, by the tenth PMOS pipe P10, the 11 PMOS manages P11, the time-delay that the 21 NMOS pipe N21 and the 22 NMOS pipe N22 introduce between the complementary drive signal of current switch, improve the drive signal crosspoint, avoid the asymmetric problem of drive signal; PMOS manages P9, P10, and P11, the substrate of P12 is connected with power supply, provides biasing to the substrate of PMOS pipe, and NMOS manages N21, N22, the substrate of N23 is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 7, the NMOS current source array structure of using during this is bright comprises: four NMOS pipe N24, N25, N26, N27; Its annexation is:
The 24 NMOS pipe (N24) links to each other with the drain electrode of the 26 NMOS pipe (N26) with the 25 NMOS pipe (N25) source electrode, and the drain electrode of source electrode the 27 NMOS pipe (N27) of the 26 NMOS pipe (N26) links to each other; The 24 NMOS manages (N24), the grid of the 25 NMOS pipe (N25) links to each other with inverted signal with the positive signal of current switch driver output signal respectively, the 24 NMOS manages (N24), and the drain electrode of the 25 NMOS pipe (N25) is respectively the positive signal and the inverted signal of output current signal; The 26 NMOS pipe (N26) links to each other with the bias voltage that bandgap voltage reference provides with the grid of the 27 NMOS pipe (N27), forms bias current sources; The NMOS current source array of this structure is the current source of cascodes, can improve output resistance thus, increases the dynamic property of circuit; NMOS pipe (N24, N25, N26, substrate N27) is connected with ground, provides biasing to the substrate of PMOS pipe.
With reference to Fig. 8, the current switch driver that uses during this is bright, the complementary output waveform under the supply voltage of 1.8V.Its amplitude of oscillation is 0.95V～1.8V, less than half of full swing 0V～1.8V, the crosspoint is apparently higher than the normal intermediate value crosspoint of 0.9V, guaranteed that the 24 NMOS pipe N24 and the 25 NMOS pipe N25 in the NMOS current source array are not turn-offed simultaneously, burr and the trap eliminating output signal effectively and produced improve the linearity of output.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; also can make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. 10 CMOS digital to analog converters based on the MOS current mode logic, comprise: input synchrolock storage, 6～63 thermometer decoders, delay equalizer, latch, current switch driver, NMOS current source array and bandgap voltage references, the input data are connected to 6～63 thermometer decoders and delay equalizer through input synchrolock storage, be connected to latch, current switch driver and NMOS current source array more successively, it is characterized in that:
6～63 thermometer decoders adopt the thermometer decoded device of parallel construction, comprise N MOS current mode logic structure with door/NAND gate logical block with or door/NOR gate logical block, 1＜N＜100;
Delay equalizer is made up of the reverse direction controller of MOS current mode logic structure;
Latch and current switch driver all adopt MOS current mode logic structure;
The NMOS current source array, input is connected with the complementary output end of latch and current switch driver, produces complementary output current.
2. digital to analog converter according to claim 1 is characterized in that: with door/NAND gate logical block, adopt two PMOS pipe (P1, P2), five NMOS pipes (N1, N2, N3, N4, N5); The drain electrode of the one PMOS pipe (P1) links to each other with the drain electrode that a NMOS manages (N1), as the output of NAND Logic; The drain electrode of the 2nd PMOS pipe (P2) and the 2nd NMOS manage the drain electrode that (N2) and the 3rd NMOS manage (N3) and link to each other, as with the output of logic; The one NMOS pipe (N1) links to each other with the drain electrode that the 4th NMOS manages (N4) with the source electrode of the 2nd NMOS pipe (N2), the 3rd NMOS pipe (N3) links to each other with the drain electrode that the 5th NMOS manages (N5) with the source electrode of the 4th NMOS pipe (N4), and the source electrode of the 5th NMOS pipe (N5) links to each other with ground; The one NMOS manages (N1), and the grid of the 2nd NMOS pipe (N2) links to each other with inverted signal with the positive signal of one of them input signal respectively; The 3rd NMOS manages (N3), and the grid of the 4th NMOS pipe (N4) links to each other with inverted signal with the positive signal of another input signal respectively; The grid of the 5th NMOS pipe (N5) links to each other with the bias voltage that bandgap voltage reference provides, and forms bias current sources; (P1, substrate P2) connects power supply to described PMOS pipe, described NMOS pipe (N1, N2, N3, N4, substrate ground connection N5).
3. digital to analog converter according to claim 1 is characterized in that: or door/NOR gate logical block, adopt two PMOS pipes (P3, P4), five NMOS pipes (N6, N7, N8, N9, N10); The drain electrode of the 3rd PMOS pipe (P3) links to each other with the drain electrode that the 6th NMOS manages (N6) and the 8th NMOS pipe (N8), as the output of NOR-logic; The drain electrode of the 4th PMOS pipe (P4) links to each other with the drain electrode that the 7th NMOS manages (N7), as or the output of logic; The 6th NMOS pipe (N6) links to each other with the drain electrode that the 9th NMOS manages (N9) with the source electrode of the 7th NMOS pipe (N7), the 8th NMOS pipe (N8) links to each other with the drain electrode that the tenth NMOS manages (N10) with the source electrode of the 9th NMOS pipe (N9), and the source electrode of the tenth NMOS pipe (N10) links to each other with ground; The 6th NMOS manages (N6), and the grid of the 7th NMOS pipe (N7) links to each other with inverted signal with the positive signal of an input signal respectively; The 8th NMOS manages (N8), and the grid of the 9th NMOS pipe (N9) links to each other with inverted signal with the positive signal of another input signal respectively; The grid of the tenth NMOS pipe (N10) links to each other with the bias voltage that bandgap voltage reference provides, and forms bias current sources; (P3, substrate P4) connects power supply to described PMOS pipe, described NMOS pipe (N6, N7, N8, N9, substrate ground connection N10).
4. digital to analog converter according to claim 1 is characterized in that: inverter, adopt two PMOS pipe (P5, P6), three NMOS pipes (N11, N12, N13); The drain electrode of the 5th PMOS pipe (P5) links to each other with the drain electrode of the 11 NMOS pipe (N11), as alogical output; The drain electrode of the 6th PMOS pipe (P6) links to each other with the drain electrode of the 12 NMOS pipe (N12), as the output identical with input; The source electrode of the 11 NMOS pipe (N11) and the 12 NMOS pipe (N12) links to each other with the drain electrode of the 13 NMOS pipe (N13); The 11 NMOS manages (N11), and the grid of the tenth NMOS pipe (N12) links to each other with inverted signal with the positive signal of input signal respectively; The grid of the 13 NMOS pipe (N13) link to each other with the bias voltage that bandgap voltage reference provides, and form bias current sources; (P5, substrate P6) connects power supply to described PMOS pipe, described NMOS pipe (N11, N12, substrate ground connection N13).
5. according to claim 2 or 3 or 4 described digital to analog converters, it is characterized in that: a PMOS manages (P1), and the 2nd PMOS manages (P2), the 3rd PMOS manages (P3), and the 4th PMOS manages (P4), and the 5th PMOS manages (P5), the source electrode of the 6th PMOS pipe (P6) connects power supply, and grounded-grid makes PMOS pipe (P1), the 2nd PMOS manages (P2), the 3rd PMOS manages (P3), and the 4th PMOS manages (P4), and the 5th PMOS manages (P5), the 6th PMOS pipe (P6) is operated in dark linear zone, as active load;
6. digital to analog converter according to claim 1 is characterized in that: latch, adopt two PMOS pipe (P7, P8), seven NMOS pipes (N14, N15, N16, N17, N18, N19, N20); The drain electrode of the 7th PMOS pipe (P7) and the 14 NMOS pipe (N14), the drain electrode of the 15 NMOS pipe (N15) links to each other with the grid of the 16 NMOS pipe (N16), as the reverse output of latch; The drain electrode of the 8th PMOS pipe (P8) and the 16 NMOS pipe (N16), the drain electrode of the 17 NMOS pipe (N17) links to each other with the grid of the 15 NMOS pipe (N15), as the forward output of latch; The source electrode of the 14 NMOS pipe (N14) and the 17 NMOS pipe (N17) links to each other with the drain electrode of the 18 NMOS pipe (N18), the source electrode of the 15 NMOS pipe (N15) and the 16 NMOS pipe (N16) links to each other with the drain electrode of the 19 NMOS pipe (N19), the source electrode of the 18 NMOS pipe (N18) and the 19 NMOS pipe (N19) links to each other with the drain electrode of the 20 NMOS pipe (N20), the source electrode of the 20 NMOS pipe (N20) links to each other with ground, the 14 NMOS manages (N14), the grid of the 17 NMOS pipe (N17) links to each other with inverted signal with the positive signal of input signal respectively, the 18 NMOS manages (N18), and the clock that the grid of the 19 NMOS pipe (N19) is opposite with phase place respectively links to each other; The grid of the 20 NMOS pipe (N20) link to each other with the bias voltage that bandgap voltage reference provides, and form bias current sources; (P7, substrate P8) connects power supply to described PMOS pipe, described NMOS pipe (N14, N15, N16, N17, N18, N19, substrate ground connection N20).
7. digital to analog converter according to claim 6 is characterized in that: the 7th PMOS manages (P7), and the source electrode of the 8th PMOS pipe (P8) connects power supply, and grounded-grid makes the 7th PMOS pipe (P7), and the 8th PMOS pipe (P8) is operated in dark linear zone, as active load; When the grid of the 18 NMOS pipe (N18) are high potential, the function that the latch realization is read in, when the grid of the 18 NMOS pipe (N18) are electronegative potential, the function that the latch realization is latched;
8. digital to analog converter according to claim 1 is characterized in that: current switch driver, adopt four PMOS pipe (P9, P10, P11, P12), three NMOS pipes (N21, N22, N23); The source electrode of the 9th PMOS pipe (P9) links to each other with power supply, drain electrode and the 22 NMOS pipe (N22), and the drain electrode of the 11 PMOS pipe (P11) links to each other with the grid of the 21 NMOS pipe (N21), exports as the current switch driver forward; The source electrode of the 12 PMOS pipe (P12) links to each other with power supply, drain electrode and the 21 NMOS pipe (N21), and the drain electrode of the tenth PMOS pipe (P10) links to each other with the grid of the 22 NMOS pipe (N22), and oppositely exports as current switch driver; The 9th PMOS manages (P9), and the grid of the tenth PMOS pipe (P10) links to each other with inverted signal with the positive signal of input signal respectively; The 21 NMOS manages (N21), and the source electrode of the 22 NMOS pipe (N22) links to each other with the drain electrode of the 23 NMOS pipe (N23); The grid of the 23 NMOS pipe (N23) links to each other with the bias voltage that bandgap voltage reference provides, form bias current sources, by the tenth PMOS pipe P10, the 11 PMOS manages P11, the time-delay that the 21 NMOS pipe N21 and the 22 NMOS pipe N22 introduce between the complementary drive signal of current switch, improve the drive signal crosspoint, avoid the asymmetric problem of drive signal; Described PMOS pipe (P9, P10, P11, substrate P12) connects power supply, described NMOS pipe (N21, N22, substrate ground connection N23).
9. digital to analog converter according to claim 8 is characterized in that: the 9th PMOS manages (P9), and the source electrode of the tenth PMOS pipe (P10) connects power supply, grounded-grid, make the 9th PMOS pipe (P9), the tenth PMOS pipe (P10) is operated in dark linear zone, as active load.
10. digital to analog converter according to claim 1 is characterized in that: the NMOS current source array, employing four NMOS pipe (N24, N25, N26, N27); The 24 NMOS pipe (N24) links to each other with the drain electrode of the 26 NMOS pipe (N26) with the 25 NMOS pipe (N25) source electrode, and the drain electrode of source electrode the 27 NMOS pipe (N27) of the 26 NMOS pipe (N26) links to each other; The 24 NMOS manages (N24), the grid of the 25 NMOS pipe (N25) links to each other with inverted signal with the positive signal of current switch driver output signal respectively, the 24 NMOS manages (N24), and the drain electrode of the 25 NMOS pipe (N25) is respectively the positive signal and the inverted signal of output current signal; The 26 NMOS pipe (N26) links to each other with the bias voltage that bandgap voltage reference provides with the grid of the 27 NMOS pipe (N27), forms bias current sources; Described NMOS pipe (N24, N25, N26, substrate ground connection N27).
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| CN102006079A (en) * | 2010-12-22 | 2011-04-06 | 复旦大学 | Digital to analog converter |
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Application publication date: 20101208 |