CN105099458A - Thermometer decoder - Google Patents
Thermometer decoder Download PDFInfo
- Publication number
- CN105099458A CN105099458A CN201410195995.1A CN201410195995A CN105099458A CN 105099458 A CN105099458 A CN 105099458A CN 201410195995 A CN201410195995 A CN 201410195995A CN 105099458 A CN105099458 A CN 105099458A
- Authority
- CN
- China
- Prior art keywords
- circuit
- data
- binary data
- output
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
A thermometer decoder comprises a first decoding subunit, a second decoding subunit and 2 (N-M) control modules. The first decoding subunit is suitably used for decoding data within a range from least significant bit data to Mth data among binary data to be decoded into 2M-bit binary data. The second decoding subunit is suitably used for decoding data within a range from the (M+1)th data to the most significant bit data among the binary data to be decoded into 2(N-M)-bit binary data. Each control module comprises 2M control units. The thermometer decoder provided in the invention has characteristics of simple circuit structure, small circuit area and great decoding speed.
Description
Technical field
The present invention relates to digital circuit technique field, particularly a kind of thermometer decoder.
Background technology
In digital system, often needing a kind of code conversion is another kind of code, and to meet specific needs, the circuit completing this function is called a yard change-over circuit.Code change-over circuit comprises encoder and decoder, and wherein, decoder is the code change-over circuit binary code with specific meanings being converted to corresponding output signal.Thermometer decoder, as the one of decoder, is widely used in memory repair design and digital to analog converter.
Table one is the truth table of existing a kind of 3 lines-8-channel temperature monitor decoder, and described 3 lines-8-channel temperature monitor decoder is suitable for the triad data A of input
2a
1a
0be decoded as 8 bit binary data Y
7y
6y
5y
4y
3y
2y
1y
0export.
Table one
| Input | Export |
| A 2A 1A 0 | Y 7Y 6Y 5Y 4Y 3Y 2Y 1Y 0 |
| 000 | 00000001 |
| 001 | 00000011 |
| 010 | 00000111 |
| 011 | 00001111 |
| 100 | 00011111 |
| 101 | 00111111 |
| 110 | 01111111 |
| 111 | 11111111 |
As shown in Table 1, described 8 bit binary data Y
7y
6y
5y
4y
3y
2y
1y
0in, least significant bit (LSB, LeastSignificantBit) data Y
0be the 1st bit data, highest significant position (MSB, MostSignificantBit) data Y
7be the 8th bit data, least significant bit data are binary data 1 to (N+1) bit data, and (N+2) bit data to highest significant position data are binary data 0, and N is described triad data A
2a
1a
0corresponding decimal data.Because of described 8 bit binary data Y
7y
6y
5y
4y
3y
2y
1y
0in, binary data 1 presents notch cuttype change, or the scale change of thermometer is similar, is thus called as thermometer decoder.
Certainly, according to the embody rule environment of thermometer decoder, its truth table has multiple version.Table two is truth tables of existing another kind of 3 lines-8-channel temperature monitor decoder:
Table two
| Input | Export |
| A 2A 1A 0 | Y 7Y 6Y 5Y 4Y 3Y 2Y 1Y 0 |
| 000 | 11111111 |
| 001 | 11111110 |
| 010 | 11111100 |
| 011 | 11111000 |
| 100 | 11110000 |
| 101 | 11100000 |
| 110 | 11000000 |
| 111 | 10000000 |
In prior art, usually can obtain according to the truth table of described 3 lines-8-channel temperature monitor decoder the logical expression that every exports data, export the electrical block diagram of the logical expression acquisition described 3 lines-8-channel temperature monitor decoder of data again by every, every exports the corresponding one group of logic gates of data.Fig. 1 is a kind of electrical block diagram of the 3 lines-8-channel temperature monitor decoder 10 of table one correspondence, described 3 lines-8-channel temperature monitor decoder 10 comprises the first OR-NOT circuit 100, first not circuit 101, second OR-NOT circuit 102, second not circuit 103, OR circuit 104, 3rd OR-NOT circuit 105, 3rd not circuit 106, 4th not circuit 107, 5th not circuit 108, OR circuit 109, first OR-NOT circuit 110, 6th not circuit 111, second OR-NOT circuit 112, 7th not circuit 113, 3rd OR-NOT circuit 114, 8th not circuit 115, 9th not circuit 116, PMOS transistor P10 and nmos pass transistor N10, wherein, the source electrode of described PMOS transistor P10 connects power end Vdd, in described 3 lines-8-channel temperature monitor decoder 10, the annexation of each logic gates is with reference to shown in figure 1.Electrical block diagram or Fig. 1 of the 3 lines-8-channel temperature monitor decoding of table two correspondence are similar, do not repeat them here.
The electrical block diagram of the thermometer decoder of any digit input can be obtained according to the logical expression of every output data, but, when the input data bits of thermometer decoder increases, the circuit structure of described thermometer decoder becomes very complicated, and the area occupied is very large.
Prior art is compared, and technical scheme of the present invention has the following advantages:
Thermometer decoder provided by the invention, according to the truth table characteristic of thermometer decoder, adopts the design of stratification.Respectively with high (N-M) bit data, decoding is carried out to the low M-bit data of binary data to be decoded by two sub-decoding units, carry out 2 of decoding acquisition by low M-bit data
mbit binary data is as 2
n-Mthe input of individual control module, and by high (N-M) bit data decoding obtains 2
n-Mbit binary data controls described 2
n-Mindividual control module, controls each control module and exports described 2
mbit binary data, 2
mbit binary data 1 or 2
mbit binary data 0.By the design of stratification, simplify the circuit structure of thermometer decoder, save circuit area, be easy to realize the decoding to multidigit binary data.
Further, thermometer decoder circuit structure provided by the invention is simple, and signaling rate is fast, improves decoding speed.
Summary of the invention
The problem that what the present invention solved is existing thermometer decoder complex structure, circuit area is large.
For solving the problem, the invention provides a kind of thermometer decoder, comprising the first sub-decoding unit, the second sub-decoding unit and 2
n-Mindividual control module, N is the figure place of binary data to be decoded, and 2≤M≤(N-2), M are positive integer;
Described first sub-decoding unit is suitable for the least significant bit data of described binary data to be decoded to be decoded as 2 to M-bit data
mbit binary data, described 2
mleast significant bit data to the J bit data of bit binary data is binary data 1, described 2
m(J+1) bit data to the highest significant position data of bit binary data are binary data 0, and J is described least significant bit data to decimal data corresponding to M-bit data;
It is 2 that described second sub-decoding unit is suitable for (M+1) bit data to the highest significant position data decoding of described binary data to be decoded
n-Mbit binary data, described 2
n-Mleast significant bit data to the K bit data of bit binary data is binary data 1, described 2
n-M(K+1) bit data to the highest significant position data of bit binary data are binary data 0, and K is described (M+1) bit data to decimal data corresponding to highest significant position data;
Each control module comprises 2
mindividual control unit;
Described control unit comprises first input end, the first output, reset terminal and set end, wherein, described first output is suitable for receiving binary data 0 at described reset terminal, described set termination exports the binary data contrary with the binary data that described first input end receives when receiving binary data 1, the binary data output 0 when described reset terminal and described set end all receive binary data 1, the binary data output 1 when described reset terminal and described set end all receive binary data 0;
In each control module, the first input end of P control unit is suitable for receiving described 2
mthe P bit data of bit binary data, 1≤P≤2
m, P is positive integer;
In Q control module, the reset terminal of each control unit is suitable for receiving described 2
n-Mthe Q bit data of bit binary data, 1≤Q≤2
n-M, Q is positive integer;
In 1st control module, the set termination of each control unit receives binary data 1, and in L control module, the set end of each control unit is suitable for receiving described 2
n-M(L-1) bit data of bit binary data, 2≤L≤2
n-M, L is positive integer.
Optionally, described control unit also comprises the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube and inverter, and described inverter comprises the second input, the second output, the first power end and second source end;
The grid of described first PMOS connects described reset terminal, and the source electrode of described first PMOS connects the source electrode of described second PMOS and is suitable for input first supply voltage, and the drain electrode of described first PMOS connects described first power end;
The grid of described second PMOS connects described set end, and the drain electrode of described second PMOS connects the drain electrode of described first output, described second output and described second NMOS tube;
The grid of described second NMOS tube connects described reset terminal, and the source electrode of described second NMOS tube connects the source electrode of described first NMOS tube and is suitable for input second source voltage, and described second source voltage is lower than described first supply voltage;
The grid of described first NMOS tube connects described set end, and the drain electrode of described first NMOS tube connects described second source end;
Described second input connects described first input end.
Accompanying drawing explanation
Fig. 1 is a kind of electrical block diagram of the 3 lines-8-channel temperature monitor decoder of table one correspondence;
Fig. 2 is the electrical block diagram of the control module of embodiment of the present invention;
Fig. 3 is the circuit diagram of the control unit of the embodiment of the present invention;
Fig. 4 is the electrical block diagram of the first sub-decoding unit of the embodiment of the present invention.
Embodiment
Just as described in the background art, export the thermometer decoder of the logical expression design multidigit binary data of data according to thermometer decoder every, the circuit structure of acquisition area that is complicated, that occupy is large.The invention provides a kind of thermometer decoder, adopt the design of stratification, the circuit structure of described thermometer decoder can be simplified, save circuit area.
Thermometer decoder provided by the invention comprises the first sub-decoding unit, the second sub-decoding unit and 2
n-Mindividual control module, N is the figure place of binary data to be decoded, and 2≤M≤(N-2), M are positive integer.The least significant bit data of described binary data to be decoded are the 1st bit data of described binary data to be decoded, and the highest significant position data of described binary data to be decoded are the N bit data of described binary data to be decoded.
Described first sub-decoding unit is suitable for the least significant bit data of described binary data to be decoded to be decoded as 2 to M-bit data
mbit binary data, described 2
mleast significant bit data to the J bit data of bit binary data is binary data 1, described 2
m(J+1) bit data to the highest significant position data of bit binary data are binary data 0, and J is described least significant bit data to decimal data corresponding to M-bit data.
It is 2 that described second sub-decoding unit is suitable for (M+1) bit data to the highest significant position data decoding of described binary data to be decoded
n-Mbit binary data, described 2
n-Mleast significant bit data to the K bit data of bit binary data is binary data 1, described 2
n-M(K+1) bit data to the highest significant position data of bit binary data are binary data 0, and K is described (M+1) bit data to decimal data corresponding to highest significant position data.
Each control module comprises 2
mindividual control unit, described control unit comprises first input end, the first output, reset terminal and set end, wherein, described first output is suitable for receiving binary data 0 at described reset terminal, described set termination exports the binary data contrary with the binary data that described first input end receives when receiving binary data 1, the binary data output 0 when described reset terminal and described set end all receive binary data 1, the binary data output 1 when described reset terminal and described set end all receive binary data 0.
In each control module, the first input end of P control unit is suitable for receiving described 2
mthe P bit data of bit binary data, 1≤P≤2
m, P is positive integer; In Q control module, the reset terminal of each control unit is suitable for receiving described 2
n-Mthe Q bit data of bit binary data, 1≤Q≤2
n-M, Q is positive integer; In 1st control module, the set termination of each control unit receives binary data 1, and in L control module, the set end of each control unit is suitable for receiving described 2
n-M(L-1) bit data of bit binary data, 2≤L≤2
n-M, L is positive integer.
Described 2
n-Mindividual control module comprises 2
nindividual control unit, described 2
nindividual control unit exports 2
nbit binary data is the decode results of described binary data to be decoded.
Thermometer decoder provided by the invention adopts the design of stratification, carry out decoding by the low M-bit data of described first sub-decoding unit to described binary data to be decoded, height (N-M) bit data of described second sub-decoding unit to described binary data to be decoded carries out decoding, carry out 2 of decoding acquisition by low M-bit data
mbit binary data is as 2
n-Mthe input of individual control module, and by high (N-M) bit data decoding obtains 2
n-Mbit binary data controls described 2
n-Mindividual control module, controls each control module and exports described 2
mbit binary data, 2
mbit binary data 1 or 2
mbit binary data 0.By the design of stratification, simplify the circuit structure of thermometer decoder, save circuit area, be easy to realize the decoding to multidigit binary data.Further, thermometer decoder circuit structure provided by the invention is simple, and signaling rate is fast, improves decoding speed.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
To be described the thermometer decoder of 6 line-64 lines, described thermometer decoder is suitable for 6 binary data A to be decoded
5a
4a
3a
2a
1a
0carry out decoding, i.e. N=6.Therefore, M can equal 2,3 or 4.In the present embodiment, equal 3 for M to be described.Described binary data A to be decoded
5a
4a
3a
2a
1a
0least significant bit data (being also the 1st bit data) be A
0, highest significant position data are A
5.Fig. 2 is the electrical block diagram of the thermometer decoder of the embodiment of the present invention, and described thermometer decoder comprises the first sub-decoding unit 200, second sub-decoding unit 201 and 8 control modules.
Particularly, described first sub-decoding unit 200 is suitable for described binary data A to be decoded
5a
4a
3a
2a
1a
0least significant bit data to the 3rd bit data A
2a
1a
0carry out decoding, by described least significant bit data to the 3rd bit data A
2a
1a
0be decoded as 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0.Described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0least significant bit data to J bit data be binary data 1, described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0(J+1) bit data to highest significant position data be binary data 0, wherein, J is that described least significant bit data are to the 3rd bit data A
2a
1a
0corresponding decimal data.
Table three
| Input | Export |
| A 2A 1A 0 | X 7X 6X 5X 4X 3X 2X 1X 0 |
| 000 | 00000000 |
| 001 | 00000001 |
| 010 | 00000011 |
| 011 | 00000111 |
| 100 | 00001111 |
| 101 | 00011111 |
| 110 | 00111111 |
| 111 | 01111111 |
The truth table of described first sub-decoding unit 200 as shown in Table 3.
Described second sub-decoding unit 201 is suitable for described binary data A to be decoded
5a
4a
3a
2a
1a
0the 4th bit data to highest significant position data A
5a
4a
3carrying out decoding, is 8 bit binary data Z by described 4th bit data to highest significant position data decoding
7z
6z
5z
4z
3z
2z
1z
0.Described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0least significant bit data to K bit data be binary data 1, described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0(K+1) bit data to highest significant position data be binary data 0, wherein, K is that described 4th bit data is to highest significant position data A
5a
4a
3corresponding decimal data.The truth table of described second sub-decoding unit 201 is as shown in Table 4:
Table four
| Input | Export |
| A 5A 4A 3 | Z 7Z 6Z 5Z 4Z 3Z 2Z 1Z 0 |
| 000 | 00000000 |
| 001 | 00000001 |
| 010 | 00000011 |
| 011 | 00000111 |
| 100 | 00001111 |
| 101 | 00011111 |
| 110 | 00111111 |
| 111 | 01111111 |
Continue with reference to figure 2, described 8 control modules be specially the 1st control module 21, the 2nd control module 22, the 8th control module 28.Each control module comprises 8 control units: the 1st control module 21 comprise control unit 211, control unit 212, control unit 218; 2nd control module 22 comprise control unit 221, control unit 222, control unit 228; 8th control module 28 comprise control unit 281, control unit 282, control unit 288.
Described control unit comprises first input end IN, the first output OUT, reset terminal RST and set end SETX.Wherein, described first output OUT is suitable for receiving binary data 0 at described reset terminal RST, described set end SETX exports the binary data contrary with the binary data that described first input end IN receives when receiving binary data 1, the i.e. binary data output 0 when described first input end IN receives binary data 1, the binary data output 1 when described first input end IN receives binary data 0; Described first output OUT is suitable for the binary data output 0 when described reset terminal RST and described set end SETX all receives binary data 1; Described first output OUT is suitable for the binary data output 1 when described reset terminal RST and described set end SETX all receives binary data 0.
In 1st control module 21 in the first input end of the 1st control unit 211, the 2nd control module 22 the 1st control unit 221 first input end, the first input end of the 1st control unit 281 is suitable for receiving described 8 bit binary data X in the 8th control module 28
7x
6x
5x
4x
3x
2x
1x
0the 1st bit data X
0; In 1st control module 21 in the first input end of the 2nd control unit 212, the 2nd control module 22 the 2nd control unit 222 first input end, the first input end of the 2nd control unit 282 is suitable for receiving described 8 bit binary data X in the 8th control module 28
7x
6x
5x
4x
3x
2x
1x
0the 2nd bit data X
1; In 1st control module 21 in the first input end of the 8th control unit 218, the 2nd control module 22 the 8th control unit 228 first input end, the first input end of the 8th control unit 288 is suitable for receiving described 8 bit binary data X in the 8th control module 28
7x
6x
5x
4x
3x
2x
1x
0the 8th bit data X
7.
In 1st control module 21, the reset terminal of each control unit is suitable for receiving described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0the 1st bit data Z
0, in the 1st control module 21, the set termination of each control unit receives binary data 1; In 2nd control module 22, the reset terminal of each control unit is suitable for receiving described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0the 2nd bit data Z
1, in the 2nd control module 22, the set end of each control unit is suitable for receiving described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0the 1st bit data Z
0; In 8th control module 28, the reset terminal of each control unit is suitable for receiving described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0the 8th bit data Z
7, in the 8th control module 28, the set end of each control unit is suitable for receiving described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0the 7th bit data Z
6.
As described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000000, described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0with described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0be 00000000.In described 1st control module 21, the first output of each control unit exports the binary data contrary with the binary data that the first input end of each control unit receives, i.e. Y
7y
1y
0be 11111111; Described 2nd control module 21, the first output binary data output 1, i.e. Y of each control unit in described 8th control module 28
63y
57y
56, Y
15y
9y
8be 11111111.Therefore, as described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000000, the binary data that decoding obtains is 11,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111 11111111.
As described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000001, described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0be 00000001, described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0be 00000000.In described 1st control module 21, the first output of each control unit exports the binary data contrary with the binary data that the first input end of each control unit receives, i.e. Y
7y
1y
0be 11111110; Described 2nd control module 21, the first output binary data output 1, i.e. Y of each control unit in described 8th control module 28
63y
57y
56, Y
15y
9y
8be 11111111.Therefore, as described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000000, the binary data that decoding obtains is 11,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111 11111110.
As described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000010, described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0be 00000011, described 8 bit binary data Z
7z
6z
5z
4z
3z
2z
1z
0be 00000000.In described 1st control module 21, the first output of each control unit exports the binary data contrary with the binary data that the first input end of each control unit receives, i.e. Y
7y
1y
0be 11111100; Described 2nd control module 21, the first output binary data output 1, i.e. Y of each control unit in described 8th control module 28
63y
57y
56, Y
15y
9y
8be 11111111.Therefore, as described binary data A to be decoded
5a
4a
3a
2a
1a
0when being 000000, the binary data that decoding obtains is 11,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111,111 11111100.
The operation principle of the thermometer decoder of the embodiment of the present invention will not enumerate, and truth table and the table 2 of described thermometer decoder are similar.It should be noted that, by simply converting the thermometer decoder of the embodiment of the present invention, also can obtain the truth table similar with table one.Those skilled in the art know and how simply to convert, and do not repeat them here.
The embodiment of the present invention also provides a kind of particular circuit configurations of described control unit, as shown in Figure 3.Described control unit comprises first input end IN, the first output OUT, reset terminal RST and set end SETX, also comprise the first PMOS P31, the second PMOS P32, the first NMOS tube N31, the second NMOS tube N32 and inverter 30, described inverter comprises the second input a3, the second output a4, the first power end a1 and second source end a2.
Particularly, the grid of described first PMOS P31 connects described reset terminal RST, the source electrode of described first PMOS P31 connects the source electrode of described second PMOS P32 and is suitable for input first supply voltage Vdd, and the drain electrode of described first PMOS P31 connects described first power end a1.The grid of described second PMOS P32 connects described set end SETX, and the drain electrode of described second PMOS P32 connects the drain electrode of described first output OUT, described second output a4 and described second NMOS tube NP32.The grid of described second NMOS tube N32 connects described reset terminal RST, and the source electrode of described second NMOS tube N32 connects the source electrode of described first NMOS tube N31 and is suitable for input second source voltage, and described second source voltage is lower than described first supply voltage Vdd.The grid of described first NMOS tube N31 connects described set end SETX, and the drain electrode of described first NMOS tube N31 connects described second source end a2.Described second input a3 connects described first input end IN.Usually, described second source voltage is ground voltage, i.e. the drain electrode of described second NMOS tube N32 and the source ground of described first NMOS tube N31.
The operation principle of the control unit of the embodiment of the present invention is below described.
When described reset terminal RST receives binary data 0, described set end SETX reception binary data 1, described first PMOS P31 and described first NMOS tube N31 conducting, described second PMOS P32 and described second NMOS tube N32 cut-off.Described first supply voltage Vdd transfers to described first power end a1 by described first PMOS P31, described second source voltage transfers to described second source end a2 by described first NMOS tube N31, described inverter 30 works: when described first input end IN receives binary data 1, described first output binary data output 0; When described first input end IN receives binary data 0, described first output binary data output 1.
When described reset terminal RST and described set end SETX all receives binary data 1, described first PMOS P31 and described second PMOS P32 cut-off, described second NMOS tube N32 conducting.Described second source voltage transfers to described first output OUT by described second NMOS tube N32, described first output OUT binary data output 0.
When described reset terminal RST and described set end SETX all receives binary data 0, described first NMOS tube N31 and described second NMOS tube N32 cut-off, described second PMOS P32 conducting.Described first supply voltage transfers to described first output OUT by described second PMOS P32, described first output OUT binary data output 1.
Further, in embodiments of the present invention, described inverter 30 is CMOS inverter.Described inverter 30 also comprises the 3rd PMOS P33 and the 3rd NMOS tube N33.The grid of described 3rd PMOS P33 connects the grid of described 3rd NMOS tube N33 and described second input a3, the source electrode of described 3rd PMOS P33 connects the drain electrode of the described 3rd NMOS tube N33 of drain electrode connection of described first power end a1, described 3rd PMOS P33 and described second output a4; The source electrode of described 3rd NMOS tube N33 connects described second source end a2.
The embodiment of the present invention also provides a kind of particular circuit configurations of described first sub-decoding unit 200, as shown in Figure 4.Described first sub-decoding unit 200 comprises the first not circuit 400, second not circuit 401, the 3rd not circuit 402, the 4th not circuit 407, first NAND gate circuit 403, second NAND gate circuit 404, the 3rd NAND gate circuit 406, OR circuit 405, AND circuit 408, first OR-NOT circuit 409, second OR-NOT circuit 410, the 3rd OR-NOT circuit 411, the 4th PMOS P41 and the 4th NMOS tube N41.
Particularly, the input of described first not circuit 400 is suitable for inputting described binary data A to be decoded
5a
4a
3a
2a
1a
0the first bit data A
0, the input of described second not circuit 401 is suitable for inputting described binary data A to be decoded
5a
4a
3a
2a
1a
0second data A
1, the input of described 3rd not circuit 402 is suitable for inputting described binary data A to be decoded
5a
4a
3a
2a
1a
0the 3rd bit data A
2.
The first input end of described first NAND gate circuit 403 connects the output of described first not circuit 400, second input of described first NAND gate circuit 403 connects the output of described second not circuit 401,3rd input of described first NAND gate circuit 403 connects the output of described 3rd not circuit 402, and the output of described first NAND gate circuit 403 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0the first bit data X
0.
The first input end of described second NAND gate circuit 404 connects the output of described second not circuit 401, second input of described second NAND gate circuit 404 connects the output of described 3rd not circuit 402, and the output of described second NAND gate circuit 404 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0second data X
1.
The first input end of described OR circuit 405 connects the output of described first not circuit 400, second input of described OR circuit 405 connects the output of described second not circuit 401, the first input end of described 3rd NAND gate circuit 406 connects the output of described OR circuit 405, second input of described 3rd NAND gate circuit 406 connects the output of described 3rd not circuit 402, and the output of described 3rd NAND gate circuit 406 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0the 3rd bit data X
2.
The input of described 4th not circuit 407 connects the output of described 3rd not circuit 402, and the output of described 4th not circuit 407 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0four figures according to X
3.
The first input end of described AND circuit 408 connects the output of described first not circuit 400, second input of described AND circuit 408 connects the output of described second not circuit 401, the first input end of described first OR-NOT circuit 409 connects the output of described AND circuit 408, second input of described first OR-NOT circuit 409 connects the output of described 3rd not circuit 402, and the output of described first OR-NOT circuit 409 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0five-digit number according to X
4.
The first input end of described second OR-NOT circuit 410 connects the output of described second not circuit 401, second input of described second OR-NOT circuit 410 connects the output of described 3rd not circuit 402, and the output of described second OR-NOT circuit 410 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0the 6th bit data X
5.
The first input end of described 3rd OR-NOT circuit 411 connects the output of described first not circuit 400, second input of described 3rd OR-NOT circuit 411 connects the output of described second not circuit 401,3rd input of described 3rd OR-NOT circuit 411 connects the output of described 3rd not circuit 402, and the output of described 3rd OR-NOT circuit 411 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0the 7th bit data X
6.
The source electrode of described 4th PMOS P41 is suitable for input first supply voltage Vdd, the grid of described 4th PMOS P41 connects the drain electrode of described 4th PMOS P41 and the grid of described 4th NMOS tube N41, and the drain electrode of described 4th NMOS tube N41 is suitable for exporting described 8 bit binary data X
7x
6x
5x
4x
3x
2x
1x
0eight bit data X
7, the source electrode of described 4th NMOS tube N41 is suitable for input second source voltage, and described second source voltage is lower than described first supply voltage Vdd.Usually, described second source voltage is ground voltage, i.e. the source ground of described 4th NMOS tube N41.
The particular circuit configurations of described second sub-decoding unit 201 and the particular circuit configurations of described first sub-decoding unit 200 similar, do not repeat them here.It should be noted that, the particular circuit configurations of described control unit and described first sub-decoding unit 200 is not limited to the circuit structure cited by the embodiment of the present invention.In other embodiments, described control unit and described first sub-decoding unit 200 can be also other forms of circuit, as long as can realize the function in technical solution of the present invention, the present invention is not construed as limiting this.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can do various change or amendment, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (6)
1. a thermometer decoder, is characterized in that, comprises the first sub-decoding unit, the second sub-decoding unit and 2
n-Mindividual control module, N is the figure place of binary data to be decoded, and 2≤M≤(N-2), M are positive integer;
Described first sub-decoding unit is suitable for the least significant bit data of described binary data to be decoded to be decoded as 2 to M-bit data
mbit binary data, described 2
mleast significant bit data to the J bit data of bit binary data is binary data 1, described 2
m(J+1) bit data to the highest significant position data of bit binary data are binary data 0, and J is described least significant bit data to decimal data corresponding to M-bit data;
It is 2 that described second sub-decoding unit is suitable for (M+1) bit data to the highest significant position data decoding of described binary data to be decoded
n-Mbit binary data, described 2
n-Mleast significant bit data to the K bit data of bit binary data is binary data 1, described 2
n-M(K+1) bit data to the highest significant position data of bit binary data are binary data 0, and K is described (M+1) bit data to decimal data corresponding to highest significant position data;
Each control module comprises 2
mindividual control unit;
Described control unit comprises first input end, the first output, reset terminal and set end, wherein, described first output is suitable for receiving binary data 0 at described reset terminal, described set termination exports the binary data contrary with the binary data that described first input end receives when receiving binary data 1, the binary data output 0 when described reset terminal and described set end all receive binary data 1, the binary data output 1 when described reset terminal and described set end all receive binary data 0;
In each control module, the first input end of P control unit is suitable for receiving described 2
mthe P bit data of bit binary data, 1≤P≤2
m, P is positive integer;
In Q control module, the reset terminal of each control unit is suitable for receiving described 2
n-Mthe Q bit data of bit binary data, 1≤Q≤2
n-M, Q is positive integer;
In 1st control module, the set termination of each control unit receives binary data 1, and in L control module, the set end of each control unit is suitable for receiving described 2
n-M(L-1) bit data of bit binary data, 2≤L≤2
n-M, L is positive integer.
2. thermometer decoder as claimed in claim 1, it is characterized in that, described control unit also comprises the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube and inverter, and described inverter comprises the second input, the second output, the first power end and second source end;
The grid of described first PMOS connects described reset terminal, and the source electrode of described first PMOS connects the source electrode of described second PMOS and is suitable for input first supply voltage, and the drain electrode of described first PMOS connects described first power end;
The grid of described second PMOS connects described set end, and the drain electrode of described second PMOS connects the drain electrode of described first output, described second output and described second NMOS tube;
The grid of described second NMOS tube connects described reset terminal, and the source electrode of described second NMOS tube connects the source electrode of described first NMOS tube and is suitable for input second source voltage, and described second source voltage is lower than described first supply voltage;
The grid of described first NMOS tube connects described set end, and the drain electrode of described first NMOS tube connects described second source end;
Described second input connects described first input end.
3. thermometer decoder as claimed in claim 2, it is characterized in that, described inverter also comprises the 3rd PMOS and the 3rd NMOS tube;
The grid of described 3rd PMOS connects the grid of described 3rd NMOS tube and described second input, the source electrode of described 3rd PMOS connects described first power end, and the drain electrode of described 3rd PMOS connects the drain electrode of described 3rd NMOS tube and described second output;
The source electrode of described 3rd NMOS tube connects described second source end.
4. thermometer decoder as claimed in claim 2, it is characterized in that, described second source voltage is ground voltage.
5. the thermometer decoder as described in any one of Claims 1-4, it is characterized in that, N is 6, M is 3, and described first sub-decoding unit comprises the first not circuit, the second not circuit, the 3rd not circuit, the 4th not circuit, the first NAND gate circuit, the second NAND gate circuit, the 3rd NAND gate circuit, OR circuit, AND circuit, the first OR-NOT circuit, the second OR-NOT circuit, the 3rd OR-NOT circuit, the 4th PMOS and the 4th NMOS tube;
The input of described first not circuit is suitable for the first bit data inputting described binary data to be decoded, the input of described second not circuit is suitable for the second data inputting described binary data to be decoded, and the input of described 3rd not circuit is suitable for the 3rd bit data inputting described binary data to be decoded;
The first input end of described first NAND gate circuit connects the output of described first not circuit, second input of described first NAND gate circuit connects the output of described second not circuit, 3rd input of described first NAND gate circuit connects the output of described 3rd not circuit, and the output of described first NAND gate circuit is suitable for exporting described 2
mfirst bit data of bit binary data;
The first input end of described second NAND gate circuit connects the output of described second not circuit, and the second input of described second NAND gate circuit connects the output of described 3rd not circuit, and the output of described second NAND gate circuit is suitable for exporting described 2
mthe second data of bit binary data;
The first input end of described OR circuit connects the output of described first not circuit, second input of described OR circuit connects the output of described second not circuit, the first input end of described 3rd NAND gate circuit connects the output of described OR circuit, second input of described 3rd NAND gate circuit connects the output of described 3rd not circuit, and the output of described 3rd NAND gate circuit is suitable for exporting described 2
m3rd bit data of bit binary data;
The input of described 4th not circuit connects the output of described 3rd not circuit, and the output of described 4th not circuit is suitable for exporting described 2
mthe four figures certificate of bit binary data;
The first input end of described AND circuit connects the output of described first not circuit, second input of described AND circuit connects the output of described second not circuit, the first input end of described first OR-NOT circuit connects the output of described AND circuit, second input of described first OR-NOT circuit connects the output of described 3rd not circuit, and the output of described first OR-NOT circuit is suitable for exporting described 2
mthe five-digit number certificate of bit binary data;
The first input end of described second OR-NOT circuit connects the output of described second not circuit, and the second input of described second OR-NOT circuit connects the output of described 3rd not circuit, and the output of described second OR-NOT circuit is suitable for exporting described 2
m6th bit data of bit binary data;
The first input end of described 3rd OR-NOT circuit connects the output of described first not circuit, second input of described 3rd OR-NOT circuit connects the output of described second not circuit, 3rd input of described 3rd OR-NOT circuit connects the output of described 3rd not circuit, and the output of described 3rd OR-NOT circuit is suitable for exporting described 2
m7th bit data of bit binary data;
The source electrode of described 4th PMOS is suitable for input first supply voltage, and the grid of described 4th PMOS connects the drain electrode of described 4th PMOS and the grid of described 4th NMOS tube, and the drain electrode of described 4th NMOS tube is suitable for exporting described 2
mthe eight bit data of bit binary data, the source electrode of described 4th NMOS tube is suitable for input second source voltage, and described second source voltage is lower than described first supply voltage.
6. thermometer decoder as claimed in claim 5, it is characterized in that, described second source voltage is ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410195995.1A CN105099458B (en) | 2014-05-09 | 2014-05-09 | Thermometer decoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410195995.1A CN105099458B (en) | 2014-05-09 | 2014-05-09 | Thermometer decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105099458A true CN105099458A (en) | 2015-11-25 |
| CN105099458B CN105099458B (en) | 2018-06-29 |
Family
ID=54579163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410195995.1A Active CN105099458B (en) | 2014-05-09 | 2014-05-09 | Thermometer decoder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105099458B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110703582A (en) * | 2019-09-25 | 2020-01-17 | 天津大学 | Thermometer code to binary code circuit for time-to-digital converter |
| CN113114264A (en) * | 2020-01-10 | 2021-07-13 | 炬芯科技股份有限公司 | Thermometer decoding method and circuit |
| CN115102553A (en) * | 2022-08-26 | 2022-09-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3940595A (en) * | 1974-05-30 | 1976-02-24 | American Medical Electronics Corporation | Electronic thermometer decoder and display system |
| EP0930717A2 (en) * | 1998-01-08 | 1999-07-21 | Fujitsu Mikroelektronik GmbH | Thermometer coding circuitry |
| US6246352B1 (en) * | 1999-07-30 | 2001-06-12 | Texas Instruments Incorporated | Analog-to-digital converter with flush access to digital-to-analog resistor string |
| CN1351422A (en) * | 2000-10-26 | 2002-05-29 | 富士通株式会社 | Segment circuit |
| US6456218B1 (en) * | 1999-11-10 | 2002-09-24 | Fujitsu Limited | Noise shaping in segmented mixed-signal circuitry |
| CN101098145A (en) * | 2006-06-30 | 2008-01-02 | 中华映管股份有限公司 | Digital simulation data transducer and transducing method |
| CN101299610A (en) * | 2008-06-16 | 2008-11-05 | 湖南大学 | High speed digital-analog converter with ten bits current rudder structure |
| CN101373957A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科创微电子（北京）有限公司 | Digital gain control method and circuit |
| CN101908886A (en) * | 2009-12-21 | 2010-12-08 | 西安电子科技大学 | Ten-bit superspeed CMOS digital to analog converter based on MOS current mode logic |
-
2014
- 2014-05-09 CN CN201410195995.1A patent/CN105099458B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3940595A (en) * | 1974-05-30 | 1976-02-24 | American Medical Electronics Corporation | Electronic thermometer decoder and display system |
| EP0930717A2 (en) * | 1998-01-08 | 1999-07-21 | Fujitsu Mikroelektronik GmbH | Thermometer coding circuitry |
| US6246352B1 (en) * | 1999-07-30 | 2001-06-12 | Texas Instruments Incorporated | Analog-to-digital converter with flush access to digital-to-analog resistor string |
| US6456218B1 (en) * | 1999-11-10 | 2002-09-24 | Fujitsu Limited | Noise shaping in segmented mixed-signal circuitry |
| CN1351422A (en) * | 2000-10-26 | 2002-05-29 | 富士通株式会社 | Segment circuit |
| CN101098145A (en) * | 2006-06-30 | 2008-01-02 | 中华映管股份有限公司 | Digital simulation data transducer and transducing method |
| CN101373957A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科创微电子（北京）有限公司 | Digital gain control method and circuit |
| CN101299610A (en) * | 2008-06-16 | 2008-11-05 | 湖南大学 | High speed digital-analog converter with ten bits current rudder structure |
| CN101908886A (en) * | 2009-12-21 | 2010-12-08 | 西安电子科技大学 | Ten-bit superspeed CMOS digital to analog converter based on MOS current mode logic |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110703582A (en) * | 2019-09-25 | 2020-01-17 | 天津大学 | Thermometer code to binary code circuit for time-to-digital converter |
| CN113114264A (en) * | 2020-01-10 | 2021-07-13 | 炬芯科技股份有限公司 | Thermometer decoding method and circuit |
| CN113114264B (en) * | 2020-01-10 | 2023-08-08 | 炬芯科技股份有限公司 | Thermometer decoding method and circuit |
| CN115102553A (en) * | 2022-08-26 | 2022-09-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
| CN115102553B (en) * | 2022-08-26 | 2022-12-23 | 深圳市汇顶科技股份有限公司 | Device for converting binary code into thermometer code and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105099458B (en) | 2018-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104113341A (en) | 12-bit intermediate-rate successive approximation type analog-digital converter | |
| CN102857324B (en) | Low density parity check (LDPC) serial coder in deep space communication and based on lookup table and coding method | |
| CN111256849B (en) | Thermometer decoding structure applied to high-speed DAC circuit | |
| CN207399180U (en) | Reference voltage adaptive circuit structure and related device | |
| CN103078645A (en) | Macrocell and method and circuit for decoding binary codes into thermometer codes | |
| CN103312331A (en) | Analog-digital converter based on memristor | |
| CN105099458A (en) | Thermometer decoder | |
| Ajanya et al. | Thermometer code to binary code converter for flash ADC-a review | |
| CN102799410B (en) | Asynchronous FIFO (first in first out) address conversion circuit based on Lee restricting competition counting coding | |
| CN204376879U (en) | There is the SAR ADC of mixed type DAC capacitor array structure | |
| CN104090859A (en) | Address decoding method based on multi-valued logic circuit | |
| CN104579352B (en) | Code conversion device and method based on the thermometer-code of FPGA to binary code | |
| CN102075192A (en) | High speed digital-analog conversion circuit and operating method thereof | |
| CN102868495B (en) | Lookup table based LDPC (low-density parity-check) serial encoder and encoding method in near-earth communication | |
| CN104158547A (en) | Thermometer code to n-bit binary code parallel conversion device and method | |
| CN115102553B (en) | Device for converting binary code into thermometer code and electronic equipment | |
| CN200976579Y (en) | Reversed phase shift restricted competition metering code circuit | |
| WO2022089429A1 (en) | Decoding method and apparatus | |
| CN104734718A (en) | Hybrid DAC capacitor array structure | |
| CN103618549A (en) | Circuit structure capable of restraining sparkle and metastability of high-speed comparator | |
| Chunn et al. | Comparison of thermometer to binary encoders for flash adcs | |
| CN108880551B (en) | Mainboard circuit, display module assembly and display device | |
| CN102064916B (en) | CMMB standard-based byte interleaving method | |
| CN104168027B (en) | Apparatus of serial conversion from binary code to thermometer code and conversion method thereof | |
| CN102065007B (en) | Configurable data recombining network unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |