CN204376879U - There is the SAR ADC of mixed type DAC capacitor array structure - Google Patents
There is the SAR ADC of mixed type DAC capacitor array structure Download PDFInfo
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- CN204376879U CN204376879U CN201520075639.6U CN201520075639U CN204376879U CN 204376879 U CN204376879 U CN 204376879U CN 201520075639 U CN201520075639 U CN 201520075639U CN 204376879 U CN204376879 U CN 204376879U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 130
- 238000005070 sampling Methods 0.000 claims description 11
- 238000005265 energy consumption Methods 0.000 abstract description 3
- 230000000052 comparative effect Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model discloses a kind of SAR ADC with mixed type DAC capacitor array structure, comprise comparator and mixed type DAC capacitor array structure; Mixed type DAC capacitor array structure comprises: n C2C capacitor array unit, a m binary capacitor array unit and a redundant capacitor, and the described output of mixed type DAC capacitor array structure is connected with the input of comparator; The utility model has the SAR ADC of mixed type DAC capacitor array structure, C2C capacitor array unit and binary capacitor array unit combine by its mixed type DAC capacitor array structure, thus had the advantage that binary weights capacitor array structure (CBW) precision is high, band decay capacitor array structure (BWA) is low in energy consumption concurrently, thus make SAR ADC can better meet various analog electronic equipment to low-power consumption, high-precision demand.
Description
Technical field
The utility model relates to the data converter field in a kind of analog integrated circuit, particularly a kind of capacitor array structure that can reduce gradual approaching A/D converter power consumption.
Background technology
In analog integrated circuit technology, the analog-digital converter (ADC) of successive approximation register type (SAR) is the medium common structure to high-resolution applications of sampling rate lower than 5Msps.The resolution of SAR ADC is generally 8 to 16, has the feature such as low-power consumption, small size.These features make SAR ADC obtain very wide range of application, such as portable, battery powered instrument, pen input quantizer, Industry Control and data signal acquisition device etc.
The DAC module of gradual approaching A/D converter is the key modules of gradual approaching A/D converter, and the reference voltage accuracy that it produces directly affects the conversion accuracy of analog to digital converter.Current have the DAC framework of four kinds to be used to gradual approaching A/D converter: voltage-type, current mode, current steer type and charge redistribution type.Because there is larger quiescent dissipation in the DAC of first three kind, in low-power consumption gradual approaching A/D converter, application is few, and charge redistribution DAC becomes the main selection of low-power consumption gradual approaching A/D converter.Charge redistribution type has again multiple capacitor architecture, and using at present is binary weights array, band decay capacitor array and fractionation capacitor array the most widely.If the thought of band decay electric capacity expanded, access decay electric capacity between each specific capacitance, capacitor array is C2C capacitor array.Binary weights antenna array control is simple and precision is higher, but power consumption is too high is not thus suitable for low power consuming devices.Although band decay capacitor array is low in energy consumption, accuracy is also low.Split the accuracy of capacitor array own higher, and it is also lower to switch power consumption, but specific capacitance quantity is large, DAC switch control rule is also comparatively complicated, and digital logic portion can consume a large amount of power consumption, thus can not meet the demand of low power consuming devices.
Utility model content
In view of this, the purpose of this utility model is to provide a kind of SAR ADC with mixed type DAC capacitor array structure, to solve the problem that existing traditional binary weight array structure (CBW) power consumption is higher, band decay capacitor array structure (BWA) precision is extremely low, to meet the needs of high-precision low-power consumption analog electronic equipment.
The utility model has the SAR ADC of mixed type DAC capacitor array structure, comprises comparator and mixed type DAC capacitor array structure;
Described mixed type DAC capacitor array structure comprises: n C2C capacitor array unit, a m binary capacitor array unit and a redundant capacitor, n C2C unit is corresponding from the 0th to the n-th bit, m binary capacitor array unit corresponding (n+1)th to the n-th+m bit, the wherein total bit number of m+n=;
In n C2C capacitor array unit, total n capacitance is the specific capacitance of C, n-1 capacitance is the electric capacity of 2*C, the node of top crown corresponding to corresponding bits of the specific capacitance that each capacitance is C, in n C2C capacitor array unit, total n node, is connected with the electric capacity that capacitance is 2*C between two adjacent nodes;
In m binary capacitor array unit, total m capacitance is followed successively by 2
1* C, 2
2* C ... 2
m* the electric capacity of C, and the top crown of each electric capacity connects together and has 1 node, this node correspondence the (n+1)th to the n-th+m bit;
In n C2C capacitor array unit, the 1st node that bit is corresponding is connected with redundant capacitor, for the input of capacitor array structure, the node that n-th bit is corresponding is connected to the node that the individual bit of the n-th+m is corresponding with (n+1)th bit, for the output of capacitor array structure, the bottom crown of the electric capacity of each node lower end connects a selector switch selected ground connection or connect power supply;
The described output of mixed type DAC capacitor array structure is connected with the input of comparator.
Further, described mixed type DAC capacitor array structure is two row, the input of two row mixed type DAC capacitor array structure is sampled with one respectively and is kept the difference output end of module to be connected, and the output of two row mixed type DAC capacitor array structure is connected with the positive and negative input of comparator respectively.
Further, described mixed type DAC capacitor array structure is row, and the input of mixed type DAC capacitor array structure is unsettled, output is connected with an input of comparator, and another input of comparator keeps the output of module to be connected with sampling.
The beneficial effects of the utility model: the utility model has the SARADC of mixed type DAC capacitor array structure, C2C capacitor array unit and binary capacitor array unit combine by its mixed type DAC capacitor array structure, thus had the advantage that binary weights capacitor array structure (CBW) precision is high, band decay capacitor array structure (BWA) is low in energy consumption concurrently, thus make SAR ADC can better meet various analog electronic equipment to low-power consumption, high-precision demand.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of mixed type DAC capacitor array structure.
Fig. 2 gets 7 groups of C2C capacitor array unit and 3 groups of binary capacitor array unit for the SAR ADC Organization Chart in single-ended SARADC.
Fig. 3 gets 7 groups of C2C capacitor array unit and 3 groups of binary capacitor array unit for the SAR ADC Organization Chart in both-end SARADC.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described.
Embodiment one, has the SAR ADC of mixed type DAC capacitor array structure, comprises comparator and mixed type DAC capacitor array structure;
As shown in Figure 2, described mixed type DAC capacitor array structure comprises: n C2C capacitor array unit, a m binary capacitor array unit and a redundant capacitor, n C2C unit is corresponding from the 0th to the n-th bit, m binary capacitor array unit corresponding (n+1)th to the n-th+m bit, the wherein total bit number of m+n=;
In n C2C capacitor array unit, total n capacitance is the specific capacitance of C, n-1 capacitance is the electric capacity of 2*C, the node of top crown corresponding to corresponding bits of the specific capacitance that each capacitance is C, in n C2C capacitor array unit, total n node, is connected with the electric capacity that capacitance is 2*C between two adjacent nodes;
In m binary capacitor array unit, total m capacitance is followed successively by 2
1* C, 2
2* C ... 2
m* the electric capacity of C, and the top crown of each electric capacity connects together and has 1 node, this node correspondence the (n+1)th to the n-th+m bit;
In n C2C capacitor array unit, the 1st node that bit is corresponding is connected with redundant capacitor, for the input of capacitor array structure, the node that n-th bit is corresponding is connected to the node that the individual bit of the n-th+m is corresponding with (n+1)th bit, for the output of capacitor array structure, the bottom crown of the electric capacity of each node lower end connects a selector switch selected ground connection or connect power supply;
As shown in Figure 3, described mixed type DAC capacitor array structure is two row, the input of two row mixed type DAC capacitor array structure is sampled with one respectively and is kept the difference output end of module to be connected, and the output of two row mixed type DAC capacitor array structure is connected with the positive and negative input of comparator respectively.
Further, in the present embodiment, often in row mixed type DAC capacitor array structure, C2C capacitor array unit is seven groups, binary capacitor array unit is three groups, certainly in different embodiments, in mixed type DAC capacitor array structure, the quantity of C2C capacitor array unit and binary capacitor array unit also can adjust as required, can better meet various analog electronic equipment to low-power consumption, high-precision demand.
In the present embodiment, the low order end of each row mixed type DAC capacitor array structure is redundant capacitor Cd, is to the right 7 C2C capacitor array unit, then is to the right 3 binary capacitor array unit.
This analog to digital converter from sampling the process producing MSB and all the other Digital sum is:
Reset DAC pole plate switch is seen from left to right, and bottom crown is connected respectively to V
rEF, V
rEF, V
rEF, V
rEF... GND.
The closed sampling switch of sampling, input signal charges to comparator input terminal, cut-off switch after charging, and voltage is V
iN.
MSB comparator carries out first time and compares, and the comparative result obtained is the highest order (MSB) that analog to digital converter exports digital code.
Switch according to comparative result switch-capacitor array bottom crown current potential, if comparative result is 0, then by electric capacity C
9bottom crown switch to GND, C
8bottom crown switches to V
rEF.If comparative result is 1, then by the C of previous column electric capacity
8bottom crown switches to V
rEF.
MSB-1 comparator carries out second time and compares, and the result obtained is analog to digital converter and exports a digital synchronous codes high position (MSB-1).
If switching comparative result is 0, then by the C of previous column capacitor array
8bottom crown switches to GND, and C7 is switched to V
rEF.If comparative result is 1, then by the C of capacitor array
7bottom crown switches to V
rEF.
MSB-2 comparator carries out third time and compares the MSB-2 position obtaining analog to digital converter.Repeat above operation until 10 digit numeric codes have all compared.
Input signal V
iNPand V
iNNbe with
for the differential signal of common-mode signal, their respective voltage ranges are 0 ~ V
rEF.Differential input signal V
iN=V
iNP-V
iNN, scope is-V
rEF~ V
rEF.Therefore this gradual approaching A/D converter 2
10-1 reference potential is respectively 0,
etc..
This analog to digital converter from sampling the process producing MSB and all the other Digital sum is:
Reset DAC pole plate switch is seen from left to right, and the bottom crown of previous column capacitor array is connected respectively to V
rEF, V
rEF, V
rEF, V
rEF... GND; Next column electric capacity is then contrary.
The closed sampling switch of sampling, input signal charges to capacitor array, and the top crown voltage terminating two column capacitance arrays during sampling is respectively V
iNPand V
iNN.
MSB comparator carries out first time and compares, and the comparative result obtained is the highest order (MSB) that analog to digital converter exports digital code.
Switch according to comparative result switch-capacitor array bottom crown current potential, if comparative result is 0, then by the C of previous column electric capacity
9bottom crown switches to V
rEF, C
8bottom crown switches to GND.The operation of next column capacitor array is contrary with it.If comparative result is 1, then by the C of previous column electric capacity
8bottom crown switches to GND, and next column capacitance operation is contrary with it.
MSB-1 comparator carries out second time and compares, and the result obtained is analog to digital converter and exports a digital synchronous codes high position (MSB-1).
If switching comparative result is 0, then by the C of previous column capacitor array
8bottom crown switches to V
rEF, and by C
7switch to GND.The operation of next column electric capacity is contrary; If comparative result is 1, then by the C of previous column capacitor array
7bottom crown switches to GND, and next column capacitance operation is contrary.
MSB-2 comparator carries out third time and compares the MSB-2 position obtaining analog to digital converter.Repeat above operation until 10 digit numeric codes have all compared.
Embodiment two, as shown in Figure 2, the present embodiment has the SAR ADC of mixed type DAC capacitor array structure, comprises comparator and mixed type DAC capacitor array structure;
Described mixed type DAC capacitor array structure comprises: n C2C capacitor array unit, a m binary capacitor array unit and a redundant capacitor, n C2C unit is corresponding from the 0th to the n-th bit, m binary capacitor array unit corresponding (n+1)th to the n-th+m bit, the wherein total bit number of m+n=;
In n C2C capacitor array unit, total n capacitance is the specific capacitance of C, n-1 capacitance is the electric capacity of 2*C, the node of top crown corresponding to corresponding bits of the specific capacitance that each capacitance is C, in n C2C capacitor array unit, total n node, is connected with the electric capacity that capacitance is 2*C between two adjacent nodes;
In m binary capacitor array unit, total m capacitance is followed successively by 2
1* C, 2
2* C ... 2
m* the electric capacity of C, and the top crown of each electric capacity connects together and has 1 node, this node correspondence the (n+1)th to the n-th+m bit;
In n C2C capacitor array unit, the 1st node that bit is corresponding is connected with redundant capacitor, for the input of capacitor array structure, the node that n-th bit is corresponding is connected to the node that the individual bit of the n-th+m is corresponding with (n+1)th bit, for the output of capacitor array structure, the bottom crown of the electric capacity of each node lower end connects a selector switch selected ground connection or connect power supply;
Described mixed type DAC capacitor array structure is row, and the input of mixed type DAC capacitor array structure is unsettled, output is connected with an input of comparator, and another input of comparator keeps the output of module to be connected with sampling.
What finally illustrate is, above embodiment is only in order to illustrate the technical solution of the utility model and unrestricted, although be described in detail the utility model with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify to the technical solution of the utility model or equivalent replacement, and not departing from aim and the scope of technical solutions of the utility model, it all should be encompassed in the middle of right of the present utility model.
Claims (3)
1. there is a SAR ADC for mixed type DAC capacitor array structure, it is characterized in that: comprise comparator and mixed type DAC capacitor array structure;
Described mixed type DAC capacitor array structure comprises: n C2C capacitor array unit, a m binary capacitor array unit and a redundant capacitor, n C2C unit is corresponding from the 0th to the n-th bit, m binary capacitor array unit corresponding (n+1)th to the n-th+m bit, the wherein total bit number of m+n=;
In n C2C capacitor array unit, total n capacitance is the specific capacitance of C, n-1 capacitance is the electric capacity of 2*C, the node of top crown corresponding to corresponding bits of the specific capacitance that each capacitance is C, in n C2C capacitor array unit, total n node, is connected with the electric capacity that capacitance is 2*C between two adjacent nodes;
In m binary capacitor array unit, total m capacitance is followed successively by 2
1* C, 2
2* C ... 2
m* the electric capacity of C, and the top crown of each electric capacity connects together and has 1 node, this node correspondence the (n+1)th to the n-th+m bit;
In n C2C capacitor array unit, the 1st node that bit is corresponding is connected with redundant capacitor, for the input of capacitor array structure, the node that n-th bit is corresponding is connected to the node that the individual bit of the n-th+m is corresponding with (n+1)th bit, for the output of capacitor array structure, the bottom crown of the electric capacity of each node lower end connects a selector switch selected ground connection or connect power supply;
The described output of mixed type DAC capacitor array structure is connected with the input of comparator.
2. the SAR ADC with mixed type DAC capacitor array structure according to claim 1, it is characterized in that: described mixed type DAC capacitor array structure is two row, the input of two row mixed type DAC capacitor array structure is sampled with one respectively and is kept the difference output end of module to be connected, and the output of two row mixed type DAC capacitor array structure is connected with the positive and negative input of comparator respectively.
3. the SAR ADC with mixed type DAC capacitor array structure according to claim 1, it is characterized in that: described mixed type DAC capacitor array structure is row, the input of mixed type DAC capacitor array structure is unsettled, output is connected with an input of comparator, and another input of comparator keeps the output of module to be connected with sampling.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105811986A (en) * | 2016-03-01 | 2016-07-27 | 武汉众为信息技术有限公司 | High-speed conversion successive approximation ADC circuit |
| CN109217874A (en) * | 2018-11-16 | 2019-01-15 | 深圳锐越微技术有限公司 | Surplus shifts loop, gradual approaching A/D converter and gain calibration methods thereof |
| WO2019091358A1 (en) * | 2017-11-07 | 2019-05-16 | 深圳锐越微技术有限公司 | N-bit hybrid structure analog-to-digital converter and integrated circuit chip comprising same |
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| WO2020199165A1 (en) * | 2019-04-03 | 2020-10-08 | 深圳市汇顶科技股份有限公司 | Capacitive analog-to-digital converter, analog-to-digital conversion system, chip, and device |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105811986A (en) * | 2016-03-01 | 2016-07-27 | 武汉众为信息技术有限公司 | High-speed conversion successive approximation ADC circuit |
| CN105811986B (en) * | 2016-03-01 | 2019-04-02 | 武汉众为信息技术有限公司 | A kind of Approach by inchmeal adc circuit of high-speed transitions |
| WO2019091358A1 (en) * | 2017-11-07 | 2019-05-16 | 深圳锐越微技术有限公司 | N-bit hybrid structure analog-to-digital converter and integrated circuit chip comprising same |
| US10965304B2 (en) | 2017-11-07 | 2021-03-30 | Radiawave Technologies Co., Ltd. | N-bit hybrid structure analog-to-digital converter and integrated circuit chip including the same |
| CN109217874A (en) * | 2018-11-16 | 2019-01-15 | 深圳锐越微技术有限公司 | Surplus shifts loop, gradual approaching A/D converter and gain calibration methods thereof |
| CN109217874B (en) * | 2018-11-16 | 2020-11-17 | 深圳锐越微技术有限公司 | Margin transfer loop, successive approximation type analog-to-digital converter and gain calibration method |
| US11296714B2 (en) | 2018-11-16 | 2022-04-05 | Radiawave Technologies Co., Ltd. | Residue transfer loop, successive approximation register analog-to-digital converter, and gain calibration method |
| WO2020199165A1 (en) * | 2019-04-03 | 2020-10-08 | 深圳市汇顶科技股份有限公司 | Capacitive analog-to-digital converter, analog-to-digital conversion system, chip, and device |
| US11159172B2 (en) | 2019-04-03 | 2021-10-26 | Shenzhen GOODIX Technology Co., Ltd. | Capacitive analog-to-digital converter, analog-to-digital conversion system, chip, and device |
| CN110380726A (en) * | 2019-07-25 | 2019-10-25 | 宁波市芯能微电子科技有限公司 | Multidigit analog compensation SAR adc circuit |
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