CN103595412A - Low-power-consumption small-area capacitor array and reset method and logic control method thereof - Google Patents
Low-power-consumption small-area capacitor array and reset method and logic control method thereof Download PDFInfo
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Abstract
The invention discloses a low-power-consumption small-area capacitor array and a reset method and a logic control method of the low-power-consumption small-area capacitor array, and belongs to the technical field of low power consumption of successive approximation A/D converters. The low-power-consumption small-area capacitor array comprises a binary capacitor array, a switch array and four reference voltages and relates to a logic control mode combining capacitor upper plate sampling, switch initiation and capacitor all-in jump. The average consumed power of the capacitor array is 2.3% that of a traditional charge redistribution structure, and the area of the capacitor array is 12.5% that of the traditional charge redistribution structure, and the low-power-consumption small-area capacitor array has the advantages of being simple in structure, small in area, low in power consumption, flexible in match and the like. When the low-power-consumption small-area capacitor array is applied to the successive approximation ADCs, power consumption can be obviously reduced, area can be saved, matching performance and conversion precision can be improved, and moreover under the condition of the same accuracy, reduction of the scale of the capacitor array is favorable for improving A/D conversion efficiency.
Description
Technical field:
The invention belongs to technical field of integrated circuits, relate in particular to a kind of capacitor array and repositioning method and logic control method of low-power consumption small size.
Background technology:
Successively approach (SAR, SAR:Successive-Approximation-Register, successive approximation register) ADC is one of conventional ADC structure type, have the advantages such as simple in structure, easy of integration, the electric charge reallocation type SAR ADC that the capacitor array of take is agent structure relies on its low-power consumption advantage to be applied widely.Yet, along with CMOS(CMOS:Complementary metal oxide semiconductor FET, complementary metal oxide semiconductor field effect transistor) progress of integrated circuit (IC) design technology and technology characteristics size, SoC scale is increasing, to embedding power consumption and the area of ADC wherein, stricter requirement has all been proposed, the scale of traditional electric charge reallocation type SAR ADC capacitor array is index with ADC figure place and doubly increases, and is unfavorable for area, power consumption and speed-optimization.Shown in Fig. 1 is traditional N-bit difference input charge reallocation type SAR ADC structure, and its capacitor array comprises 2 altogether
n+1individual specific capacitance.On the one hand, be subject to the constraint of matching precision, not only circuit area is larger, and process costs is high, and the dynamic power consumption of capacitor array is larger; On the other hand, large-scale capacitor array, causes the input capacitance of SAR ADC larger, affects the raising of ADC sampling rate.
Summary of the invention:
The object of the invention is to overcome the deficiency of conventional charge reallocation type SAR ADC structure, a kind of capacitor array and repositioning method and logic control method of low-power consumption small size are provided, this capacitor array has reduced the scale of capacitor array when realizing equal A/D conversion accuracy, can significantly reduce power consumption, reduce area, save cost, the flexibility that can improve electric capacity compatibility design simultaneously.
For achieving the above object, the technical solution adopted in the present invention is:
A capacitor array for low-power consumption small size, comprises by two groups of capacitor C
0, capacitor C
1, capacitor C
2... capacitor C
n-3capacitor array forms binary system capacitor array, by switch S
0p～switch S
ipand switch S
0n～switch S
inthe capacitor array switch, four reference voltage V that form
ref, V
cm, V
r1and V
r2and differential input signal V
ipand V
in; Wherein N is more than or equal to 3 integer, i=N-3;
V
ipand V
inbe connected respectively on two inputs of comparator positive pole and the V of electric capacity in one group of capacitor array
ipbe connected, positive pole and the V of electric capacity in another group capacitor array
inbe connected;
Switch S
1p～switch S
(N-2) pand switch S
1n～switch S
(N-2) nbe single-pole double-throw switch (SPDT), one end is connected with electric capacity negative pole, the other end one tunnel and V
ref，Yi road ground connection is connected; Switch S
0pand switch S
0nfor single pole multiple throw, one end and capacitor C
0negative pole be connected, the other end is provided with four ，Yi road, road and V
ref，Yi road and V are connected
r1，Yi road and V are connected
r2be connected, last road ground connection.
Described four reference voltages, V
cm=V
ref/ 2, V
r1=V
ref/
4, V
r2=3V
ref/ 4.
A switch arrays sequential repositioning method, S
(N-3) n=S
(N-3) p=" 0 ", S
(N-4) n=S
(N-5) n=... S
1n=S
0n=" 1 ", S
(N-4) p=S
(N-5) p=... S
1p=S
0p=" 1 ", according to B
n-1result change S
(N-3)value, export the corresponding highest order switch of less capacitor array and be connected to V
ref, its control signal S
(N-3)from " 0 ", become " 1 ", and then the size that relatively capacitor array is exported again, second-order digit output B produced
n-2.
Electric capacity entirely descend a saltus step logic control method, in the larger capacitor array of output, electric capacity corresponding to respective counts word bit from V
refbe connected to " 0 ", successively produce B
n-3～B
2, further introduce V
cm, V
r1, V
r2three benchmark, are connected to capacitor C by corresponding reference voltage
1and capacitor C
0, produce B
1and B
0, in whole logic control process, the level that only corresponding capacitance need to be connect reduces, and can further reduce the power consumption of capacitor array.
Compared with prior art, the present invention has following beneficial effect:
The capacitor array of low-power consumption small size of the present invention, takes the sampling of electric capacity top crown, after sampling finishes, by comparator, compares V
ipand V
insize directly produce the output B of highest order
n-1, this process does not consume energy consumption, and because highest order directly produces after sampling finishes, has reduced the scale of capacitor array, and then reduced power consumption, chip area and cost, improves the flexibility of coupling simultaneously.V
cm, V
r1, V
r2three sub-benchmark are only applied in the production process of minimum two, therefore reduced the requirement of antithetical phrase reference precision, make the producing method of subbase standard more flexible, can directly be provided by external voltage source, also can the resistor ladder dividing potential drop by discontinuous operation pattern produce at chip internal, to reduce the power consumption of whole ADC.
The present invention is in sample phase, S
(N-3) n=S
(N-3) p=" 0 ", S
(N-4) n=S
(N-5) n=... S
1n=S
0n=" 1 ", S
(N-4) p=S
(N-5) p=... S
1p=S
0p=" 1 ", makes second-order digit output B on the one hand
n-2production process do not consume energy consumption, also guaranteed that on the other hand follow-up electric capacity descends the logic control mode of saltus step entirely, to reduce power consumption.In addition the sequential resetting technique that, the present invention takes makes the common mode output level of differential configuration capacitor array approach gradually V in the stage that successively approaches
ref/ 2, thus the common mode electrical level excursion of comparator is significantly reduced, under electric capacity, in saltus step process, can effectively reduce because comparator common mode electrical level changes the input offset error causing.
Accompanying drawing explanation:
Fig. 1 is the structural representation of conventional charge reallocation type SAR ADC;
Fig. 2 is the structural representation of SAR ADC of the present invention;
Fig. 3 is the structural representation of 5-bit A/D conversion embodiment of the present invention; Wherein, 3-a is for producing the structural representation of Senior Three position 3MSBs, and 3-b is for producing the structural representation of minimum two 2LSBs;
Fig. 4 is the design sketch that improves that in the embodiment of the present invention, sequential resets to converted-wave;
Fig. 5 is the energy consumption curve figure of 10-bit embodiment of the present invention and conventional charge reallocation structure.
Embodiment:
For the object, technical solutions and advantages of the present invention are expressed clearlyer, below in conjunction with accompanying drawing, the present invention is further described in more detail.At this, embodiments of the invention and explanation are only explanation of the invention, not as a limitation of the invention.
Referring to Fig. 2, the capacitor array of low-power consumption small size of the present invention, comprises by two groups of capacitor C
0, capacitor C
1, capacitor C
2... capacitor C
n-3capacitor array forms binary system capacitor array, by switch S
0p～switch S
ipand switch S
0n～switch S
inthe capacitor array switch, four reference voltage V that form
ref, V
cm, V
r1and V
r2and differential input signal V
ipand V
in; Wherein N is more than or equal to 3 integer, i=N-3; V
ipand V
inbe connected respectively on two inputs of comparator positive pole and the V of electric capacity in one group of capacitor array
ipbe connected, positive pole and the V of electric capacity in another group capacitor array
inbe connected; Switch S
1p～switch S
(N-2) pand switch S
1n～switch S
(N-2) nbe single-pole double-throw switch (SPDT), one end is connected with electric capacity negative pole, the other end one tunnel and V
ref，Yi road ground connection is connected; Switch S
0pand switch S
0nfor single pole multiple throw, one end and capacitor C
0negative pole be connected, the other end is provided with four ，Yi road, road and V
ref，Yi road and V are connected
r1，Yi road and V are connected
r2be connected, last road ground connection.Described four reference voltages, V
cm=V
ref/ 2, V
r1=V
ref/
4, V
r2=3V
ref/ 4.
The invention also discloses a kind of switch arrays sequential repositioning method of capacitor array, S
(N-3) n=S
(N-3) p=" 0 ", S
(N-4) n=S
(N-5) n=... S
1n=S
0n=" 1 ", S
(N-4) p=S
(N-5) p=... S
1p=S
0p=" 1 ", according to B
n-1result change S
(N-3)value, export the corresponding highest order switch of less capacitor array and be connected to V
ref, its control signal S
(N-3)from " 0 ", become " 1 ", and then the size that relatively capacitor array is exported again, second-order digit output B produced
n-2.
The electric capacity that the invention also discloses a kind of capacitor array descends saltus step logic control method entirely, in the larger capacitor array of output, electric capacity corresponding to respective counts word bit from V
refbe connected to " 0 ", successively produce B
n-3～B
2, further introduce V
cm, V
r1, V
r2three benchmark, are connected to capacitor C by corresponding reference voltage
1and capacitor C
0, produce B
1and B
0, in whole logic control process, the level that only corresponding capacitance need to be connect reduces, and can further reduce the power consumption of capacitor array.
Circuit structure of the present invention and principle:
As shown in Figure 1, in conventional charge reallocation type SAR ADC structure, take the sampling of electric capacity bottom crown and traditional mode of successively approaching, C
0, C
1, C
2... C
n-1form binary system capacitor array, C
0=C
1, C
i=2C
i-1, i=1～N-1; S
ip, S
in(i=0～N-1) is capacitor array switch; V
ipand V
infor differential input signal; V
reffor voltage reference.Whole capacitor array is not only larger, and area, power consumption and process costs are higher, and capacitor array causes the input capacitance of SAR ADC larger on a large scale, causes overall work limited speed.
The comparison (10-bit ADC) of table 1 the present invention and conventional charge reallocation structure
In upper table, take 10-bit ADC as example, in capacitor array scale, number of switches and capacitor array energy consumption aspect compare the present invention and conventional charge reallocation structure, shown in Fig. 5 is the energy consumption curve of 10-bit embodiment of the present invention and conventional charge reallocation structure, capacitor array structure provided by the invention has obvious advantage, capacitor array scale and number of switches are only 12.5% of conventional charge reallocation structure, energy consumption is only 2.3% of traditional structure, in addition, capacitor array provided by the invention is for SAR ADC, can effectively reduce the input capacitance of ADC, improve A/D switching rate.
With reference to Fig. 3, show the present invention and with 2-bit capacitor array, in conjunction with a plurality of benchmark, complete the embodiment of 5-bit mould/number conversion.Wherein, C
2=2C and C
1=C
0=C forms capacitor array, in sample phase, and V
ipand V
inas differential input signal, be connected to respectively the top crown of differential capacitance array, take capacitor array switching sequence resetting technique simultaneously, another C
2bottom crown is connected to " 0 ", C
1and C
0bottom crown be connected to " 1 ".For structure of the present invention and principle are explained clearlyer, respectively from high 3 (3MSBs, Fig. 3-a) be described respectively with minimum two (2LSBs, Fig. 3-b).Technical scheme is clearly expressed for convenience of follow-up, respectively will with V
ipand V
inconnected capacitor array is called capacitor P array and electric capacity N array, and the output of capacitor array is called V
opand V
on.
B
4generation: with reference to Fig. 3-a, after sampling finishes, disconnect V
ipand V
inwith being connected between capacitor array top crown, V
op4=V
ip, V
on4=V
in, by comparator, compare V
op4and V
on4size, directly produce top digit output B
4if, V
op4> V
on4, V
ip> V
in, B
4=" 1 ", otherwise, B
4=" 0 ".In this process, capacitor array does not consume energy consumption.
B
3generation: with reference to Fig. 3-a, if B
4=" 1 ", keeps V
op3=V
op4=V
ipconstant, by C in electric capacity N array
2bottom crown be connected to " 1 ", make V
on3=V
in+ V
ref/ 2, and then compare V
ipand V
in+ V
ref/ 2 size, if V
ip> V
in+ V
ref/ 2, B
3=" 1 ", otherwise, B
3=" 0 "; On the contrary, if B
4=" 0 ", keeps V
on3=V
on4=V
inconstant, by C in capacitor P array
2bottom crown be connected to " 1 ", make V
op3=V
ip+ V
ref/ 2, and then compare V
inand V
ip+ V
ref/ 2 size, if V
ip+ V
ref/ 2 > V
in, B
3=" 1 ", otherwise, B
3=" 0 ".At B
3the generation stage, the electric capacity bottom crown of electric capacity N array or P array connects and from " 011 ", becomes " 111 ", capacitor C in this process
2the energy that=2C charging consumes is just in time by C
1=C and C
0=C electric discharge provides, and does not consume on the whole extra energy consumption.
B
2generation take saltus step logic control mode under electric capacity, with reference to Fig. 3-a, according to B
3result, if B
3=" 1 ", keeps V
on2=V
on3constant, by capacitor C in capacitor P array
1by " 1 " lower saltus step, to " 0 ", make V
opreduce V
ref/ 4, V
op2=V
op3-V
ref/ 4; If B
3=" 0 ", keeps V
op2=V
op3constant, by capacitor C in electric capacity N array
1by " 1 " lower saltus step, to " 0 ", make V
onreduce V
ref/ 4, V
on2=V
on3-V
ref/ 4; Compare V
op2and V
on2size, if V
op2> V
on2, B
2=" 1 ", otherwise, B
2=" 0 ".This process only completes by saltus step under electric capacity, has simplified successively the electric capacity saltus step mode in approximate procedure, is also conducive to the linear optimization of ADC when reducing power consumption.
B
1generation, under electric capacity on the basis of saltus step, introduce benchmark V
cm, with reference to Fig. 3-b, according to B
2result, if B
2=" 1 ", keeps V
on1=V
on2constant, by capacitor C in capacitor P array
0by " 1 " lower saltus step, to " 0.5 ", (" 0.5 " represents that this electric capacity meets V
cm), make V
opreduce V
ref/ 8, V
op1=V
op2-V
ref/ 8; If B
2=" 0 ", keeps V
op1=V
op2constant, by capacitor C in electric capacity N array
0by " 1 " lower saltus step, to " 0.5 ", make V
onreduce V
ref/ 8, V
on1=V
on2-V
ref/ 8; Compare V
op1and V
on1size, if V
op1> V
on1, B
1=" 1 ", otherwise, B
1=" 0 ".
B
0generation, on above operation principle basis, further introduce benchmark V
r1and V
r2(V
r1=V
ref/
4, V
r2=3V
ref/ 4), with reference to Fig. 3-b, according to B
1result, if B
1=" 1 ", keeps V
on0=V
on1constant, by capacitor C in capacitor P array
0by " 0.5 " lower saltus step, to " 0.25 ", (" 0.25 " represents that this electric capacity meets V
r1), or by " 1 " lower saltus step, to " 0.75 ", (" 0.75 " represents that this electric capacity meets V
r2), make V
opreduce V
ref/ 16, V
op0=V
op1-V
ref/ 16; If B
1=" 0 ", keeps V
op0=V
op1constant, by capacitor C in electric capacity N array
0by " 1 ", descend saltus step to " 0.75 ", or to " 0.25 ", make V by " 0.5 " lower saltus step
onreduce V
ref/ 16, V
on0=V
on1-V
ref/ 16; Compare V
op0and V
on0size, if V
op0> V
on0, B
0=" 1 ", otherwise, B
0=" 0 ".
With reference to Fig. 3-a and Fig. 3-b, in above embodiment, the energy consumption that capacitor array consumes in approximate procedure is successively with CV
ref 2form mark in the drawings.
With reference to Fig. 4, show capacitance switch sequential resetting technique of the present invention to successively approaching the improvement of waveform.In order to reduce power consumption, the present invention has taked electric capacity entirely to descend the logic control mode of saltus step, makes the common mode exporting change of differential capacitance array larger, and then because common mode electrical level variation can cause the input offset error of comparator.In order to overcome the above problems, the present invention, before electric capacity descends saltus step logic control entirely, resets to the logical sequence of capacitive switch array, has effectively improved above problem.
In the embodiment of other precision capacitor array of the present invention, the generation of the minimum two digits output of the highest sum-bit is identical with above-mentioned 5-bit embodiment, the B in other a few bit digital output and 5-bit embodiment
2generation similar, all adopt the logic control mode of saltus step under electric capacity.With reference to Fig. 5, contrasted the energy consumption of 10-bit embodiment of the present invention and conventional charge reallocation structure, the average energy consumption of capacitor array of the present invention is only 2.3% of traditional structure, has reduced 97.7%.
The invention provides a kind of novel capacitor array for successive approximation analog to digital C, combine saltus step and many benchmark technology under top crown sampling, electric capacity, can significantly reduce power consumption, by introducing capacitance switch sequential, reset, effectively reduced the common mode exporting change scope of time saltus step differential capacitance array, and then can effectively improve because comparator common mode electrical level changes the input offset error causing, in addition, capacitor array scale of the present invention is less, not only can reduce chip area, reduce costs, and be conducive to improve A/D switching rate.
The above is preferred embodiment of the present invention, not in order to limit the present invention, every within the spirit and principles in the present invention scope, and that does is anyly equal to replacement, retouching and improvement etc., all should be considered as protection scope of the present invention.
Claims (4)
1. a capacitor array for low-power consumption small size, is characterized in that: comprise by two groups of capacitor C
0, capacitor C
1, capacitor C
2... capacitor C
n-3capacitor array forms binary system capacitor array, by switch S
0p～switch S
ipand switch S
0n～switch S
inthe capacitor array switch, four reference voltage V that form
ref, V
cm, V
r1and V
r2and differential input signal V
ipand V
in; Wherein N is more than or equal to 3 integer, i=N-3;
V
ipand V
inbe connected respectively on two inputs of comparator positive pole and the V of electric capacity in one group of capacitor array
ipbe connected, positive pole and the V of electric capacity in another group capacitor array
inbe connected;
Switch S
1p～switch S
(N-2) pand switch S
1n～switch S
(N-2) nbe single-pole double-throw switch (SPDT), one end is connected with electric capacity negative pole, the other end one tunnel and V
ref，Yi road ground connection is connected; Switch S
0pand switch S
0nfor single pole multiple throw, one end and capacitor C
0negative pole be connected, the other end is provided with four ，Yi road, road and V
ref，Yi road and V are connected
r1，Yi road and V are connected
r2be connected, last road ground connection.
2. the capacitor array of low-power consumption small size according to claim 1, is characterized in that: described four reference voltages, V
cm=V
ref/ 2, V
r1=V
ref/
4, V
r2=3V
ref/ 4.
3. a switch arrays sequential repositioning method for capacitor array as claimed in claim 1, is characterized in that: S
(N-3) n=S
(N-3) p=" 0 ", S
(N-4) n=S
(N-5) n=... S
1n=S
0n=" 1 ", S
(N-4) p=S
(N-5) p=... S
1p=S
0p=" 1 ", according to B
n-1result change S
(N-3)value, export the corresponding highest order switch of less capacitor array and be connected to V
ref, its control signal S
(N-3)from " 0 ", become " 1 ", and then the size that relatively capacitor array is exported again, second-order digit output B produced
n-2.
4. the electric capacity of capacitor array descends a saltus step logic control method entirely as claimed in claim 1, it is characterized in that: in the larger capacitor array of output, electric capacity corresponding to respective counts word bit from V
refbe connected to " 0 ", successively produce B
n-3～B
2, further introduce V
cm, V
r1, V
r2three benchmark, are connected to capacitor C by corresponding reference voltage
1and capacitor C
0, produce B
1and B
0, in whole logic control process, the level that only corresponding capacitance need to be connect reduces, and can further reduce the power consumption of capacitor array.
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| CN104485960A (en) * | 2015-01-06 | 2015-04-01 | 吴江圣博瑞信息科技有限公司 | Three-level switching method and circuit for successive approximation type analog-digital converter |
| CN104485961A (en) * | 2015-01-06 | 2015-04-01 | 吴江圣博瑞信息科技有限公司 | Monotonic switching method and circuit for successive approximation type analog-digital converter |
| CN104734721A (en) * | 2015-02-03 | 2015-06-24 | 国网重庆市电力公司电力科学研究院 | Low-power-consumption Radix-4 charge weight distributed type DAC and switching technology |
| CN105187065A (en) * | 2015-07-17 | 2015-12-23 | 西安邮电大学 | Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof |
| CN105391451A (en) * | 2015-11-30 | 2016-03-09 | 江苏芯力特电子科技有限公司 | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof |
| CN105811986A (en) * | 2016-03-01 | 2016-07-27 | 武汉众为信息技术有限公司 | High-speed conversion successive approximation ADC circuit |
| CN108111171A (en) * | 2017-12-19 | 2018-06-01 | 中山大学花都产业科技研究院 | Suitable for differential configuration gradual approaching A/D converter dullness formula method of switching |
| CN112039528A (en) * | 2020-07-22 | 2020-12-04 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN112865796A (en) * | 2021-01-21 | 2021-05-28 | 电子科技大学中山学院 | Analog-to-digital converter and control method thereof |
| CN112965588A (en) * | 2021-02-02 | 2021-06-15 | 核芯互联科技(青岛)有限公司 | Sequential batch reset method and system |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
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| CN104485961A (en) * | 2015-01-06 | 2015-04-01 | 吴江圣博瑞信息科技有限公司 | Monotonic switching method and circuit for successive approximation type analog-digital converter |
| CN104485960A (en) * | 2015-01-06 | 2015-04-01 | 吴江圣博瑞信息科技有限公司 | Three-level switching method and circuit for successive approximation type analog-digital converter |
| CN104734721B (en) * | 2015-02-03 | 2018-09-04 | 国网重庆市电力公司电力科学研究院 | Low-power consumption Radix-4 charge redistribution type DAC and switching method |
| CN104734721A (en) * | 2015-02-03 | 2015-06-24 | 国网重庆市电力公司电力科学研究院 | Low-power-consumption Radix-4 charge weight distributed type DAC and switching technology |
| CN105187065A (en) * | 2015-07-17 | 2015-12-23 | 西安邮电大学 | Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof |
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| CN105391451B (en) * | 2015-11-30 | 2018-12-04 | 江苏芯力特电子科技有限公司 | Switching method when a kind of gradual approaching A/D converter and its analog-to-digital conversion |
| CN105811986A (en) * | 2016-03-01 | 2016-07-27 | 武汉众为信息技术有限公司 | High-speed conversion successive approximation ADC circuit |
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| CN108111171A (en) * | 2017-12-19 | 2018-06-01 | 中山大学花都产业科技研究院 | Suitable for differential configuration gradual approaching A/D converter dullness formula method of switching |
| CN108111171B (en) * | 2017-12-19 | 2021-11-09 | 中山大学花都产业科技研究院 | Monotonic switching method suitable for differential structure successive approximation type analog-to-digital converter |
| CN112039528A (en) * | 2020-07-22 | 2020-12-04 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN112039528B (en) * | 2020-07-22 | 2022-11-29 | 重庆中易智芯科技有限责任公司 | Capacitor array logic control method in successive approximation analog-to-digital converter |
| CN112865796A (en) * | 2021-01-21 | 2021-05-28 | 电子科技大学中山学院 | Analog-to-digital converter and control method thereof |
| CN112965588A (en) * | 2021-02-02 | 2021-06-15 | 核芯互联科技(青岛)有限公司 | Sequential batch reset method and system |
| CN112968704A (en) * | 2021-02-03 | 2021-06-15 | 电子科技大学 | Successive approximation type analog-to-digital converter based on transient capacitance switching mode and quantization method thereof |
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