CN105187065B - Successive approximation analog to digital C super low-power consumption capacitor array and its logic control method - Google Patents
Successive approximation analog to digital C super low-power consumption capacitor array and its logic control method Download PDFInfo
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Abstract
The invention discloses a kind of successive approximation analog to digital C super low-power consumption capacitor array and its logic control methods, belong to the ultralow Consumption technical field of successive approximation analog to digital C, including binary capacitor array and switch arrays, benchmark (Vref、Vcm=Vref/ 2 and Gnd=0) and combine the sampling of capacitor top crown, switch control time sequence to initialize, the new logic control mode of the reduction of parasitic capacitance power consumption and the switching of capacitor dullness, capacitor array average energy consumption disclosed by the invention is only the 1.2% of conventional charge reallocation structure, has many advantages, such as that structure is simple, low in energy consumption, area is small.Apply the present invention to successive approximation analog to digital C, power consumption can be significantly reduced, and under same conversion accuracy, the reduction of capacitor array scale of the present invention also advantageously improves A/D conversion rate.
Description
Technical field
The invention belongs to technical field of integrated circuits more particularly to a kind of super low-power consumption capacitors for successive approximation analog to digital C
Array and its logic control method.
Background technique
Charge scaling type Approach by inchmeal (SAR) ADC of structure based on capacitor array is obtained by its low-power consumption advantage
Extensive use was obtained, with the progress of CMOS IC design technology and the reduction of technology feature size, SoC scale is increasingly
Greatly, especially in nerve signal record (EEG, ECOG etc.) implantating biological electronic system, the ADC being embedded needs to have
Super low-power consumption, miniaturization the characteristics of, the scale of traditional Charge scaling type SAR ADC capacitor array with ADC digit exponentially
Increase again, is unfavorable for area, power consumption and speed-optimization.Shown in FIG. 1 is traditional N-bit fully differential Charge scaling type SAR
ADC structure, capacitor array include 2 altogetherN+1A specific capacitance.On the one hand, by the constraint of matching precision and noiseproof feature, no
Only circuit area is larger, and process costs are high, and the dynamic power consumption of capacitor array is larger；On the other hand, large-scale capacitor battle array
Column, cause the input capacitance of SAR ADC larger, not only influence the raising of ADC sampling rate, but also require AFE(analog front end) (AFE)
Circuit has stronger driving capability, influences AFE circuitry and the low-power consumption optimization of entire SoC.
Summary of the invention
It is an object of the invention to overcome the above-mentioned prior art, a kind of successive approximation analog to digital C super low-power consumption electricity is provided
Hold array and its logic control method can significantly reduce with super low-power consumption, miniaturized capacitance array and logic control mode
The power consumption of SAR ADC reduces chip area, saves cost, while can improve the flexibility of capacitor array compatibility design.
The purpose of the present invention is achieved through the following technical solutions：
Successive approximation analog to digital C super low-power consumption capacitor array of the invention, two inputs of comparator are connected to including two groups
(the N-2)-bit binary capacitor array at end, every group of (N-2)-bit binary capacitor array connect voltage base by switch arrays
Quasi- Vref, Vcm, Gnd；Every group of (N-2)-bit binary capacitor array is by capacitor C0、C1、C2、……CN-2Connection composition, wherein N is
Natural number；The capacitor C of first group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2To be separately connected difference defeated for one end
Enter signal Vip, the switch that the other end of each capacitor passes through in switch arrays respectively is connected to voltage reference Vref, Vcm, Gnd；Second
The capacitor C of group (N-2)-bit binary capacitor array0、C1、C2、……CN-2One end be separately connected differential input signal Vin, separately
The switch that one end passes through in switch arrays respectively is connected to voltage reference Vref, Vcm, Gnd；The output end connection of comparator is gradually forced
Nearly logic control element SAR Logic, according to the output of comparator, the Approach by inchmeal logic control element SAR Logic exists
The logic control switched to capacitor array is realized under the action of clock signal clk and soc, and generates the numeral output B of ADC0-
BN-1。
Further, the above C0=C1, Ci=2Ci-1, i=1~N-2.
Further, the switch arrays connecting with first group of (N-2)-bit binary capacitor array are first switch array, the
One switch arrays are by switch S0p、S1p、S2p、……S(N-2)pComposition.
Further, the switch arrays connecting with second group of (N-2)-bit binary capacitor array are second switch array, the
Two switch arrays are by switch S0n、S1n、S2n、……S(N-2)nComposition.
The present invention also proposes a kind of logic control method of above-mentioned successive approximation analog to digital C super low-power consumption capacitor array：
(1) in sample phase, switch arrays timing initialization technique, S are taken(N-2)n=S(N-2)p=" 1 ", S(N-3)n=
S(N-4)n=... S1n=S0n=" 0 ", S(N-3)p=S(N-4)p=... S1p=S0p=" 0 ", according to BN-1Result change S(N-2)
(S(N-2)nOr S(N-2)p) value, export the control signal S of highest bit switch corresponding to biggish capacitor array(N-2)By " 1 "
It is connected to " 0 ", and then compares the size of capacitor array output again, second-order digit is generated and exports BN-2；" 1 " and " 0 " respectively represents
Respective switch is by the capacitance connection corresponding to it to VrefAnd Gnd；
(2) by using top crown sampling and switch arrays logical sequence initialization technique, highest order and the are being generated
Binary digit does not need benchmark and provides energy consumption during exporting；B is exported generating third bit digitalN-3When, if upper jump,
Capacitor array switch control signal is become " 11/21/2 ... 1/2 " from " 100 ... 0 ", and energy consumption is-CN-2Vref 2/2；If under
Jump, capacitor array switch control signal become " 1/200 ... 0 " from " 100 ... 0 ", and energy consumption is also-CN-2Vref 2/2；"1/
2 " represent respective switch for the capacitance connection corresponding to it to Vcm, Vcm=Vref/2。
Further, in above method, in the numeral output B for generating front threeN-1-BN-3Later, in subsequent conversion process
Middle capacitor array takes dull switch logic control mode, the change that connection relationship occurs for an only capacitor in each clock cycle
Change.
Further, B is exported above according to second-order digitN-2Difference, the variation of the common mode output level of capacitor array is in
Existing two kinds of trend：
If 1) BN-2Logic 1 is exported, capacitor array needs to occur jump to generate third position output BN-3, capacitor array is total
Mould output level gradually approaches V during Approach by inchmealref/2；
If 2) BN-2Logical zero is exported, capacitor array needs to occur lower jump to generate third position output BN-3, capacitor array is total
Mould output level gradually approaches V during Approach by inchmealref/4。
The invention has the advantages that：
Capacitor array structure provided by the invention has apparent advantage, and capacitor array scale and number of switches are only tradition
The 25% of Charge scaling structure and 38.5%, in the case where not considering parasitic capacitance energy consumption, capacitor array energy consumption is only to pass
The 1.2% of structure of uniting, in the case where considering parasitic capacitance energy consumption, with Cpt=0.1Ctot,CpbFor=0.15C, the present invention is mentioned
The energy consumption of the capacitor array of confession is only the 1.4% of conventional charge reallocation structure.
Detailed description of the invention
Fig. 1 is conventional charge reallocation type SAR ADC structure；
Fig. 2 is novel SAR ADC structure of the invention；
Fig. 3 is 4-bit A/D conversion embodiment of the invention；
A, the generation of highest two digits output,
B, the generation of minimum two digits output；
Fig. 4 is improvement of the logic control mode to converted-wave in the embodiment of the present invention；
Fig. 5 is improvement of the logic control mode to parasitic capacitance power consumption in the embodiment of the present invention；
Fig. 6 is the energy consumption curve of 10-bit embodiment of the present invention and conventional charge reallocation structure；
Specific embodiment
Present invention firstly provides successive approximation analog to digital C super low-power consumption capacitor arrays：Comparator is connected to including two groups
(N-2)-bit binary capacitor array of two input terminals, every group of (N-2)-bit binary capacitor array are connected by switch arrays
Voltage reference Vref, Vcm, Gnd；Every group of (N-2)-bit binary capacitor array is by capacitor C0、C1、C2、……CN-2Connection composition,
Wherein N is natural number；The capacitor C of first group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2One end connect respectively
Meet differential input signal Vip, the switch that the other end of each capacitor passes through in switch arrays respectively is connected to voltage reference Vref, Vcm,
Gnd；The capacitor C of second group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2One end be separately connected Differential Input
Signal Vin, the switch that the other end passes through in switch arrays respectively is connected to voltage reference Vref, Vcm, Gnd；The output end of comparator
Connect Approach by inchmeal logic control element SAR Logic, according to the output of comparator, the Approach by inchmeal logic control element
SAR Logic realizes the logic control switched to capacitor array under the action of clock signal clk and soc, and generates the number of ADC
Word exports B0-BN-1。
The wherein above C0=C1, Ci=2Ci-1, i=1~N-2.It is connect with first group of (N-2)-bit binary capacitor array
Switch arrays be first switch array, first switch array is by switch S0p、S1p、S2p、……S(N-2)pComposition.With second group
(N-2) switch arrays of-bit binary capacitor array connection are second switch array, and second switch array is by switch S0n、S1n、
S2n、……S(N-2)nComposition.
Logic control method based on the above successive approximation analog to digital C super low-power consumption capacitor array is as follows：
(1) in sample phase, switch arrays timing initialization technique, S are taken(N-2)n=S(N-2)p=" 1 ", S(N-3)n=
S(N-4)n=... S1n=S0n=" 0 ", S(N-3)p=S(N-4)p=... S1p=S0p=" 0 ", according to BN-1Result change S(N-2)
(S(N-2)nOr S(N-2)p) value, export the control signal S of highest bit switch corresponding to biggish capacitor array(N-2)By " 1 "
It is connected to " 0 ", and then compares the size of capacitor array output again, second-order digit is generated and exports BN-2；" 1 " and " 0 " respectively represents
Respective switch is by the capacitance connection corresponding to it to VrefAnd Gnd；
(2) by using top crown sampling and switch arrays logical sequence initialization technique, highest order and the are being generated
Binary digit does not need benchmark and provides energy consumption during exporting；B is exported generating third bit digitalN-3When, if upper jump,
Capacitor array switch control signal is become " 11/21/2 ... 1/2 " from " 100 ... 0 ", and energy consumption is-CN-2Vref 2/2；If under
Jump, capacitor array switch control signal become " 1/200 ... 0 " from " 100 ... 0 ", and energy consumption is also-CN-2Vref 2/2；"1/
2 " represent respective switch for the capacitance connection corresponding to it to Vcm, Vcm=Vref/2。
In above method：In the numeral output B for generating front threeN-1-BN-3Later, the capacitor battle array in subsequent conversion process
Column take dull switch logic control mode, the variation that connection relationship occurs for an only capacitor in each clock cycle.According to
Second-order digit exports BN-2Difference, two kinds of trend are presented in the variation of the common mode output level of capacitor array：
If 1) BN-2Logic 1 is exported, capacitor array needs to occur jump to generate third position output BN-3, capacitor array is total
Mould output level gradually approaches V during Approach by inchmealref/2；
If 2) BN-2Logical zero is exported, capacitor array needs to occur lower jump to generate third position output BN-3, capacitor array is total
Mould output level gradually approaches V during Approach by inchmealref/4。
The invention will be described in further detail with reference to the accompanying drawings and examples：
Embodiment
The successive approximation analog to digital C super low-power consumption capacitor array of the present embodiment is as shown in Figure 2：It is connected to and compares including two groups
(N-2)-bit binary capacitor array of two input terminals of device, every group of (N-2)-bit binary capacitor array pass through switch arrays
Connect voltage reference Vref, Vcm, Gnd；Every group of (N-2)-bit binary capacitor array is by capacitor C0、C1、C2、……CN-2Connection group
At wherein N is natural number；The capacitor C of first group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2One end difference
Connect differential input signal Vip, the switch that the other end of each capacitor passes through in switch arrays respectively is connected to voltage reference Vref,
Vcm, Gnd；The capacitor C of second group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2To be separately connected difference defeated for one end
Enter signal Vin, the switch that the other end passes through in switch arrays respectively is connected to voltage reference Vref, Vcm, Gnd；The output of comparator
End connection Approach by inchmeal logic control element SAR Logic, according to the output of comparator, the SAR Logic is in clock signal
The logic control switched to capacitor array is realized under the action of clk and soc, and generates the numeral output B of ADC0-BN-1。。
Wherein C0=C1, Ci=2Ci-1, i=1~N-2；Reference voltage Vcm=Vref/2.With first group of (N-2)-bit two into
The switch arrays of capacitor array connection processed are first switch array, and first switch array is by switch S0p、S1p、S2p、……S(N-2)p
Composition.The switch arrays connecting with second group of (N-2)-bit binary capacitor array are second switch array, second switch array
By switch S0n、S1n、S2n、……S(N-2)nComposition.
In above-mentioned differential capacitance array structure, takes capacitor top crown to sample, after sampling, compared by comparator
VipAnd VinSize directly generate the output B of highest orderN-1, which does not consume energy consumption, and since highest order is tied in sampling
It is directly generated after beam, reduces the scale of capacitor array, and then reduce power consumption, chip area and cost.
In above-mentioned differential capacitance array structure, in sample phase, switch arrays timing initialization technique, S are taken(N-2)n
=S(N-2)p=" 1 ", S(N-3)n=S(N-4)n=... S1n=S0n=" 0 ", S(N-3)p=S(N-4)p=... S1p=S0p=" 0 ", root
According to BN-1Result change S(N-2)(S(N-2)nOr S(N-2)p) value, export highest bit switch corresponding to biggish capacitor array
Control signal (S(N-2)nOr S(N-2)p) " 0 " is connected to by " 1 ", as shown in Figure 3a, and then compare capacitor array output again
Size generates second-order digit and exports BN-2, which does not also consume energy consumption.
In above-mentioned capacitor array structure, skill is initialized by using top crown sampling and switch arrays logical sequence
Art does not need benchmark during generating highest order and second-order digit exports and provides energy consumption.In addition, generating third digit
Word exports BN-3When, if upper jump (up-transition), capacitor array switch control signal is become from " 100 ... 0 "
" 11/21/2 ... 1/2 ", energy consumption are-CN-2Vref 2/2；If lower jump (down-transition), capacitor array switch control
Signal processed becomes " 1/200 ... 0 " from " 100 ... 0 ", and energy consumption is also-CN-2Vref 2/2.It is controlled by using this new logic
Mode, third bit digital export BN-3Generation do not need yet benchmark provide energy consumption.Fig. 3 gives 4-bit embodiment of the present invention
Specific conversion process and corresponding energy loss.
In above-mentioned capacitor array structure, in the numeral output (B for generating front threeN-1-BN-3) after, in subsequent conversion
Capacitor array takes dull switch logic control mode in the process, and only connection relationship occurs for a capacitor in each clock cycle
Variation, not only simplify logic-controlled sequential, also reduce power consumption.
In above-mentioned capacitor array structure, B is exported according to second-order digitN-2Difference, the common mode of capacitor array exports electricity
Two kinds of trend are presented in flat variation：If 1) BN-2For logic 1, capacitor array need to occur jump (as shown in A and D in Fig. 3) with
It generates third position and exports BN-3, capacitor array common mode output level gradually approaches V during Approach by inchmealref/2；If 2) BN-2For
Logical zero, capacitor array need to occur lower jump (as shown in B and C in Fig. 3) to generate third position output BN-3, capacitor array common mode
Output level gradually approaches V during Approach by inchmealref/4.Fig. 4 compares 4-bit embodiment of the present invention and cuts with traditional dullness
The capacitor array output waveform of mold changing formula, compared to traditional dull switch mode, the common mode of capacitor array provided by the invention is defeated
Out (i.e.：The common mode of comparator inputs) level change range is substantially reduced, can effectively reduce since comparator common mode electrical level becomes
Offset error is inputted caused by changing, conducive to the Low Power Optimization of comparator.
In above-mentioned capacitor array structure, the new logic control mode taken can be effectively reduced to be led by parasitic capacitance
The extra power consumption of cause, Fig. 5 give the schematic diagram of 4-bit inventive embodiments.Between the upper bottom crown and substrate (" 0 ") of capacitor all
There are parasitic capacitances, wherein the parasitic capacitance between bottom crown and substrate is directly connected with benchmark by switch, is switched in capacitor
In the process, the charge and discharge of parasitic capacitance can consume additional energy, wherein highest order capacitor CN-2Weight is maximum, parasitic capacitance
Energy consumption at most, ensure that under the premise of not increasing logical complexity whole by the logical sequence of optimization capacitor array switch
In a A/D conversion process, highest order capacitor CN-2Only occur it is dull lower jump (" 1 " → " 0 " or " 1 " → " 1/2 "), avoid pair
Its parasitic capacitance (2Cpb) recharge, to effectively reduce the power consumption of parasitic capacitance.
In conventional charge reallocation type SAR ADC structure shown in Fig. 1, take capacitor bottom crown sample and it is traditional
Approach by inchmeal mode, C0、C1、C2、……CN-1Form binary capacitor array, C0=C1, Ci=2Ci-1, i=1~N-1；Sip、
Sin(i=0~N-1) is capacitor array switch；VipAnd VinFor differential input signal；VrefFor voltage reference.Entire capacitor array
It is not only larger, area, power consumption and high process cost, and also large-scale capacitor array causes the input of SAR ADC
Capacitor is larger, leads to overall work limited speed.
The comparison (10-bit ADC) of table 1 present invention and conventional charge reallocation structure
It is right in terms of capacitor array scale, number of switches and capacitor array energy consumption in upper table by taking 10-bit ADC as an example
The present invention and conventional charge reallocation structure compare, wherein CptIndicate the top crown of entire capacitor array to substrate
The sum of parasitic capacitance, CpbIndicate parasitic capacitance of the bottom crown of specific capacitance to substrate, CtotIndicate total electricity of entire capacitor array
Capacitance.Capacitor array structure provided by the invention has apparent advantage, and capacitor array scale and number of switches are only tradition electricity
The 25% and 38.5% of lotus reallocation structure, in the case where not considering parasitic capacitance energy consumption, capacitor array energy consumption is only tradition
The 1.2% of structure, in the case where considering parasitic capacitance energy consumption, with Cpt=0.1Ctot,CpbFor=0.15C, the present invention is provided
The energy consumption of capacitor array be only the 1.4% of conventional charge reallocation structure.For details, reference can be made to Fig. 6.
Claims (6)
1. a kind of logic control method of successive approximation analog to digital C super low-power consumption capacitor array, it is characterised in that：
(1) in sample phase, switch arrays timing initialization technique, S are taken(N-2)n=S(N-2)p=" 1 ", S(N-3)n=S(N-4)n
=... S1n=S0n=" 0 ", S(N-3)p=S(N-4)p=... S1p=S0p=" 0 ", according to BN-1Result change S(N-2)(S(N-2)n
Or S(N-2)p) value, export the control signal S of highest bit switch corresponding to biggish capacitor array(N-2)It is connected to by " 1 "
" 0 ", and then compare the size of capacitor array output again, it generates second-order digit and exports BN-2；" 1 " and " 0 " respectively represents accordingly
Switch is by the capacitance connection corresponding to it to VrefAnd Gnd；
(2) by using top crown sampling and switch arrays logical sequence initialization technique, highest order and second are being generated
Benchmark is not needed during numeral output, and energy consumption is provided；B is exported generating third bit digitalN-3When, if upper jump, capacitor
Array switch, which controls signal, becomes " 1 1/2 1/2 ... 1/2 " from " 100 ... 0 ", and energy consumption isIf under
Jump, capacitor array switch control signal become " 1/2 00 ... 0 " from " 100 ... 0 ", and energy consumption is also
" 1/2 " represents respective switch for the capacitance connection corresponding to it to Vcm, Vcm=Vref/2；
For a kind of successive approximation analog to digital C super low-power consumption capacitor array, the successive approximation analog to digital C super low-power consumption capacitor array includes two
Group is connected to (N-2)-bit binary capacitor array of two input terminals of comparator, every group of (N-2)-bit binary capacitor
Array connects voltage reference V by switch arraysref, Vcm, Gnd；Every group of (N-2)-bit binary capacitor array is by capacitor C0、
C1、C2、……CN-2Connection composition, wherein N is natural number；The capacitor C of first group of (N-2)-bit binary capacitor array0、C1、
C2、……CN-2One end be separately connected differential input signal Vip, the other end of each capacitor passes through the switch in switch arrays respectively
It is connected to voltage reference Vref, Vcm, Gnd；The capacitor C of second group of (N-2)-bit binary capacitor array0、C1、C2、……CN-2's
One end is separately connected differential input signal Vin, the switch that the other end passes through in switch arrays respectively is connected to voltage reference Vref,
Vcm, Gnd；The output end of comparator connects Approach by inchmeal logic control element SAR Logic, described according to the output of comparator
Approach by inchmeal logic control element SAR Logic is realized under the action of clock signal clk and soc and is patrolled capacitor array switch
Control is collected, and generates the numeral output B of ADC0-BN-1。
2. logic control method according to claim 1, which is characterized in that in the numeral output B for generating front threeN-1-
BN-3Later, capacitor array takes dull switch logic control mode in subsequent conversion process, in each clock cycle only
The variation of connection relationship occurs for one capacitor.
3. logic control method according to claim 1, which is characterized in that export B according to second-order digitN-2Difference,
Two kinds of trend are presented in the variation of the common mode output level of capacitor array：
If 1) BN-2Logic 1 is exported, capacitor array needs to occur jump to generate third position output BN-3, capacitor array common mode is defeated
Level gradually approaches V during Approach by inchmeal outref/2；
If 2) BN-2Logical zero is exported, capacitor array needs to occur lower jump to generate third position output BN-3, capacitor array common mode is defeated
Level gradually approaches V during Approach by inchmeal outref/4。
4. logic control method according to claim 1, which is characterized in that C0=C1, Ci=2Ci-1, i=1~N-2.
5. logic control method according to claim 1, which is characterized in that with first group of (N-2)-bit binary capacitor
The switch arrays of array connection are first switch array, and first switch array is by switch S0p、S1p、S2p、……S(N-2)pComposition.
6. logic control method according to claim 1, which is characterized in that with second group of (N-2)-bit binary capacitor
The switch arrays of array connection are second switch array, and second switch array is by switch S0n、S1n、S2n、……S(N-2)nComposition.
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| CN108649956A (en) * | 2018-05-15 | 2018-10-12 | 西安电子科技大学 | A kind of gradual approaching A/D converter based on asymmetric differential capacitance array |
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| CN105187065A (en) | 2015-12-23 |
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